arm: imx6ul: Add Engicam GEAM6UL Starter Kit initial support

Boot Log: -------- U-Boot SPL 2016.11-rc2-00144-g922adaa-dirty (Oct 28 2016 - 18:55:30) Trying to boot from MMC1 U-Boot 2016.11-rc2-00144-g922adaa-dirty (Oct 28 2016 - 18:55:30 +0530) CPU: Freescale i.MX6UL rev1.1 528 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 43C Reset cause: POR Model: Engicam GEAM6UL DRAM: 128 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 geam6ul> Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

arm: imx6ul: Add Engicam GEAM6UL Starter Kit initial support
Boot Log: -------- U-Boot SPL 2016.11-rc2-00144-g922adaa-dirty (Oct 28 2016 - 18:55:30) Trying to boot from MMC1 U-Boot 2016.11-rc2-00144-g922adaa-dirty (Oct 28 2016 - 18:55:30 +0530) CPU: Freescale i.MX6UL rev1.1 528 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 43C Reset cause: POR Model: Engicam GEAM6UL DRAM: 128 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 geam6ul> Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki · Stefano Babic
1 parent b8ad70f706
Showing 10 changed files with 594 additions and 1 deletions Side-by-side Diff
arch/arm/cpu/armv7/mx6/Kconfig
arch/arm/dts/Makefile
arch/arm/dts/imx6ul-geam-kit.dts
board/engicam/geam6ul/Kconfig
board/engicam/geam6ul/MAINTAINERS
board/engicam/geam6ul/Makefile
board/engicam/geam6ul/README
board/engicam/geam6ul/geam6ul.c
configs/imx6ul_geam_mmc_defconfig
include/configs/imx6ul_geam.h
@@ -181,6 +181,16 @@
 	select DM_THERMAL
 	select SUPPORT_SPL
  
+config TARGET_MX6UL_GEAM
+	bool "Support Engicam GEAM6UL"
+	select MX6UL
+	select OF_CONTROL
+	select DM
+	select DM_GPIO
+	select DM_MMC
+	select DM_THERMAL
+	select SUPPORT_SPL
+
 config TARGET_MX6ULL_14X14_EVK
 	bool "Support mx6ull_14x14_evk"
 	select MX6ULL
@@ -286,6 +296,7 @@
 source "board/congatec/cgtqmx6eval/Kconfig"
 source "board/el/el6x/Kconfig"
 source "board/embest/mx6boards/Kconfig"
+source "board/engicam/geam6ul/Kconfig"
 source "board/engicam/icorem6/Kconfig"
 source "board/freescale/mx6qarm2/Kconfig"
 source "board/freescale/mx6qsabreauto/Kconfig"
@@ -298,7 +298,8 @@
 dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
 	imx6sll-evk.dtb \
 	imx6dl-icore.dtb \
-	imx6q-icore.dtb
+	imx6q-icore.dtb \
+	imx6ul-geam-kit.dtb
  
 dtb-$(CONFIG_MX7) += imx7-colibri.dtb
  
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "imx6ul.dtsi"
+
+/ {
+	model = "Engicam GEAM6UL";
+	compatible = "engicam,imx6ul-geam", "fsl,imx6ul";
+
+	memory {
+		reg = <0x80000000 0x08000000>;
+	};
+
+	chosen {
+		stdout-path = &uart1;
+	};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	bus-width = <4>;
+	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+	no-1-8-v;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
+			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10059
+			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+		fsl,pins = <
+			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
+			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
+			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
+			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
+			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
+			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+		>;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+		fsl,pins = <
+			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
+			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
+			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
+			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
+			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
+			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
+		>;
+	};
+};
+if TARGET_MX6UL_GEAM
+
+config SYS_BOARD
+	default "geam6ul"
+
+config SYS_VENDOR
+	default "engicam"
+
+config SYS_CONFIG_NAME
+	default "imx6ul_geam"
+
+endif
+GEAM6UL BOARD
+M:	Jagan Teki <jagan@amarulasolutions.com>
+S:	Maintained
+F:	board/engicam/geam6ul
+F:	include/configs/imx6ul_geam.h
+F:	configs/imx6ul_geam_mmc_defconfig
+# Copyright (C) 2016 Amarula Solutions B.V.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := geam6ul.o
+How to use U-Boot on Engicam GEAM6UL Starter Kit:
+-------------------------------------------------
+
+- Configure U-Boot for Engicam GEAM6UL:
+
+$ make mrproper
+$ make imx6ul_geam_mmc_defconfig
+$ make
+
+This will generate the SPL image called SPL and the u-boot-dtb.img.
+
+- Flash the SPL image into the micro SD card:
+
+sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+
+- Flash the u-boot-dtb.img image into the micro SD card:
+
+sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Jumper settings:
+
+MMC Boot: JM3 Closed
+
+- Connect the Serial cable between the Starter Kit and the PC for the console.
+(J28 is the Linux Serial console connector)
+
+- Insert the micro SD card in the board, power it up and U-Boot messages should
+come up.
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <linux/sizes.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/iomux-v3.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+#include <libfdt.h>
+#include <spl.h>
+
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx6-ddr.h>
+
+/* MMC board initialization is needed till adding DM support in SPL */
+#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
+#include <mmc.h>
+#include <fsl_esdhc.h>
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
+	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	/* VSELECT */
+	MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	/* CD */
+	MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* RST_B */
+	MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#define USDHC1_CD_GPIO	IMX_GPIO_NR(1, 1)
+
+struct fsl_esdhc_cfg usdhc_cfg[1] = {
+	{USDHC1_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int i, ret;
+
+	/*
+	* According to the board_mmc_init() the following map is done:
+	* (U-boot device node)    (Physical Port)
+	* mmc0				USDHC1
+	*/
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+			gpio_direction_input(USDHC1_CD_GPIO);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			break;
+		default:
+			printf("Warning - USDHC%d controller not supporting\n",
+			       i + 1);
+			return 0;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret) {
+			printf("Warning: failed to initialize mmc dev %d\n", i);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+#endif /* CONFIG_FSL_ESDHC */
+
+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_addds = 0x00000030,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_b0ds = 0x00000030,
+	.grp_ctlds = 0x00000030,
+	.grp_b1ds = 0x00000030,
+	.grp_ddrpke = 0x00000000,
+	.grp_ddrmode = 0x00020000,
+	.grp_ddr_type = 0x000c0000,
+};
+
+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_dqm0 = 0x00000030,
+	.dram_dqm1 = 0x00000030,
+	.dram_ras = 0x00000030,
+	.dram_cas = 0x00000030,
+	.dram_odt0 = 0x00000030,
+	.dram_odt1 = 0x00000030,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdclk_0 = 0x00000008,
+	.dram_sdqs0 = 0x00000038,
+	.dram_sdqs1 = 0x00000030,
+	.dram_reset = 0x00000030,
+};
+
+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
+	.p0_mpwldectrl0 = 0x00070007,
+	.p0_mpdgctrl0 = 0x41490145,
+	.p0_mprddlctl = 0x40404546,
+	.p0_mpwrdlctl = 0x4040524D,
+};
+
+struct mx6_ddr_sysinfo ddr_sysinfo = {
+	.dsize = 0,
+	.cs_density = 20,
+	.ncs = 1,
+	.cs1_mirror = 0,
+	.rtt_wr = 2,
+	.rtt_nom = 1,		/* RTT_Nom = RZQ/2 */
+	.walat = 1,		/* Write additional latency */
+	.ralat = 5,		/* Read additional latency */
+	.mif3_mode = 3,		/* Command prediction working mode */
+	.bi_on = 1,		/* Bank interleaving enabled */
+	.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
+	.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+	.ddr_type = DDR_TYPE_DDR3,
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+	.mem_speed = 800,
+	.density = 4,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 13,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0xFFFFFFFF, &ccm->CCGR0);
+	writel(0xFFFFFFFF, &ccm->CCGR1);
+	writel(0xFFFFFFFF, &ccm->CCGR2);
+	writel(0xFFFFFFFF, &ccm->CCGR3);
+	writel(0xFFFFFFFF, &ccm->CCGR4);
+	writel(0xFFFFFFFF, &ccm->CCGR5);
+	writel(0xFFFFFFFF, &ccm->CCGR6);
+	writel(0xFFFFFFFF, &ccm->CCGR7);
+}
+
+static void spl_dram_init(void)
+{
+	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+void board_init_f(ulong dummy)
+{
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	ccgr_init();
+
+	/* iomux and setup of i2c */
+	board_early_init_f();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+#endif /* CONFIG_SPL_BUILD */
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_MX6UL_GEAM=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
+CONFIG_DEFAULT_FDT_FILE="imx6ul-geam-kit.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam-kit"
+CONFIG_SYS_PROMPT="geam6ul> "
+CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_HUSH_PARSER=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_SYS_MAXARGS=32
+# CONFIG_CMD_IMLS is not set
+# CONFIG_BLK is not set
+# CONFIG_DM_MMC_OPS is not set
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_LIBFDT=y
+CONFIG_MXC_UART=y
+CONFIG_IMX_THERMAL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ *
+ * Configuration settings for the Engicam GEAM6UL  Starter Kits.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __IMX6UL_GEAM_CONFIG_H
+#define __IMX6UL_GEAM_CONFIG_H
+
+#include <linux/sizes.h>
+#include "mx6_common.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(16 * SZ_1M)
+
+/* Total Size of Environment Sector */
+#define CONFIG_ENV_SIZE			SZ_128K
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Environment */
+#ifndef CONFIG_ENV_IS_NOWHERE
+/* Environment in MMC */
+# if defined(CONFIG_ENV_IS_IN_MMC)
+#  define CONFIG_ENV_OFFSET		0x100000
+# endif
+#endif
+
+/* Default environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttymxc0\0" \
+	"fdt_high=0xffffffff\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_addr=0x87800000\0" \
+	"boot_fdt=try\0" \
+	"mmcdev=0\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev};" \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			"if run loadimage; then " \
+				"run mmcboot; " \
+			"fi; " \
+		   "fi; " \
+	   "fi"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x8000000)
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					CONFIG_SYS_INIT_SP_OFFSET)
+
+/* UART */
+#ifdef CONFIG_MXC_UART
+# define CONFIG_MXC_UART_BASE		UART1_BASE
+#endif
+
+/* MMC */
+#ifdef CONFIG_FSL_USDHC
+# define CONFIG_SYS_MMC_ENV_DEV		0
+# define CONFIG_SYS_FSL_USDHC_NUM	1
+# define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
+#endif
+
+/* SPL */
+#ifdef CONFIG_SPL
+# define CONFIG_SPL_MMC_SUPPORT
+
+# include "imx6_spl.h"
+# ifdef CONFIG_SPL_BUILD
+#  undef CONFIG_DM_GPIO
+#  undef CONFIG_DM_MMC
+# endif
+#endif
+
+#endif /* __IMX6UL_GEAM_CONFIG_H */
...	...	@@ -181,6 +181,16 @@
181	181	select DM_THERMAL
182	182	select SUPPORT_SPL
183	183
	184	+config TARGET_MX6UL_GEAM
	185	+ bool "Support Engicam GEAM6UL"
	186	+ select MX6UL
	187	+ select OF_CONTROL
	188	+ select DM
	189	+ select DM_GPIO
	190	+ select DM_MMC
	191	+ select DM_THERMAL
	192	+ select SUPPORT_SPL
	193	+
184	194	config TARGET_MX6ULL_14X14_EVK
185	195	bool "Support mx6ull_14x14_evk"
186	196	select MX6ULL
...	...	@@ -286,6 +296,7 @@
286	296	source "board/congatec/cgtqmx6eval/Kconfig"
287	297	source "board/el/el6x/Kconfig"
288	298	source "board/embest/mx6boards/Kconfig"
	299	+source "board/engicam/geam6ul/Kconfig"
289	300	source "board/engicam/icorem6/Kconfig"
290	301	source "board/freescale/mx6qarm2/Kconfig"
291	302	source "board/freescale/mx6qsabreauto/Kconfig"
...	...	@@ -298,7 +298,8 @@
298	298	dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
299	299	imx6sll-evk.dtb \
300	300	imx6dl-icore.dtb \
301		- imx6q-icore.dtb
	301	+ imx6q-icore.dtb \
	302	+ imx6ul-geam-kit.dtb
302	303
303	304	dtb-$(CONFIG_MX7) += imx7-colibri.dtb
304	305
	1	+/*
	2	+ * Copyright (C) 2016 Amarula Solutions B.V.
	3	+ * Copyright (C) 2016 Engicam S.r.l.
	4	+ *
	5	+ * This file is dual-licensed: you can use it either under the terms
	6	+ * of the GPL or the X11 license, at your option. Note that this dual
	7	+ * licensing only applies to this file, and not this project as a
	8	+ * whole.
	9	+ *
	10	+ * a) This file is free software; you can redistribute it and/or
	11	+ * modify it under the terms of the GNU General Public License
	12	+ * version 2 as published by the Free Software Foundation.
	13	+ *
	14	+ * This file is distributed in the hope that it will be useful
	15	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	+ * GNU General Public License for more details.
	18	+ *
	19	+ * Or, alternatively
	20	+ *
	21	+ * b) Permission is hereby granted, free of charge, to any person
	22	+ * obtaining a copy of this software and associated documentation
	23	+ * files (the "Software"), to deal in the Software without
	24	+ * restriction, including without limitation the rights to use
	25	+ * copy, modify, merge, publish, distribute, sublicense, and/or
	26	+ * sell copies of the Software, and to permit persons to whom the
	27	+ * Software is furnished to do so, subject to the following
	28	+ * conditions:
	29	+ *
	30	+ * The above copyright notice and this permission notice shall be
	31	+ * included in all copies or substantial portions of the Software.
	32	+ *
	33	+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
	34	+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	35	+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	36	+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	37	+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
	38	+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	39	+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	40	+ * OTHER DEALINGS IN THE SOFTWARE.
	41	+ */
	42	+
	43	+/dts-v1/;
	44	+
	45	+#include <dt-bindings/gpio/gpio.h>
	46	+#include <dt-bindings/input/input.h>
	47	+#include "imx6ul.dtsi"
	48	+
	49	+/ {
	50	+ model = "Engicam GEAM6UL";
	51	+ compatible = "engicam,imx6ul-geam", "fsl,imx6ul";
	52	+
	53	+ memory {
	54	+ reg = <0x80000000 0x08000000>;
	55	+ };
	56	+
	57	+ chosen {
	58	+ stdout-path = &uart1;
	59	+ };
	60	+};
	61	+
	62	+&uart1 {
	63	+ pinctrl-names = "default";
	64	+ pinctrl-0 = <&pinctrl_uart1>;
	65	+ status = "okay";
	66	+};
	67	+
	68	+&usdhc1 {
	69	+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
	70	+ pinctrl-0 = <&pinctrl_usdhc1>;
	71	+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	72	+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	73	+ bus-width = <4>;
	74	+ cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
	75	+ no-1-8-v;
	76	+ status = "okay";
	77	+};
	78	+
	79	+&iomuxc {
	80	+ pinctrl_uart1: uart1grp {
	81	+ fsl,pins = <
	82	+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
	83	+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
	84	+ >;
	85	+ };
	86	+
	87	+ pinctrl_usdhc1: usdhc1grp {
	88	+ fsl,pins = <
	89	+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
	90	+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
	91	+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
	92	+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
	93	+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
	94	+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
	95	+ >;
	96	+ };
	97	+
	98	+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
	99	+ fsl,pins = <
	100	+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
	101	+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
	102	+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
	103	+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
	104	+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
	105	+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
	106	+ >;
	107	+ };
	108	+
	109	+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
	110	+ fsl,pins = <
	111	+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
	112	+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
	113	+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
	114	+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
	115	+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
	116	+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
	117	+ >;
	118	+ };
	119	+};
	1	+if TARGET_MX6UL_GEAM
	2	+
	3	+config SYS_BOARD
	4	+ default "geam6ul"
	5	+
	6	+config SYS_VENDOR
	7	+ default "engicam"
	8	+
	9	+config SYS_CONFIG_NAME
	10	+ default "imx6ul_geam"
	11	+
	12	+endif
	1	+GEAM6UL BOARD
	2	+M: Jagan Teki <jagan@amarulasolutions.com>
	3	+S: Maintained
	4	+F: board/engicam/geam6ul
	5	+F: include/configs/imx6ul_geam.h
	6	+F: configs/imx6ul_geam_mmc_defconfig
	1	+# Copyright (C) 2016 Amarula Solutions B.V.
	2	+#
	3	+# SPDX-License-Identifier: GPL-2.0+
	4	+#
	5	+
	6	+obj-y := geam6ul.o
	1	+How to use U-Boot on Engicam GEAM6UL Starter Kit:
	2	+-------------------------------------------------
	3	+
	4	+- Configure U-Boot for Engicam GEAM6UL:
	5	+
	6	+$ make mrproper
	7	+$ make imx6ul_geam_mmc_defconfig
	8	+$ make
	9	+
	10	+This will generate the SPL image called SPL and the u-boot-dtb.img.
	11	+
	12	+- Flash the SPL image into the micro SD card:
	13	+
	14	+sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
	15	+
	16	+- Flash the u-boot-dtb.img image into the micro SD card:
	17	+
	18	+sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
	19	+
	20	+- Jumper settings:
	21	+
	22	+MMC Boot: JM3 Closed
	23	+
	24	+- Connect the Serial cable between the Starter Kit and the PC for the console.
	25	+(J28 is the Linux Serial console connector)
	26	+
	27	+- Insert the micro SD card in the board, power it up and U-Boot messages should
	28	+come up.
	1	+/*
	2	+ * Copyright (C) 2016 Amarula Solutions B.V.
	3	+ * Copyright (C) 2016 Engicam S.r.l.
	4	+ * Author: Jagan Teki <jagan@amarulasolutions.com>
	5	+ *
	6	+ * SPDX-License-Identifier: GPL-2.0+
	7	+ */
	8	+
	9	+#include <common.h>
	10	+
	11	+#include <asm/io.h>
	12	+#include <asm/gpio.h>
	13	+#include <linux/sizes.h>
	14	+
	15	+#include <asm/arch/clock.h>
	16	+#include <asm/arch/iomux.h>
	17	+#include <asm/arch/mx6-pins.h>
	18	+#include <asm/arch/sys_proto.h>
	19	+#include <asm/imx-common/iomux-v3.h>
	20	+
	21	+DECLARE_GLOBAL_DATA_PTR;
	22	+
	23	+#define UART_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	24	+ PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
	25	+ PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	26	+
	27	+static iomux_v3_cfg_t const uart1_pads[] = {
	28	+ MX6_PAD_UART1_TX_DATA__UART1_DCE_TX \| MUX_PAD_CTRL(UART_PAD_CTRL),
	29	+ MX6_PAD_UART1_RX_DATA__UART1_DCE_RX \| MUX_PAD_CTRL(UART_PAD_CTRL),
	30	+};
	31	+
	32	+int board_early_init_f(void)
	33	+{
	34	+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
	35	+
	36	+ return 0;
	37	+}
	38	+
	39	+int board_init(void)
	40	+{
	41	+ /* Address of boot parameters */
	42	+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	43	+
	44	+ return 0;
	45	+}
	46	+
	47	+int dram_init(void)
	48	+{
	49	+ gd->ram_size = imx_ddr_size();
	50	+
	51	+ return 0;
	52	+}
	53	+
	54	+#ifdef CONFIG_SPL_BUILD
	55	+#include <libfdt.h>
	56	+#include <spl.h>
	57	+
	58	+#include <asm/arch/crm_regs.h>
	59	+#include <asm/arch/mx6-ddr.h>
	60	+
	61	+/* MMC board initialization is needed till adding DM support in SPL */
	62	+#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC)
	63	+#include <mmc.h>
	64	+#include <fsl_esdhc.h>
	65	+
	66	+#define USDHC_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	67	+ PAD_CTL_PUS_22K_UP \| PAD_CTL_SPEED_LOW \| \
	68	+ PAD_CTL_DSE_80ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	69	+
	70	+static iomux_v3_cfg_t const usdhc1_pads[] = {
	71	+ MX6_PAD_SD1_CLK__USDHC1_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	72	+ MX6_PAD_SD1_CMD__USDHC1_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	73	+ MX6_PAD_SD1_DATA0__USDHC1_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	74	+ MX6_PAD_SD1_DATA1__USDHC1_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	75	+ MX6_PAD_SD1_DATA2__USDHC1_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	76	+ MX6_PAD_SD1_DATA3__USDHC1_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	77	+
	78	+ /* VSELECT */
	79	+ MX6_PAD_GPIO1_IO05__USDHC1_VSELECT \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	80	+ /* CD */
	81	+ MX6_PAD_UART1_RTS_B__GPIO1_IO19 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	82	+ /* RST_B */
	83	+ MX6_PAD_GPIO1_IO09__GPIO1_IO09 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	84	+};
	85	+
	86	+#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
	87	+
	88	+struct fsl_esdhc_cfg usdhc_cfg[1] = {
	89	+ {USDHC1_BASE_ADDR, 0, 4},
	90	+};
	91	+
	92	+int board_mmc_getcd(struct mmc *mmc)
	93	+{
	94	+ struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
	95	+ int ret = 0;
	96	+
	97	+ switch (cfg->esdhc_base) {
	98	+ case USDHC1_BASE_ADDR:
	99	+ ret = !gpio_get_value(USDHC1_CD_GPIO);
	100	+ break;
	101	+ }
	102	+
	103	+ return ret;
	104	+}
	105	+
	106	+int board_mmc_init(bd_t *bis)
	107	+{
	108	+ int i, ret;
	109	+
	110	+ /*
	111	+ * According to the board_mmc_init() the following map is done:
	112	+ * (U-boot device node) (Physical Port)
	113	+ * mmc0 USDHC1
	114	+ */
	115	+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
	116	+ switch (i) {
	117	+ case 0:
	118	+ imx_iomux_v3_setup_multiple_pads(
	119	+ usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
	120	+ gpio_direction_input(USDHC1_CD_GPIO);
	121	+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
	122	+ break;
	123	+ default:
	124	+ printf("Warning - USDHC%d controller not supporting\n",
	125	+ i + 1);
	126	+ return 0;
	127	+ }
	128	+
	129	+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
	130	+ if (ret) {
	131	+ printf("Warning: failed to initialize mmc dev %d\n", i);
	132	+ return ret;
	133	+ }
	134	+ }
	135	+
	136	+ return 0;
	137	+}
	138	+#endif /* CONFIG_FSL_ESDHC */
	139	+
	140	+static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
	141	+ .grp_addds = 0x00000030,
	142	+ .grp_ddrmode_ctl = 0x00020000,
	143	+ .grp_b0ds = 0x00000030,
	144	+ .grp_ctlds = 0x00000030,
	145	+ .grp_b1ds = 0x00000030,
	146	+ .grp_ddrpke = 0x00000000,
	147	+ .grp_ddrmode = 0x00020000,
	148	+ .grp_ddr_type = 0x000c0000,
	149	+};
	150	+
	151	+static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
	152	+ .dram_dqm0 = 0x00000030,
	153	+ .dram_dqm1 = 0x00000030,
	154	+ .dram_ras = 0x00000030,
	155	+ .dram_cas = 0x00000030,
	156	+ .dram_odt0 = 0x00000030,
	157	+ .dram_odt1 = 0x00000030,
	158	+ .dram_sdba2 = 0x00000000,
	159	+ .dram_sdclk_0 = 0x00000008,
	160	+ .dram_sdqs0 = 0x00000038,
	161	+ .dram_sdqs1 = 0x00000030,
	162	+ .dram_reset = 0x00000030,
	163	+};
	164	+
	165	+static struct mx6_mmdc_calibration mx6_mmcd_calib = {
	166	+ .p0_mpwldectrl0 = 0x00070007,
	167	+ .p0_mpdgctrl0 = 0x41490145,
	168	+ .p0_mprddlctl = 0x40404546,
	169	+ .p0_mpwrdlctl = 0x4040524D,
	170	+};
	171	+
	172	+struct mx6_ddr_sysinfo ddr_sysinfo = {
	173	+ .dsize = 0,
	174	+ .cs_density = 20,
	175	+ .ncs = 1,
	176	+ .cs1_mirror = 0,
	177	+ .rtt_wr = 2,
	178	+ .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
	179	+ .walat = 1, /* Write additional latency */
	180	+ .ralat = 5, /* Read additional latency */
	181	+ .mif3_mode = 3, /* Command prediction working mode */
	182	+ .bi_on = 1, /* Bank interleaving enabled */
	183	+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
	184	+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
	185	+ .ddr_type = DDR_TYPE_DDR3,
	186	+};
	187	+
	188	+static struct mx6_ddr3_cfg mem_ddr = {
	189	+ .mem_speed = 800,
	190	+ .density = 4,
	191	+ .width = 16,
	192	+ .banks = 8,
	193	+ .rowaddr = 13,
	194	+ .coladdr = 10,
	195	+ .pagesz = 2,
	196	+ .trcd = 1375,
	197	+ .trcmin = 4875,
	198	+ .trasmin = 3500,
	199	+};
	200	+
	201	+static void ccgr_init(void)
	202	+{
	203	+ struct mxc_ccm_reg ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	204	+
	205	+ writel(0xFFFFFFFF, &ccm->CCGR0);
	206	+ writel(0xFFFFFFFF, &ccm->CCGR1);
	207	+ writel(0xFFFFFFFF, &ccm->CCGR2);
	208	+ writel(0xFFFFFFFF, &ccm->CCGR3);
	209	+ writel(0xFFFFFFFF, &ccm->CCGR4);
	210	+ writel(0xFFFFFFFF, &ccm->CCGR5);
	211	+ writel(0xFFFFFFFF, &ccm->CCGR6);
	212	+ writel(0xFFFFFFFF, &ccm->CCGR7);
	213	+}
	214	+
	215	+static void spl_dram_init(void)
	216	+{
	217	+ mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
	218	+ mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
	219	+}
	220	+
	221	+void board_init_f(ulong dummy)
	222	+{
	223	+ /* setup AIPS and disable watchdog */
	224	+ arch_cpu_init();
	225	+
	226	+ ccgr_init();
	227	+
	228	+ /* iomux and setup of i2c */
	229	+ board_early_init_f();
	230	+
	231	+ /* setup GP timer */
	232	+ timer_init();
	233	+
	234	+ /* UART clocks enabled and gd valid - init serial console */
	235	+ preloader_console_init();
	236	+
	237	+ /* DDR initialization */
	238	+ spl_dram_init();
	239	+
	240	+ /* Clear the BSS. */
	241	+ memset(__bss_start, 0, __bss_end - __bss_start);
	242	+
	243	+ /* load/boot image from boot device */
	244	+ board_init_r(NULL, 0);
	245	+}
	246	+#endif /* CONFIG_SPL_BUILD */
	1	+CONFIG_ARM=y
	2	+CONFIG_ARCH_MX6=y
	3	+CONFIG_TARGET_MX6UL_GEAM=y
	4	+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC"
	5	+CONFIG_DEFAULT_FDT_FILE="imx6ul-geam-kit.dtb"
	6	+CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam-kit"
	7	+CONFIG_SYS_PROMPT="geam6ul> "
	8	+CONFIG_SPL=y
	9	+CONFIG_BOOTDELAY=3
	10	+CONFIG_BOARD_EARLY_INIT_F=y
	11	+CONFIG_DISPLAY_CPUINFO=y
	12	+CONFIG_HUSH_PARSER=y
	13	+CONFIG_AUTO_COMPLETE=y
	14	+CONFIG_SYS_MAXARGS=32
	15	+# CONFIG_CMD_IMLS is not set
	16	+# CONFIG_BLK is not set
	17	+# CONFIG_DM_MMC_OPS is not set
	18	+CONFIG_CMD_BOOTZ=y
	19	+CONFIG_CMD_GPIO=y
	20	+CONFIG_CMD_MEMTEST=y
	21	+CONFIG_CMD_MMC=y
	22	+CONFIG_CMD_CACHE=y
	23	+CONFIG_CMD_EXT2=y
	24	+CONFIG_CMD_EXT4=y
	25	+CONFIG_CMD_EXT4_WRITE=y
	26	+CONFIG_CMD_FAT=y
	27	+CONFIG_CMD_FS_GENERIC=y
	28	+CONFIG_OF_LIBFDT=y
	29	+CONFIG_MXC_UART=y
	30	+CONFIG_IMX_THERMAL=y
	31	+CONFIG_PINCTRL=y
	32	+CONFIG_PINCTRL_IMX6=y
	33	+CONFIG_SPL_LIBDISK_SUPPORT=y
	34	+CONFIG_SPL_LIBCOMMON_SUPPORT=y
	35	+CONFIG_SPL_LIBGENERIC_SUPPORT=y
	36	+CONFIG_SPL_SERIAL_SUPPORT=y
	37	+CONFIG_SPL_GPIO_SUPPORT=y
	38	+CONFIG_SPL_WATCHDOG_SUPPORT=y
	39	+CONFIG_SPL_EXT_SUPPORT=y
	1	+/*
	2	+ * Copyright (C) 2016 Amarula Solutions B.V.
	3	+ * Copyright (C) 2016 Engicam S.r.l.
	4	+ *
	5	+ * Configuration settings for the Engicam GEAM6UL Starter Kits.
	6	+ *
	7	+ * SPDX-License-Identifier: GPL-2.0+
	8	+ */
	9	+
	10	+#ifndef __IMX6UL_GEAM_CONFIG_H
	11	+#define __IMX6UL_GEAM_CONFIG_H
	12	+
	13	+#include <linux/sizes.h>
	14	+#include "mx6_common.h"
	15	+
	16	+/* Size of malloc() pool */
	17	+#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
	18	+
	19	+/* Total Size of Environment Sector */
	20	+#define CONFIG_ENV_SIZE SZ_128K
	21	+
	22	+/* Allow to overwrite serial and ethaddr */
	23	+#define CONFIG_ENV_OVERWRITE
	24	+
	25	+/* Environment */
	26	+#ifndef CONFIG_ENV_IS_NOWHERE
	27	+/* Environment in MMC */
	28	+# if defined(CONFIG_ENV_IS_IN_MMC)
	29	+# define CONFIG_ENV_OFFSET 0x100000
	30	+# endif
	31	+#endif
	32	+
	33	+/* Default environment */
	34	+#define CONFIG_EXTRA_ENV_SETTINGS \
	35	+ "script=boot.scr\0" \
	36	+ "image=zImage\0" \
	37	+ "console=ttymxc0\0" \
	38	+ "fdt_high=0xffffffff\0" \
	39	+ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
	40	+ "fdt_addr=0x87800000\0" \
	41	+ "boot_fdt=try\0" \
	42	+ "mmcdev=0\0" \
	43	+ "mmcpart=1\0" \
	44	+ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
	45	+ "mmcautodetect=yes\0" \
	46	+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
	47	+ "root=${mmcroot}\0" \
	48	+ "loadbootscript=" \
	49	+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
	50	+ "bootscript=echo Running bootscript from mmc ...; " \
	51	+ "source\0" \
	52	+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
	53	+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
	54	+ "mmcboot=echo Booting from mmc ...; " \
	55	+ "run mmcargs; " \
	56	+ "if test ${boot_fdt} = yes \|\| test ${boot_fdt} = try; then " \
	57	+ "if run loadfdt; then " \
	58	+ "bootz ${loadaddr} - ${fdt_addr}; " \
	59	+ "else " \
	60	+ "if test ${boot_fdt} = try; then " \
	61	+ "bootz; " \
	62	+ "else " \
	63	+ "echo WARN: Cannot load the DT; " \
	64	+ "fi; " \
	65	+ "fi; " \
	66	+ "else " \
	67	+ "bootz; " \
	68	+ "fi\0"
	69	+
	70	+#define CONFIG_BOOTCOMMAND \
	71	+ "mmc dev ${mmcdev};" \
	72	+ "mmc dev ${mmcdev}; if mmc rescan; then " \
	73	+ "if run loadbootscript; then " \
	74	+ "run bootscript; " \
	75	+ "else " \
	76	+ "if run loadimage; then " \
	77	+ "run mmcboot; " \
	78	+ "fi; " \
	79	+ "fi; " \
	80	+ "fi"
	81	+
	82	+/* Miscellaneous configurable options */
	83	+#define CONFIG_SYS_MEMTEST_START 0x80000000
	84	+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000)
	85	+
	86	+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
	87	+#define CONFIG_SYS_HZ 1000
	88	+
	89	+/* Physical Memory Map */
	90	+#define CONFIG_NR_DRAM_BANKS 1
	91	+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
	92	+
	93	+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
	94	+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
	95	+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
	96	+
	97	+#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
	98	+ GENERATED_GBL_DATA_SIZE)
	99	+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	100	+ CONFIG_SYS_INIT_SP_OFFSET)
	101	+
	102	+/* UART */
	103	+#ifdef CONFIG_MXC_UART
	104	+# define CONFIG_MXC_UART_BASE UART1_BASE
	105	+#endif
	106	+
	107	+/* MMC */
	108	+#ifdef CONFIG_FSL_USDHC
	109	+# define CONFIG_SYS_MMC_ENV_DEV 0
	110	+# define CONFIG_SYS_FSL_USDHC_NUM 1
	111	+# define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
	112	+#endif
	113	+
	114	+/* SPL */
	115	+#ifdef CONFIG_SPL
	116	+# define CONFIG_SPL_MMC_SUPPORT
	117	+
	118	+# include "imx6_spl.h"
	119	+# ifdef CONFIG_SPL_BUILD
	120	+# undef CONFIG_DM_GPIO
	121	+# undef CONFIG_DM_MMC
	122	+# endif
	123	+#endif
	124	+
	125	+#endif /* __IMX6UL_GEAM_CONFIG_H */