Commit a5f88877af9ae7d9f462efcbc5cb6fd7be9af106

Authored by Stefan Roese
1 parent a9fc5a247c

arm: mvebu: Add runtime boot-device detection

This patch adds runtime boot-device detection to SPL U-Boot.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Kevin Smith <kevin.smith@elecsyscorp.com>

Showing 2 changed files with 39 additions and 7 deletions Side-by-side Diff

arch/arm/mach-mvebu/include/mach/soc.h
... ... @@ -99,14 +99,24 @@
99 99 #if defined(CONFIG_ARMADA_38X)
100 100 /* SAR values for Armada 38x */
101 101 #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600))
  102 +
102 103 #define SAR_CPU_FREQ_OFFS 10
103 104 #define SAR_CPU_FREQ_MASK (0x1f << SAR_CPU_FREQ_OFFS)
104 105 #define SAR_BOOT_DEVICE_OFFS 4
105 106 #define SAR_BOOT_DEVICE_MASK (0x1f << SAR_BOOT_DEVICE_OFFS)
  107 +
  108 +#define BOOT_DEV_SEL_OFFS 4
  109 +#define BOOT_DEV_SEL_MASK (0x1f << BOOT_DEV_SEL_OFFS)
  110 +
  111 +#define BOOT_FROM_UART 0x28
  112 +#define BOOT_FROM_SPI 0x32
  113 +#define BOOT_FROM_MMC 0x30
  114 +#define BOOT_FROM_MMC_ALT 0x31
106 115 #else
107 116 /* SAR values for Armada XP */
108 117 #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230))
109 118 #define CONFIG_SAR2_REG (MVEBU_REGISTER(0x18234))
  119 +
110 120 #define SAR_CPU_FREQ_OFFS 21
111 121 #define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS)
112 122 #define SAR_FFC_FREQ_OFFS 24
... ... @@ -115,6 +125,12 @@
115 125 #define SAR2_CPU_FREQ_MASK (0x1 << SAR2_CPU_FREQ_OFFS)
116 126 #define SAR_BOOT_DEVICE_OFFS 5
117 127 #define SAR_BOOT_DEVICE_MASK (0xf << SAR_BOOT_DEVICE_OFFS)
  128 +
  129 +#define BOOT_DEV_SEL_OFFS 5
  130 +#define BOOT_DEV_SEL_MASK (0xf << BOOT_DEV_SEL_OFFS)
  131 +
  132 +#define BOOT_FROM_UART 0x2
  133 +#define BOOT_FROM_SPI 0x3
118 134 #endif
119 135  
120 136 #endif /* _MVEBU_SOC_H */
arch/arm/mach-mvebu/spl.c
1 1 /*
2   - * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
  2 + * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
3 3 *
4 4 * SPDX-License-Identifier: GPL-2.0+
5 5 */
6 6  
7 7  
... ... @@ -15,14 +15,30 @@
15 15  
16 16 DECLARE_GLOBAL_DATA_PTR;
17 17  
18   -u32 spl_boot_device(void)
  18 +static u32 get_boot_device(void)
19 19 {
20   -#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT)
21   - return BOOT_DEVICE_SPI;
  20 + u32 val;
  21 + u32 boot_device;
  22 +
  23 + val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */
  24 + boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS;
  25 + switch (boot_device) {
  26 +#ifdef CONFIG_SPL_MMC_SUPPORT
  27 + case BOOT_FROM_MMC:
  28 + case BOOT_FROM_MMC_ALT:
  29 + return BOOT_DEVICE_MMC1;
22 30 #endif
23   -#if defined(CONFIG_SPL_MMC_SUPPORT)
24   - return BOOT_DEVICE_MMC1;
25   -#endif
  31 + case BOOT_FROM_UART:
  32 + return BOOT_DEVICE_UART;
  33 + case BOOT_FROM_SPI:
  34 + default:
  35 + return BOOT_DEVICE_SPI;
  36 + };
  37 +}
  38 +
  39 +u32 spl_boot_device(void)
  40 +{
  41 + return get_boot_device();
26 42 }
27 43  
28 44 #ifdef CONFIG_SPL_MMC_SUPPORT