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Commit a605ea7e8322000d99a890d3173748f62ccb8549

Authored by Dirk Eibach
Committed by Stefan Roese
1 parent c163f4478c
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ppc4xx: Add Io and IoCon 405EP board support 

Board support for the Guntermann & Drunck CATCenter Io.
Board support for the Guntermann & Drunck IoCon.

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>

Showing 13 changed files with 1544 additions and 0 deletions Side-by-side Diff

... ... @@ -144,6 +144,8 @@
144 144 dlvision PPC405EP
145 145 gdppc440etx PPC440EP/GR
146 146 intip PPC460EX
  147 + io PPC405EP
  148 + iocon PPC405EP
147 149 neo PPC405EP
148 150  
149 151 Dave Ellis <DGE@sixnetio.com>
board/gdsys/405ep/405ep.c
Diff comments   View file @ a605ea7
  1 +/*
  2 + * (C) Copyright 2010
  3 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#include <common.h>
  25 +#include <command.h>
  26 +#include <asm/processor.h>
  27 +#include <asm/io.h>
  28 +#include <asm/ppc4xx-gpio.h>
  29 +
  30 +#include "../common/fpga.h"
  31 +
  32 +#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
  33 +#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
  34 +#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
  35 +
  36 +#define REFLECTION_TESTPATTERN 0xdede
  37 +#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
  38 +
  39 +int board_early_init_f(void)
  40 +{
  41 + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
  42 + mtdcr(UIC0ER, 0x00000000); /* disable all ints */
  43 + mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
  44 + mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
  45 + mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
  46 + mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
  47 + mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
  48 +
  49 + /*
  50 + * EBC Configuration Register: set ready timeout to 512 ebc-clks
  51 + * -> ca. 15 us
  52 + */
  53 + mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
  54 +
  55 + /*
  56 + * setup io-latches for reset
  57 + */
  58 + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
  59 + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
  60 +
  61 + /*
  62 + * set "startup-finished"-gpios
  63 + */
  64 + gpio_write_bit(21, 0);
  65 + gpio_write_bit(22, 1);
  66 +
  67 + /*
  68 + * wait for fpga-done
  69 + * fail ungraceful if fpga is not configuring properly
  70 + */
  71 + while (!(in_le16((void *)LATCH2_BASE) & 0x0010))
  72 + ;
  73 +
  74 + /*
  75 + * setup io-latches for boot (stop reset)
  76 + */
  77 + udelay(10);
  78 + out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
  79 + out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
  80 +
  81 + /*
  82 + * wait for fpga out of reset
  83 + * fail ungraceful if fpga is not working properly
  84 + */
  85 + while (1) {
  86 + fpga_set_reg(CONFIG_SYS_FPGA_RFL_LOW, REFLECTION_TESTPATTERN);
  87 + if (fpga_get_reg(CONFIG_SYS_FPGA_RFL_HIGH) ==
  88 + REFLECTION_TESTPATTERN_INV)
  89 + break;
  90 + }
  91 +
  92 + return 0;
  93 +}
board/gdsys/405ep/Makefile
Diff comments   View file @ a605ea7
  1 +#
  2 +# (C) Copyright 2007
  3 +# Stefan Roese, DENX Software Engineering, sr@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +include $(TOPDIR)/config.mk
  25 +
  26 +LIB = $(obj)lib$(BOARD).a
  27 +
  28 +COBJS-$(CONFIG_IO) += io.o
  29 +COBJS-$(CONFIG_IOCON) += iocon.o
  30 +
  31 +COBJS := $(BOARD).o $(COBJS-y)
  32 +SOBJS =
  33 +
  34 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
  35 +OBJS := $(addprefix $(obj),$(COBJS))
  36 +SOBJS := $(addprefix $(obj),$(SOBJS))
  37 +
  38 +$(LIB): $(OBJS) $(SOBJS)
  39 + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
  40 +
  41 +clean:
  42 + rm -f $(SOBJS) $(OBJS)
  43 +
  44 +distclean: clean
  45 + rm -f $(LIB) core *.bak $(obj).depend
  46 +
  47 +#########################################################################
  48 +
  49 +# defines $(obj).depend target
  50 +include $(SRCTREE)/rules.mk
  51 +
  52 +sinclude $(obj).depend
  53 +
  54 +#########################################################################
board/gdsys/405ep/io.c
Diff comments   View file @ a605ea7
  1 +/*
  2 + * (C) Copyright 2010
  3 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#include <common.h>
  25 +#include <command.h>
  26 +#include <asm/processor.h>
  27 +#include <asm/io.h>
  28 +#include <asm/ppc4xx-gpio.h>
  29 +
  30 +#include <miiphy.h>
  31 +
  32 +#include "../common/fpga.h"
  33 +
  34 +#define PHYREG_CONTROL 0
  35 +#define PHYREG_PAGE_ADDRESS 22
  36 +#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
  37 +#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
  38 +
  39 +enum {
  40 + REG_VERSIONS = 0x0002,
  41 + REG_FPGA_FEATURES = 0x0004,
  42 + REG_FPGA_VERSION = 0x0006,
  43 + REG_QUAD_SERDES_RESET = 0x0012,
  44 +};
  45 +
  46 +enum {
  47 + UNITTYPE_CCD_SWITCH = 1,
  48 +};
  49 +
  50 +enum {
  51 + HWVER_100 = 0,
  52 + HWVER_110 = 1,
  53 + HWVER_121 = 2,
  54 + HWVER_122 = 3,
  55 +};
  56 +
  57 +int configure_gbit_phy(unsigned char addr)
  58 +{
  59 + unsigned short value;
  60 +
  61 + /* select page 2 */
  62 + if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  63 + PHYREG_PAGE_ADDRESS, 0x0002))
  64 + goto err_out;
  65 + /* disable SGMII autonegotiation */
  66 + if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  67 + PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2, 0x800a))
  68 + goto err_out;
  69 + /* select page 0 */
  70 + if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  71 + PHYREG_PAGE_ADDRESS, 0x0000))
  72 + goto err_out;
  73 + /* switch from powerdown to normal operation */
  74 + if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  75 + PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, &value))
  76 + goto err_out;
  77 + if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  78 + PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, value & ~0x0004))
  79 + goto err_out;
  80 + /* reset phy so settings take effect */
  81 + if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
  82 + PHYREG_CONTROL, 0x9140))
  83 + goto err_out;
  84 +
  85 + return 0;
  86 +
  87 +err_out:
  88 + printf("Error writing to the PHY addr=%02x\n", addr);
  89 + return -1;
  90 +}
  91 +
  92 +/*
  93 + * Check Board Identity:
  94 + */
  95 +int checkboard(void)
  96 +{
  97 + char *s = getenv("serial#");
  98 + u16 versions = fpga_get_reg(REG_VERSIONS);
  99 + u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
  100 + u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
  101 + unsigned unit_type;
  102 + unsigned hardware_version;
  103 + unsigned feature_channels;
  104 + unsigned feature_expansion;
  105 +
  106 + unit_type = (versions & 0xf000) >> 12;
  107 + hardware_version = versions & 0x000f;
  108 + feature_channels = fpga_features & 0x007f;
  109 + feature_expansion = fpga_features & (1<<15);
  110 +
  111 + printf("Board: ");
  112 +
  113 + printf("CATCenter Io");
  114 +
  115 + if (s != NULL) {
  116 + puts(", serial# ");
  117 + puts(s);
  118 + }
  119 + puts("\n ");
  120 +
  121 + switch (unit_type) {
  122 + case UNITTYPE_CCD_SWITCH:
  123 + printf("CCD-Switch");
  124 + break;
  125 +
  126 + default:
  127 + printf("UnitType %d(not supported)", unit_type);
  128 + break;
  129 + }
  130 +
  131 + switch (hardware_version) {
  132 + case HWVER_100:
  133 + printf(" HW-Ver 1.00\n");
  134 + break;
  135 +
  136 + case HWVER_110:
  137 + printf(" HW-Ver 1.10\n");
  138 + break;
  139 +
  140 + case HWVER_121:
  141 + printf(" HW-Ver 1.21\n");
  142 + break;
  143 +
  144 + case HWVER_122:
  145 + printf(" HW-Ver 1.22\n");
  146 + break;
  147 +
  148 + default:
  149 + printf(" HW-Ver %d(not supported)\n",
  150 + hardware_version);
  151 + break;
  152 + }
  153 +
  154 + printf(" FPGA V %d.%02d, features:",
  155 + fpga_version / 100, fpga_version % 100);
  156 +
  157 + printf(" %d channel(s)", feature_channels);
  158 +
  159 + printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
  160 +
  161 + return 0;
  162 +}
  163 +
  164 +/*
  165 + * setup Gbit PHYs
  166 + */
  167 +int last_stage_init(void)
  168 +{
  169 + unsigned int k;
  170 +
  171 + miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
  172 + bb_miiphy_read, bb_miiphy_write);
  173 +
  174 + for (k = 0; k < 32; ++k)
  175 + configure_gbit_phy(k);
  176 +
  177 + /* take fpga serdes blocks out of reset */
  178 + fpga_set_reg(REG_QUAD_SERDES_RESET, 0);
  179 +
  180 + return 0;
  181 +}
board/gdsys/405ep/iocon.c
Diff comments   View file @ a605ea7
  1 +/*
  2 + * (C) Copyright 2010
  3 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#include <common.h>
  25 +#include <command.h>
  26 +#include <asm/processor.h>
  27 +#include <asm/io.h>
  28 +#include <asm/ppc4xx-gpio.h>
  29 +
  30 +#include "../common/fpga.h"
  31 +#include "../common/osd.h"
  32 +
  33 +enum {
  34 + REG_VERSIONS = 0x0002,
  35 + REG_FPGA_VERSION = 0x0004,
  36 + REG_FPGA_FEATURES = 0x0006,
  37 +};
  38 +
  39 +enum {
  40 + UNITTYPE_MAIN_SERVER = 0,
  41 + UNITTYPE_MAIN_USER = 1,
  42 + UNITTYPE_VIDEO_SERVER = 2,
  43 + UNITTYPE_VIDEO_USER = 3,
  44 +};
  45 +
  46 +enum {
  47 + HWVER_100 = 0,
  48 + HWVER_104 = 1,
  49 + HWVER_110 = 2,
  50 +};
  51 +
  52 +enum {
  53 + COMPRESSION_NONE = 0,
  54 + COMPRESSION_TYPE1_DELTA,
  55 +};
  56 +
  57 +enum {
  58 + AUDIO_NONE = 0,
  59 + AUDIO_TX = 1,
  60 + AUDIO_RX = 2,
  61 + AUDIO_RXTX = 3,
  62 +};
  63 +
  64 +enum {
  65 + SYSCLK_147456 = 0,
  66 +};
  67 +
  68 +enum {
  69 + RAM_DDR2_32 = 0,
  70 +};
  71 +
  72 +/*
  73 + * Check Board Identity:
  74 + */
  75 +int checkboard(void)
  76 +{
  77 + char *s = getenv("serial#");
  78 + u16 versions = fpga_get_reg(REG_VERSIONS);
  79 + u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
  80 + u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
  81 + unsigned unit_type;
  82 + unsigned hardware_version;
  83 + unsigned feature_compression;
  84 + unsigned feature_osd;
  85 + unsigned feature_audio;
  86 + unsigned feature_sysclock;
  87 + unsigned feature_ramconfig;
  88 + unsigned feature_carriers;
  89 + unsigned feature_video_channels;
  90 +
  91 + unit_type = (versions & 0xf000) >> 12;
  92 + hardware_version = versions & 0x000f;
  93 + feature_compression = (fpga_features & 0xe000) >> 13;
  94 + feature_osd = fpga_features & (1<<11);
  95 + feature_audio = (fpga_features & 0x0600) >> 9;
  96 + feature_sysclock = (fpga_features & 0x0180) >> 7;
  97 + feature_ramconfig = (fpga_features & 0x0060) >> 5;
  98 + feature_carriers = (fpga_features & 0x000c) >> 2;
  99 + feature_video_channels = fpga_features & 0x0003;
  100 +
  101 + printf("Board: ");
  102 +
  103 + printf("IoCon");
  104 +
  105 + if (s != NULL) {
  106 + puts(", serial# ");
  107 + puts(s);
  108 + }
  109 + puts("\n ");
  110 +
  111 + switch (unit_type) {
  112 + case UNITTYPE_MAIN_USER:
  113 + printf("Mainchannel");
  114 + break;
  115 +
  116 + case UNITTYPE_VIDEO_USER:
  117 + printf("Videochannel");
  118 + break;
  119 +
  120 + default:
  121 + printf("UnitType %d(not supported)", unit_type);
  122 + break;
  123 + }
  124 +
  125 + switch (hardware_version) {
  126 + case HWVER_100:
  127 + printf(" HW-Ver 1.00\n");
  128 + break;
  129 +
  130 + case HWVER_104:
  131 + printf(" HW-Ver 1.04\n");
  132 + break;
  133 +
  134 + case HWVER_110:
  135 + printf(" HW-Ver 1.10\n");
  136 + break;
  137 +
  138 + default:
  139 + printf(" HW-Ver %d(not supported)\n",
  140 + hardware_version);
  141 + break;
  142 + }
  143 +
  144 + printf(" FPGA V %d.%02d, features:",
  145 + fpga_version / 100, fpga_version % 100);
  146 +
  147 +
  148 + switch (feature_compression) {
  149 + case COMPRESSION_NONE:
  150 + printf(" no compression");
  151 + break;
  152 +
  153 + case COMPRESSION_TYPE1_DELTA:
  154 + printf(" type1-deltacompression");
  155 + break;
  156 +
  157 + default:
  158 + printf(" compression %d(not supported)", feature_compression);
  159 + break;
  160 + }
  161 +
  162 + printf(", %sosd", feature_osd ? "" : "no ");
  163 +
  164 + switch (feature_audio) {
  165 + case AUDIO_NONE:
  166 + printf(", no audio");
  167 + break;
  168 +
  169 + case AUDIO_TX:
  170 + printf(", audio tx");
  171 + break;
  172 +
  173 + case AUDIO_RX:
  174 + printf(", audio rx");
  175 + break;
  176 +
  177 + case AUDIO_RXTX:
  178 + printf(", audio rx+tx");
  179 + break;
  180 +
  181 + default:
  182 + printf(", audio %d(not supported)", feature_audio);
  183 + break;
  184 + }
  185 +
  186 + puts(",\n ");
  187 +
  188 + switch (feature_sysclock) {
  189 + case SYSCLK_147456:
  190 + printf("clock 147.456 MHz");
  191 + break;
  192 +
  193 + default:
  194 + printf("clock %d(not supported)", feature_sysclock);
  195 + break;
  196 + }
  197 +
  198 + switch (feature_ramconfig) {
  199 + case RAM_DDR2_32:
  200 + printf(", RAM 32 bit DDR2");
  201 + break;
  202 +
  203 + default:
  204 + printf(", RAM %d(not supported)", feature_ramconfig);
  205 + break;
  206 + }
  207 +
  208 + printf(", %d carrier(s)", feature_carriers);
  209 +
  210 + printf(", %d video channel(s)\n", feature_video_channels);
  211 +
  212 + return 0;
  213 +}
  214 +
  215 +int last_stage_init(void)
  216 +{
  217 + return osd_probe();
  218 +}
  219 +
  220 +/*
  221 + * provide access to fpga gpios (for I2C bitbang)
  222 + */
  223 +void fpga_gpio_set(int pin)
  224 +{
  225 + out_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x18), pin);
  226 +}
  227 +
  228 +void fpga_gpio_clear(int pin)
  229 +{
  230 + out_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x16), pin);
  231 +}
  232 +
  233 +int fpga_gpio_get(int pin)
  234 +{
  235 + return in_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x14)) & pin;
  236 +}
board/gdsys/common/Makefile
Diff comments   View file @ a605ea7
  1 +#
  2 +# (C) Copyright 2007
  3 +# Stefan Roese, DENX Software Engineering, sr@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +include $(TOPDIR)/config.mk
  25 +
  26 +ifneq ($(OBJTREE),$(SRCTREE))
  27 +$(shell mkdir -p $(obj)board/$(VENDOR)/common)
  28 +endif
  29 +
  30 +LIB = $(obj)lib$(VENDOR).a
  31 +
  32 +COBJS-$(CONFIG_IO) += miiphybb.o
  33 +COBJS-$(CONFIG_IOCON) += osd.o
  34 +
  35 +COBJS := $(COBJS-y)
  36 +SOBJS =
  37 +
  38 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
  39 +OBJS := $(addprefix $(obj),$(COBJS))
  40 +SOBJS := $(addprefix $(obj),$(SOBJS))
  41 +
  42 +$(LIB): $(OBJS) $(SOBJS)
  43 + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
  44 +
  45 +clean:
  46 + rm -f $(SOBJS) $(OBJS)
  47 +
  48 +distclean: clean
  49 + rm -f $(LIB) core *.bak $(obj).depend
  50 +
  51 +#########################################################################
  52 +
  53 +# defines $(obj).depend target
  54 +include $(SRCTREE)/rules.mk
  55 +
  56 +sinclude $(obj).depend
  57 +
  58 +#########################################################################
board/gdsys/common/fpga.h
Diff comments   View file @ a605ea7
  1 +/*
  2 + * (C) Copyright 2010
  3 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#ifndef _FPGA_H_
  25 +#define _FPGA_H_
  26 +
  27 +static inline u16 fpga_get_reg(unsigned reg)
  28 +{
  29 + return in_le16((void *)(CONFIG_SYS_FPGA_BASE + reg));
  30 +}
  31 +
  32 +static inline void fpga_set_reg(unsigned reg, u16 val)
  33 +{
  34 + return out_le16((void *)(CONFIG_SYS_FPGA_BASE + reg), val);
  35 +}
  36 +
  37 +#endif
board/gdsys/common/miiphybb.c
Diff comments   View file @ a605ea7
  1 +/*
  2 + * (C) Copyright 2010
  3 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#include <common.h>
  25 +#include <miiphy.h>
  26 +
  27 +#include <asm/io.h>
  28 +
  29 +static int io_bb_mii_init(struct bb_miiphy_bus *bus)
  30 +{
  31 + return 0;
  32 +}
  33 +
  34 +static int io_bb_mdio_active(struct bb_miiphy_bus *bus)
  35 +{
  36 + out_be32((void *)GPIO0_TCR,
  37 + in_be32((void *)GPIO0_TCR) | CONFIG_SYS_MDIO_PIN);
  38 +
  39 + return 0;
  40 +}
  41 +
  42 +static int io_bb_mdio_tristate(struct bb_miiphy_bus *bus)
  43 +{
  44 + out_be32((void *)GPIO0_TCR,
  45 + in_be32((void *)GPIO0_TCR) & ~CONFIG_SYS_MDIO_PIN);
  46 +
  47 + return 0;
  48 +}
  49 +
  50 +static int io_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
  51 +{
  52 + if (v)
  53 + out_be32((void *)GPIO0_OR,
  54 + in_be32((void *)GPIO0_OR) | CONFIG_SYS_MDIO_PIN);
  55 + else
  56 + out_be32((void *)GPIO0_OR,
  57 + in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_MDIO_PIN);
  58 +
  59 + return 0;
  60 +}
  61 +
  62 +static int io_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
  63 +{
  64 + *v = ((in_be32((void *)GPIO0_IR) & CONFIG_SYS_MDIO_PIN) != 0);
  65 +
  66 + return 0;
  67 +}
  68 +
  69 +static int io_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
  70 +{
  71 + if (v)
  72 + out_be32((void *)GPIO0_OR,
  73 + in_be32((void *)GPIO0_OR) | CONFIG_SYS_MDC_PIN);
  74 + else
  75 + out_be32((void *)GPIO0_OR,
  76 + in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_MDC_PIN);
  77 +
  78 + return 0;
  79 +}
  80 +
  81 +static int io_bb_delay(struct bb_miiphy_bus *bus)
  82 +{
  83 + udelay(1);
  84 +
  85 + return 0;
  86 +}
  87 +
  88 +struct bb_miiphy_bus bb_miiphy_buses[] = {
  89 + {
  90 + .name = CONFIG_SYS_GBIT_MII_BUSNAME,
  91 + .init = io_bb_mii_init,
  92 + .mdio_active = io_bb_mdio_active,
  93 + .mdio_tristate = io_bb_mdio_tristate,
  94 + .set_mdio = io_bb_set_mdio,
  95 + .get_mdio = io_bb_get_mdio,
  96 + .set_mdc = io_bb_set_mdc,
  97 + .delay = io_bb_delay,
  98 + }
  99 +};
  100 +
  101 +int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
  102 + sizeof(bb_miiphy_buses[0]);
board/gdsys/common/osd.c
Diff comments   View file @ a605ea7
  1 +/*
  2 + * (C) Copyright 2010
  3 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#include <common.h>
  25 +#include <i2c.h>
  26 +#include <asm/io.h>
  27 +
  28 +#include "fpga.h"
  29 +
  30 +#define CH7301_I2C_ADDR 0x75
  31 +
  32 +#define PIXCLK_640_480_60 25180000
  33 +
  34 +#define BASE_WIDTH 32
  35 +#define BASE_HEIGHT 16
  36 +#define BUFSIZE (BASE_WIDTH * BASE_HEIGHT)
  37 +
  38 +enum {
  39 + REG_CONTROL = 0x0010,
  40 + REG_MPC3W_CONTROL = 0x001a,
  41 + REG_VIDEOCONTROL = 0x0042,
  42 + REG_OSDVERSION = 0x0100,
  43 + REG_OSDFEATURES = 0x0102,
  44 + REG_OSDCONTROL = 0x0104,
  45 + REG_XY_SIZE = 0x0106,
  46 + REG_VIDEOMEM = 0x0800,
  47 +};
  48 +
  49 +enum {
  50 + CH7301_CM = 0x1c, /* Clock Mode Register */
  51 + CH7301_IC = 0x1d, /* Input Clock Register */
  52 + CH7301_GPIO = 0x1e, /* GPIO Control Register */
  53 + CH7301_IDF = 0x1f, /* Input Data Format Register */
  54 + CH7301_CD = 0x20, /* Connection Detect Register */
  55 + CH7301_DC = 0x21, /* DAC Control Register */
  56 + CH7301_HPD = 0x23, /* Hot Plug Detection Register */
  57 + CH7301_TCTL = 0x31, /* DVI Control Input Register */
  58 + CH7301_TPCP = 0x33, /* DVI PLL Charge Pump Ctrl Register */
  59 + CH7301_TPD = 0x34, /* DVI PLL Divide Register */
  60 + CH7301_TPVT = 0x35, /* DVI PLL Supply Control Register */
  61 + CH7301_TPF = 0x36, /* DVI PLL Filter Register */
  62 + CH7301_TCT = 0x37, /* DVI Clock Test Register */
  63 + CH7301_TSTP = 0x48, /* Test Pattern Register */
  64 + CH7301_PM = 0x49, /* Power Management register */
  65 + CH7301_VID = 0x4a, /* Version ID Register */
  66 + CH7301_DID = 0x4b, /* Device ID Register */
  67 + CH7301_DSP = 0x56, /* DVI Sync polarity Register */
  68 +};
  69 +
  70 +static void mpc92469ac_calc_parameters(unsigned int fout,
  71 + unsigned int *post_div, unsigned int *feedback_div)
  72 +{
  73 + unsigned int n = *post_div;
  74 + unsigned int m = *feedback_div;
  75 + unsigned int a;
  76 + unsigned int b = 14745600 / 16;
  77 +
  78 + if (fout < 50169600)
  79 + n = 8;
  80 + else if (fout < 100339199)
  81 + n = 4;
  82 + else if (fout < 200678399)
  83 + n = 2;
  84 + else
  85 + n = 1;
  86 +
  87 + a = fout * n + (b / 2); /* add b/2 for proper rounding */
  88 +
  89 + m = a / b;
  90 +
  91 + *post_div = n;
  92 + *feedback_div = m;
  93 +}
  94 +
  95 +static void mpc92469ac_set(unsigned int fout)
  96 +{
  97 + unsigned int n;
  98 + unsigned int m;
  99 + unsigned int bitval = 0;
  100 + mpc92469ac_calc_parameters(fout, &n, &m);
  101 +
  102 + switch (n) {
  103 + case 1:
  104 + bitval = 0x00;
  105 + break;
  106 + case 2:
  107 + bitval = 0x01;
  108 + break;
  109 + case 4:
  110 + bitval = 0x02;
  111 + break;
  112 + case 8:
  113 + bitval = 0x03;
  114 + break;
  115 + }
  116 +
  117 + fpga_set_reg(REG_MPC3W_CONTROL, (bitval << 9) | m);
  118 +}
  119 +
  120 +static int osd_write_videomem(unsigned offset, u16 *data, size_t charcount)
  121 +{
  122 + unsigned int k;
  123 +
  124 + for (k = 0; k < charcount; ++k) {
  125 + if (offset + k >= BUFSIZE)
  126 + return -1;
  127 + fpga_set_reg(REG_VIDEOMEM + 2 * (offset + k), data[k]);
  128 + }
  129 +
  130 + return charcount;
  131 +}
  132 +
  133 +static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  134 +{
  135 + unsigned x;
  136 + unsigned y;
  137 + unsigned charcount;
  138 + unsigned len;
  139 + u8 color;
  140 + unsigned int k;
  141 + u16 buf[BUFSIZE];
  142 + char *text;
  143 +
  144 + if (argc < 5) {
  145 + cmd_usage(cmdtp);
  146 + return 1;
  147 + }
  148 +
  149 + x = simple_strtoul(argv[1], NULL, 16);
  150 + y = simple_strtoul(argv[2], NULL, 16);
  151 + color = simple_strtoul(argv[3], NULL, 16);
  152 + text = argv[4];
  153 + charcount = strlen(text);
  154 + len = (charcount > BUFSIZE) ? BUFSIZE : charcount;
  155 +
  156 + for (k = 0; k < len; ++k)
  157 + buf[k] = (text[k] << 8) | color;
  158 +
  159 + return osd_write_videomem(y * BASE_WIDTH + x, buf, len);
  160 +}
  161 +
  162 +int osd_probe(void)
  163 +{
  164 + u8 value;
  165 + u16 version = fpga_get_reg(REG_OSDVERSION);
  166 + u16 features = fpga_get_reg(REG_OSDFEATURES);
  167 + unsigned width;
  168 + unsigned height;
  169 +
  170 + width = ((features & 0x3f00) >> 8) + 1;
  171 + height = (features & 0x001f) + 1;
  172 +
  173 + printf("OSD: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
  174 + version/100, version%100, width, height);
  175 +
  176 + value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
  177 + if (value != 0x17) {
  178 + printf(" Probing CH7301 failed, DID %02x\n", value);
  179 + return -1;
  180 + }
  181 + i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
  182 + i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
  183 + i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
  184 + i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
  185 + i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
  186 +
  187 + mpc92469ac_set(PIXCLK_640_480_60);
  188 + fpga_set_reg(REG_VIDEOCONTROL, 0x0002);
  189 + fpga_set_reg(REG_OSDCONTROL, 0x0049);
  190 +
  191 + fpga_set_reg(REG_XY_SIZE, ((32 - 1) << 8) | (16 - 1));
  192 +
  193 + return 0;
  194 +}
  195 +
  196 +int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  197 +{
  198 + unsigned x;
  199 + unsigned y;
  200 + unsigned k;
  201 + u16 buffer[BASE_WIDTH];
  202 + char *rp;
  203 + u16 *wp = buffer;
  204 + unsigned count = (argc > 4) ? simple_strtoul(argv[4], NULL, 16) : 1;
  205 +
  206 + if ((argc < 4) || (strlen(argv[3]) % 4)) {
  207 + cmd_usage(cmdtp);
  208 + return 1;
  209 + }
  210 +
  211 + x = simple_strtoul(argv[1], NULL, 16);
  212 + y = simple_strtoul(argv[2], NULL, 16);
  213 + rp = argv[3];
  214 +
  215 +
  216 + while (*rp) {
  217 + char substr[5];
  218 +
  219 + memcpy(substr, rp, 4);
  220 + substr[4] = 0;
  221 + *wp = simple_strtoul(substr, NULL, 16);
  222 +
  223 + rp += 4;
  224 + wp++;
  225 + if (wp - buffer > BASE_WIDTH)
  226 + break;
  227 + }
  228 +
  229 + for (k = 0; k < count; ++k) {
  230 + unsigned offset = y * BASE_WIDTH + x + k * (wp - buffer);
  231 + osd_write_videomem(offset, buffer, wp - buffer);
  232 + }
  233 +
  234 + return 0;
  235 +}
  236 +
  237 +U_BOOT_CMD(
  238 + osdw, 5, 0, osd_write,
  239 + "write 16-bit hex encoded buffer to osd memory",
  240 + "pos_x pos_y buffer count\n"
  241 +);
  242 +
  243 +U_BOOT_CMD(
  244 + osdp, 5, 0, osd_print,
  245 + "write ASCII buffer to osd memory",
  246 + "pos_x pos_y color text\n"
  247 +);
board/gdsys/common/osd.h
Diff comments   View file @ a605ea7
  1 +/*
  2 + * (C) Copyright 2010
  3 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#ifndef _OSD_H_
  25 +#define _OSD_H_
  26 +
  27 +int osd_probe(void);
  28 +
  29 +#endif
... ... @@ -642,6 +642,8 @@
642 642 CPCI405DT powerpc ppc4xx cpci405 esd
643 643 dlvision powerpc ppc4xx - gdsys
644 644 gdppc440etx powerpc ppc4xx - gdsys
  645 +io powerpc ppc4xx 405ep gdsys
  646 +iocon powerpc ppc4xx 405ep gdsys
645 647 CPCIISER4 powerpc ppc4xx cpciiser4 esd
646 648 DASA_SIM powerpc ppc4xx dasa_sim esd
647 649 PMC405DE powerpc ppc4xx pmc405de esd
include/configs/io.h
Diff comments   View file @ a605ea7
  1 +/*
  2 + * (C) Copyright 2010
  3 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#ifndef __CONFIG_H
  25 +#define __CONFIG_H
  26 +
  27 +#define CONFIG_405EP 1 /* this is a PPC405 CPU */
  28 +#define CONFIG_4xx 1 /* member of PPC4xx family */
  29 +#define CONFIG_IO 1 /* on a Io board */
  30 +
  31 +#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
  32 +
  33 +/*
  34 + * Include common defines/options for all AMCC eval boards
  35 + */
  36 +#define CONFIG_HOSTNAME io
  37 +#define CONFIG_IDENT_STRING " io 0.04"
  38 +#include "amcc-common.h"
  39 +
  40 +#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
  41 +#define CONFIG_LAST_STAGE_INIT /* call last_stage_init */
  42 +
  43 +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
  44 +
  45 +/*
  46 + * Configure PLL
  47 + */
  48 +#define PLLMR0_DEFAULT PLLMR0_266_133_66
  49 +#define PLLMR1_DEFAULT PLLMR1_266_133_66
  50 +
  51 +/* new uImage format support */
  52 +#define CONFIG_FIT
  53 +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
  54 +
  55 +#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
  56 +
  57 +/*
  58 + * Default environment variables
  59 + */
  60 +#define CONFIG_EXTRA_ENV_SETTINGS \
  61 + CONFIG_AMCC_DEF_ENV \
  62 + CONFIG_AMCC_DEF_ENV_POWERPC \
  63 + CONFIG_AMCC_DEF_ENV_NOR_UPD \
  64 + "kernel_addr=fc000000\0" \
  65 + "fdt_addr=fc1e0000\0" \
  66 + "ramdisk_addr=fc200000\0" \
  67 + ""
  68 +
  69 +#define CONFIG_PHY_ADDR 4 /* PHY address */
  70 +#define CONFIG_HAS_ETH0
  71 +#define CONFIG_HAS_ETH1
  72 +#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */
  73 +#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
  74 +
  75 +/*
  76 + * Commands additional to the ones defined in amcc-common.h
  77 + */
  78 +#define CONFIG_CMD_CACHE
  79 +#undef CONFIG_CMD_EEPROM
  80 +
  81 +/*
  82 + * SDRAM configuration (please see cpu/ppc/sdram.[ch])
  83 + */
  84 +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
  85 +
  86 +/* SDRAM timings used in datasheet */
  87 +#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
  88 +#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
  89 +#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
  90 +#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
  91 +#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
  92 +
  93 +/*
  94 + * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
  95 + * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
  96 + * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
  97 + * The Linux BASE_BAUD define should match this configuration.
  98 + * baseBaud = cpuClock/(uartDivisor*16)
  99 + * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
  100 + * set Linux BASE_BAUD to 403200.
  101 + */
  102 +#define CONFIG_CONS_INDEX 1 /* Use UART0 */
  103 +#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
  104 +#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
  105 +#define CONFIG_SYS_BASE_BAUD 691200
  106 +
  107 +/*
  108 + * I2C stuff
  109 + */
  110 +#define CONFIG_SYS_I2C_SPEED 100000
  111 +
  112 +/* Temp sensor/hwmon/dtt */
  113 +#define CONFIG_DTT_LM63 1 /* National LM63 */
  114 +#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */
  115 +#define CONFIG_DTT_PWM_LOOKUPTABLE \
  116 + { { 40, 10 }, { 50, 20 }, { 60, 40 } }
  117 +#define CONFIG_DTT_TACH_LIMIT 0xa10
  118 +
  119 +/*
  120 + * FLASH organization
  121 + */
  122 +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
  123 +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
  124 +
  125 +#define CONFIG_SYS_FLASH_BASE 0xFC000000
  126 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
  127 +
  128 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
  129 +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
  130 +
  131 +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
  132 +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
  133 +
  134 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
  135 +#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protect */
  136 +
  137 +#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
  138 +#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
  139 +
  140 +#ifdef CONFIG_ENV_IS_IN_FLASH
  141 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
  142 +#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
  143 +#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
  144 +
  145 +/* Address and size of Redundant Environment Sector */
  146 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
  147 +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  148 +#endif
  149 +
  150 +/* Gbit PHYs */
  151 +#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
  152 +#define CONFIG_BITBANGMII_MULTI
  153 +
  154 +#define CONFIG_SYS_MDIO_PIN (0x80000000 >> 13) /* our MDIO is GPIO0 */
  155 +#define CONFIG_SYS_MDC_PIN (0x80000000 >> 7) /* our MDC is GPIO7 */
  156 +
  157 +#define CONFIG_SYS_GBIT_MII_BUSNAME "io_miiphy"
  158 +
  159 +/*
  160 + * PPC405 GPIO Configuration
  161 + */
  162 +#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
  163 +{ \
  164 +/* GPIO Core 0 */ \
  165 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
  166 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
  167 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
  168 +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
  169 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
  170 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
  171 +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
  172 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
  173 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
  174 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
  175 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
  176 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
  177 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
  178 +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
  179 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
  180 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
  181 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
  182 +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
  183 +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
  184 +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
  185 +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
  186 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
  187 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
  188 +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
  189 +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
  190 +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
  191 +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
  192 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
  193 +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
  194 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
  195 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
  196 +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
  197 +} \
  198 +}
  199 +
  200 +/*
  201 + * Definitions for initial stack pointer and data area (in data cache)
  202 + */
  203 +/* use on chip memory (OCM) for temperary stack until sdram is tested */
  204 +#define CONFIG_SYS_TEMP_STACK_OCM 1
  205 +
  206 +/* On Chip Memory location */
  207 +#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
  208 +#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
  209 +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
  210 +#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
  211 +
  212 +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/
  213 +#define CONFIG_SYS_GBL_DATA_OFFSET \
  214 + (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  215 +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  216 +
  217 +/*
  218 + * External Bus Controller (EBC) Setup
  219 + */
  220 +
  221 +/* Memory Bank 0 (NOR-FLASH) initialization */
  222 +#define CONFIG_SYS_EBC_PB0AP 0xa382a880
  223 +/* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
  224 +#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
  225 +
  226 +/* Memory Bank 1 (NVRAM) initializatio */
  227 +#define CONFIG_SYS_EBC_PB1AP 0x92015480
  228 +/* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
  229 +#define CONFIG_SYS_EBC_PB1CR 0x7f318000
  230 +
  231 +/* Memory Bank 2 (FPGA) initialization */
  232 +#define CONFIG_SYS_FPGA_BASE 0x7f100000
  233 +#define CONFIG_SYS_EBC_PB2AP 0x02025080
  234 +/* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
  235 +#define CONFIG_SYS_EBC_PB2CR 0x7f11a000
  236 +
  237 +#define CONFIG_SYS_FPGA_RFL_LOW 0x0000
  238 +#define CONFIG_SYS_FPGA_RFL_HIGH 0x3ffe
  239 +
  240 +/* Memory Bank 3 (Latches) initialization */
  241 +#define CONFIG_SYS_LATCH_BASE 0x7f200000
  242 +#define CONFIG_SYS_EBC_PB3AP 0xa2015480
  243 +/* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
  244 +#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
  245 +
  246 +#define CONFIG_SYS_LATCH0_RESET 0xffff
  247 +#define CONFIG_SYS_LATCH0_BOOT 0xffff
  248 +#define CONFIG_SYS_LATCH1_RESET 0xffbf
  249 +#define CONFIG_SYS_LATCH1_BOOT 0xffff
  250 +
  251 +#endif /* __CONFIG_H */
include/configs/iocon.h
Diff comments   View file @ a605ea7
  1 +/*
  2 + * (C) Copyright 2010
  3 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#ifndef __CONFIG_H
  25 +#define __CONFIG_H
  26 +
  27 +#define CONFIG_405EP 1 /* this is a PPC405 CPU */
  28 +#define CONFIG_4xx 1 /* member of PPC4xx family */
  29 +#define CONFIG_IOCON 1 /* on a IoCon board */
  30 +
  31 +#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
  32 +
  33 +/*
  34 + * Include common defines/options for all AMCC eval boards
  35 + */
  36 +#define CONFIG_HOSTNAME iocon
  37 +#define CONFIG_IDENT_STRING " iocon 0.03"
  38 +#include "amcc-common.h"
  39 +
  40 +#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
  41 +#define CONFIG_LAST_STAGE_INIT
  42 +
  43 +#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
  44 +
  45 +/*
  46 + * Configure PLL
  47 + */
  48 +#define PLLMR0_DEFAULT PLLMR0_266_133_66
  49 +#define PLLMR1_DEFAULT PLLMR1_266_133_66
  50 +
  51 +/* new uImage format support */
  52 +#define CONFIG_FIT
  53 +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
  54 +
  55 +#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
  56 +
  57 +/*
  58 + * Default environment variables
  59 + */
  60 +#define CONFIG_EXTRA_ENV_SETTINGS \
  61 + CONFIG_AMCC_DEF_ENV \
  62 + CONFIG_AMCC_DEF_ENV_POWERPC \
  63 + CONFIG_AMCC_DEF_ENV_NOR_UPD \
  64 + "kernel_addr=fc000000\0" \
  65 + "fdt_addr=fc1e0000\0" \
  66 + "ramdisk_addr=fc200000\0" \
  67 + ""
  68 +
  69 +#define CONFIG_PHY_ADDR 4 /* PHY address */
  70 +#define CONFIG_HAS_ETH0
  71 +#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
  72 +
  73 +/*
  74 + * Commands additional to the ones defined in amcc-common.h
  75 + */
  76 +#define CONFIG_CMD_CACHE
  77 +#undef CONFIG_CMD_EEPROM
  78 +
  79 +/*
  80 + * SDRAM configuration (please see cpu/ppc/sdram.[ch])
  81 + */
  82 +#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
  83 +
  84 +/* SDRAM timings used in datasheet */
  85 +#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
  86 +#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
  87 +#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
  88 +#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
  89 +#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
  90 +
  91 +/*
  92 + * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
  93 + * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
  94 + * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
  95 + * The Linux BASE_BAUD define should match this configuration.
  96 + * baseBaud = cpuClock/(uartDivisor*16)
  97 + * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
  98 + * set Linux BASE_BAUD to 403200.
  99 + */
  100 +#define CONFIG_CONS_INDEX 1 /* Use UART0 */
  101 +#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
  102 +#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
  103 +#define CONFIG_SYS_BASE_BAUD 691200
  104 +
  105 +/*
  106 + * I2C stuff
  107 + */
  108 +#define CONFIG_SYS_I2C_SPEED 400000
  109 +
  110 +/* enable I2C and select the hardware/software driver */
  111 +#undef CONFIG_HARD_I2C /* I2C with hardware support */
  112 +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
  113 +
  114 +/*
  115 + * Software (bit-bang) I2C driver configuration
  116 + */
  117 +
  118 +#ifndef __ASSEMBLY__
  119 +void fpga_gpio_set(int pin);
  120 +void fpga_gpio_clear(int pin);
  121 +int fpga_gpio_get(int pin);
  122 +#endif
  123 +
  124 +#define I2C_ACTIVE { }
  125 +#define I2C_TRISTATE { }
  126 +#define I2C_READ fpga_gpio_get(0x0040) ? 1 : 0
  127 +#define I2C_SDA(bit) if (bit) fpga_gpio_set(0x0040); \
  128 + else fpga_gpio_clear(0x0040)
  129 +#define I2C_SCL(bit) if (bit) fpga_gpio_set(0x0020); \
  130 + else fpga_gpio_clear(0x0020)
  131 +#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
  132 +
  133 +/*
  134 + * FLASH organization
  135 + */
  136 +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
  137 +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
  138 +
  139 +#define CONFIG_SYS_FLASH_BASE 0xFC000000
  140 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
  141 +
  142 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
  143 +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
  144 +
  145 +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
  146 +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
  147 +
  148 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
  149 +#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protect */
  150 +
  151 +#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
  152 +#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
  153 +
  154 +#ifdef CONFIG_ENV_IS_IN_FLASH
  155 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
  156 +#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
  157 +#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
  158 +
  159 +/* Address and size of Redundant Environment Sector */
  160 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
  161 +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  162 +#endif
  163 +
  164 +/*
  165 + * PPC405 GPIO Configuration
  166 + */
  167 +#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
  168 +{ \
  169 +/* GPIO Core 0 */ \
  170 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
  171 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
  172 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
  173 +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
  174 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
  175 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
  176 +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
  177 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
  178 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
  179 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
  180 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
  181 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
  182 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
  183 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
  184 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
  185 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
  186 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
  187 +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
  188 +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
  189 +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
  190 +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
  191 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
  192 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
  193 +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
  194 +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
  195 +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
  196 +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
  197 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
  198 +{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
  199 +{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
  200 +{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
  201 +{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
  202 +} \
  203 +}
  204 +
  205 +/*
  206 + * Definitions for initial stack pointer and data area (in data cache)
  207 + */
  208 +/* use on chip memory (OCM) for temperary stack until sdram is tested */
  209 +#define CONFIG_SYS_TEMP_STACK_OCM 1
  210 +
  211 +/* On Chip Memory location */
  212 +#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
  213 +#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
  214 +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
  215 +#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
  216 +
  217 +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/
  218 +#define CONFIG_SYS_GBL_DATA_OFFSET \
  219 + (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  220 +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  221 +
  222 +/*
  223 + * External Bus Controller (EBC) Setup
  224 + */
  225 +
  226 +/* Memory Bank 0 (NOR-FLASH) initialization */
  227 +#define CONFIG_SYS_EBC_PB0AP 0xa382a880
  228 +#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
  229 +
  230 +/* Memory Bank 1 (NVRAM) initializatio */
  231 +#define CONFIG_SYS_EBC_PB1AP 0x92015480
  232 +#define CONFIG_SYS_EBC_PB1CR 0xFB858000
  233 +
  234 +/* Memory Bank 2 (FPGA) initialization */
  235 +#define CONFIG_SYS_FPGA_BASE 0x7f100000
  236 +#define CONFIG_SYS_EBC_PB2AP 0x02825080
  237 +#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE | 0x1a000)
  238 +
  239 +#define CONFIG_SYS_FPGA_RFL_LOW 0x0000
  240 +#define CONFIG_SYS_FPGA_RFL_HIGH 0x00fe
  241 +
  242 +/* Memory Bank 3 (Latches) initialization */
  243 +#define CONFIG_SYS_LATCH_BASE 0x7f200000
  244 +#define CONFIG_SYS_EBC_PB3AP 0x02025080
  245 +#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
  246 +
  247 +#define CONFIG_SYS_LATCH0_RESET 0xffef
  248 +#define CONFIG_SYS_LATCH0_BOOT 0xffff
  249 +#define CONFIG_SYS_LATCH1_RESET 0xffff
  250 +#define CONFIG_SYS_LATCH1_BOOT 0xffff
  251 +
  252 +#endif /* __CONFIG_H */