ARM: mvebu: x530: use MV_DDR_FREQ_SAR

MV_DDR_FREQ_SAR lets the DDR frequency be determined by hardware strapping. This also has the side effect of running the DDR clock in synchronous mode with the CPU core clock rather than from an independent PLL. We've seen this improve reliability in operation across a number of boards and temperature ranges. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>

ARM: mvebu: x530: use MV_DDR_FREQ_SAR
MV_DDR_FREQ_SAR lets the DDR frequency be determined by hardware strapping. This also has the side effect of running the DDR clock in synchronous mode with the CPU core clock rather than from an independent PLL. We've seen this improve reliability in operation across a number of boards and temperature ranges. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
Chris Packham · Stefan Roese
1 parent 0ef6920843
Showing 1 changed file with 1 additions and 1 deletions Side-by-side Diff
board/alliedtelesis/x530/x530.c
@@ -57,7 +57,7 @@
 	    SPEED_BIN_DDR_1866M,	/* speed_bin */
 	    MV_DDR_DEV_WIDTH_16BIT,	/* sdram device width */
 	    MV_DDR_DIE_CAP_4GBIT,	/* die capacity */
-	    MV_DDR_FREQ_933,		/* frequency */
+	    MV_DDR_FREQ_SAR,		/* frequency */
 	    0, 0,			/* cas_l cas_wl */
 	    MV_DDR_TEMP_LOW,		/* temperature */
 	    MV_DDR_TIM_2T} },		/* timing */
...	...	@@ -57,7 +57,7 @@
57	57	SPEED_BIN_DDR_1866M, /* speed_bin */
58	58	MV_DDR_DEV_WIDTH_16BIT, /* sdram device width */
59	59	MV_DDR_DIE_CAP_4GBIT, /* die capacity */
60		- MV_DDR_FREQ_933, /* frequency */
	60	+ MV_DDR_FREQ_SAR, /* frequency */
61	61	0, 0, /* cas_l cas_wl */
62	62	MV_DDR_TEMP_LOW, /* temperature */
63	63	MV_DDR_TIM_2T} }, /* timing */