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Commit a6b0652bb5040351eeb1a2580270bd3988cb0a59

Authored by Nikita Kiryanov
Committed by Stefano Babic
1 parent e32028a70b
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm: mx6: cm_fx6: add nand support 

Add NAND support for Compulab CM-FX6 CoM.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>

Showing 3 changed files with 78 additions and 1 deletions Side-by-side Diff

board/compulab/cm_fx6/cm_fx6.c
Diff comments   View file @ a6b0652
... ... @@ -10,11 +10,46 @@
10 10  
11 11 #include <common.h>
12 12 #include <fsl_esdhc.h>
  13 +#include <asm/arch/crm_regs.h>
13 14 #include <asm/arch/sys_proto.h>
  15 +#include <asm/io.h>
14 16 #include "common.h"
15 17  
16 18 DECLARE_GLOBAL_DATA_PTR;
17 19  
  20 +#ifdef CONFIG_NAND_MXS
  21 +static iomux_v3_cfg_t const nand_pads[] = {
  22 + IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
  23 + IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
  24 + IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  25 + IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  26 + IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  27 + IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  28 + IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  29 + IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  30 + IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  31 + IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  32 + IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  33 + IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  34 + IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  35 + IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  36 +};
  37 +
  38 +static void cm_fx6_setup_gpmi_nand(void)
  39 +{
  40 + SETUP_IOMUX_PADS(nand_pads);
  41 + /* Enable clock roots */
  42 + enable_usdhc_clk(1, 3);
  43 + enable_usdhc_clk(1, 4);
  44 +
  45 + setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
  46 + MXC_CCM_CS2CDR_ENFC_CLK_PRED(1) |
  47 + MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
  48 +}
  49 +#else
  50 +static void cm_fx6_setup_gpmi_nand(void) {}
  51 +#endif
  52 +
18 53 #ifdef CONFIG_FSL_ESDHC
19 54 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
20 55 {USDHC1_BASE_ADDR},
... ... @@ -47,6 +82,8 @@
47 82 int board_init(void)
48 83 {
49 84 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  85 + cm_fx6_setup_gpmi_nand();
  86 +
50 87 return 0;
51 88 }
52 89  
board/compulab/cm_fx6/spl.c
Diff comments   View file @ a6b0652
... ... @@ -15,6 +15,7 @@
15 15 #include <asm/arch/mx6-ddr.h>
16 16 #include <asm/arch/clock.h>
17 17 #include <asm/arch/sys_proto.h>
  18 +#include <asm/arch/crm_regs.h>
18 19 #include <asm/imx-common/iomux-v3.h>
19 20 #include <fsl_esdhc.h>
20 21 #include "common.h"
21 22  
... ... @@ -309,7 +310,17 @@
309 310  
310 311 void board_init_f(ulong dummy)
311 312 {
  313 + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  314 +
312 315 gd = &gdata;
  316 + /*
  317 + * We don't use DMA in SPL, but we do need it in U-Boot. U-Boot
  318 + * initializes DMA very early (before all board code), so the only
  319 + * opportunity we have to initialize APBHDMA clocks is in SPL.
  320 + */
  321 + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  322 + enable_usdhc_clk(1, 2);
  323 +
313 324 arch_cpu_init();
314 325 timer_init();
315 326 cm_fx6_setup_ecspi();
include/configs/cm_fx6.h
Diff comments   View file @ a6b0652
... ... @@ -130,6 +130,20 @@
130 130 "mmcboot=echo Booting from mmc ...; " \
131 131 "run mmcargs; " \
132 132 "run doboot\0" \
  133 + "nandroot=/dev/mtdblock4 rw\0" \
  134 + "nandrootfstype=ubifs\0" \
  135 + "nandargs=setenv bootargs console=${console} " \
  136 + "root=${nandroot} " \
  137 + "rootfstype=${nandrootfstype} " \
  138 + "${video}\0" \
  139 + "nandloadfdt=nand read ${fdtaddr} 780000 80000;\0" \
  140 + "nandboot=echo Booting from nand ...; " \
  141 + "run nandargs; " \
  142 + "nand read ${loadaddr} 0 780000; " \
  143 + "if ${loadfdt}; then " \
  144 + "run nandloadfdt;" \
  145 + "fi; " \
  146 + "run doboot\0" \
133 147 "boot=mmc dev ${mmcdev}; " \
134 148 "if mmc rescan; then " \
135 149 "if run loadmmcbootscript; then " \
... ... @@ -142,7 +156,8 @@
142 156 "run mmcboot;" \
143 157 "fi;" \
144 158 "fi;" \
145   - "fi;\0"
  159 + "fi;" \
  160 + "run nandboot\0"
146 161  
147 162 #define CONFIG_BOOTCOMMAND \
148 163 "run setboottypem; run boot"
... ... @@ -159,6 +174,20 @@
159 174 #define CONFIG_SPI_FLASH_STMICRO
160 175 #define CONFIG_SPI_FLASH_SST
161 176 #define CONFIG_SPI_FLASH_WINBOND
  177 +
  178 +/* NAND */
  179 +#ifndef CONFIG_SPL_BUILD
  180 +#define CONFIG_CMD_NAND
  181 +#define CONFIG_SYS_NAND_BASE 0x40000000
  182 +#define CONFIG_SYS_NAND_MAX_CHIPS 1
  183 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
  184 +#define CONFIG_NAND_MXS
  185 +#define CONFIG_SYS_NAND_ONFI_DETECTION
  186 +/* APBH DMA is required for NAND support */
  187 +#define CONFIG_APBH_DMA
  188 +#define CONFIG_APBH_DMA_BURST
  189 +#define CONFIG_APBH_DMA_BURST8
  190 +#endif
162 191  
163 192 /* GPIO */
164 193 #define CONFIG_MXC_GPIO