Commit a73ca4789fddce35936dd8decb1522f08b6cb620

Authored by Stephen Warren
Committed by Tom Warren
1 parent b9dd6215ce

mmc: tegra: support Tegra124

Tegra124's MMC controller is very similar to earlier SoC generations,
and can be supported by the same driver.

However, there are some non-backwards-compatible HW differences, and
hence a new DT compatible value must be used to describe the HW. This
patch updates the driver to support that new compatible value.

That said, the HW differences are only relevant when enabling certain
high-performance transfer modes. Since the driver is currently very
simple and doesn't enable those modes, we don't actually need to address
any of these HW differences in the code yet, hence the simple nature of
this patch.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

Showing 3 changed files with 11 additions and 0 deletions Side-by-side Diff

drivers/mmc/tegra_mmc.c
... ... @@ -668,6 +668,15 @@
668 668 const void *blob = gd->fdt_blob;
669 669 debug("%s entry\n", __func__);
670 670  
  671 + /* See if any Tegra124 MMC controllers are present */
  672 + count = fdtdec_find_aliases_for_id(blob, "sdhci",
  673 + COMPAT_NVIDIA_TEGRA124_SDMMC, node_list, MAX_HOSTS);
  674 + debug("%s: count of Tegra124 sdhci nodes is %d\n", __func__, count);
  675 + if (process_nodes(blob, node_list, count)) {
  676 + printf("%s: Error processing T30 mmc node(s)!\n", __func__);
  677 + return;
  678 + }
  679 +
671 680 /* See if any Tegra30 MMC controllers are present */
672 681 count = fdtdec_find_aliases_for_id(blob, "sdhci",
673 682 COMPAT_NVIDIA_TEGRA30_SDMMC, node_list, MAX_HOSTS);
... ... @@ -59,6 +59,7 @@
59 59 COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */
60 60 COMPAT_NVIDIA_TEGRA20_PWM, /* Tegra 2 PWM controller */
61 61 COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */
  62 + COMPAT_NVIDIA_TEGRA124_SDMMC, /* Tegra124 SDMMC controller */
62 63 COMPAT_NVIDIA_TEGRA30_SDMMC, /* Tegra30 SDMMC controller */
63 64 COMPAT_NVIDIA_TEGRA20_SDMMC, /* Tegra20 SDMMC controller */
64 65 COMPAT_NVIDIA_TEGRA20_SFLASH, /* Tegra 2 SPI flash controller */
... ... @@ -32,6 +32,7 @@
32 32 COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),
33 33 COMPAT(NVIDIA_TEGRA20_PWM, "nvidia,tegra20-pwm"),
34 34 COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"),
  35 + COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"),
35 36 COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"),
36 37 COMPAT(NVIDIA_TEGRA20_SDMMC, "nvidia,tegra20-sdhci"),
37 38 COMPAT(NVIDIA_TEGRA20_SFLASH, "nvidia,tegra20-sflash"),