arm: socfpga: agilex: Enable Agilex SoC build

Add build support for Agilex SoC. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

arm: socfpga: agilex: Enable Agilex SoC build
Add build support for Agilex SoC. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Ley Foon Tan · Marek Vasut
1 parent 380477f1d1
Showing 6 changed files with 104 additions and 3 deletions Side-by-side Diff
arch/arm/Kconfig
arch/arm/mach-socfpga/Kconfig
arch/arm/mach-socfpga/Makefile
configs/socfpga_agilex_defconfig
include/configs/socfpga_agilex_socdk.h
include/configs/socfpga_soc64_common.h
@@ -905,7 +905,7 @@
 	bool "Altera SOCFPGA family"
 	select ARCH_EARLY_INIT_R
 	select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
-	select ARM64 if TARGET_SOCFPGA_STRATIX10
+	select ARM64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
 	select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
 	select DM
 	select DM_SERIAL
@@ -917,7 +917,7 @@
 	select SPL_LIBGENERIC_SUPPORT
 	select SPL_NAND_SUPPORT if SPL_NAND_DENALI
 	select SPL_OF_CONTROL
-	select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
+	select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
 	select SPL_SERIAL_SUPPORT
 	select SPL_SYSRESET
 	select SPL_WATCHDOG_SUPPORT
@@ -29,6 +29,15 @@
 	default 0x01000040 if TARGET_SOCFPGA_ARRIA10
 	default 0x01000040 if TARGET_SOCFPGA_GEN5
  
+config TARGET_SOCFPGA_AGILEX
+	bool
+	select ARMV8_MULTIENTRY
+	select ARMV8_SET_SMPEN
+	select ARMV8_SPIN_TABLE
+	select CLK
+	select NCORE_CACHE
+	select SPL_CLK if SPL
+
 config TARGET_SOCFPGA_ARRIA5
 	bool
 	select TARGET_SOCFPGA_GEN5
@@ -75,6 +84,10 @@
 	prompt "Altera SOCFPGA board select"
 	optional
  
+config TARGET_SOCFPGA_AGILEX_SOCDK
+	bool "Intel SOCFPGA SoCDK (Agilex)"
+	select TARGET_SOCFPGA_AGILEX
+
 config TARGET_SOCFPGA_ARIES_MCVEVK
 	bool "Aries MCVEVK (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
@@ -135,6 +148,7 @@
 endchoice
  
 config SYS_BOARD
+	default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
 	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 	default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
@@ -151,6 +165,7 @@
 	default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
  
 config SYS_VENDOR
+	default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
 	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
 	default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
 	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
@@ -168,6 +183,7 @@
 	default "socfpga"
  
 config SYS_CONFIG_NAME
+	default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
 	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 	default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
@@ -41,6 +41,14 @@
  
 ifdef CONFIG_TARGET_SOCFPGA_AGILEX
 obj-y	+= clock_manager_agilex.o
+obj-y	+= mailbox_s10.o
+obj-y	+= misc_s10.o
+obj-y	+= mmu-arm64_s10.o
+obj-y	+= reset_manager_s10.o
+obj-y	+= system_manager_s10.o
+obj-y	+= timer_s10.o
+obj-y	+= wrap_pinmux_config_s10.o
+obj-y	+= wrap_pll_config_s10.o
 endif
  
 ifdef CONFIG_SPL_BUILD
@@ -59,6 +67,7 @@
 obj-y	+= spl_s10.o
 endif
 ifdef CONFIG_TARGET_SOCFPGA_AGILEX
+obj-y	+= firewall.o
 obj-y	+= spl_agilex.o
 endif
 endif
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_TEXT_BASE=0x1000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x200
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
+CONFIG_IDENT_STRING="socfpga_agilex"
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_TEXT_BASE=0xFFE00000
+CONFIG_BOOTDELAY=5
+CONFIG_SPL_CACHE=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c00000
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # "
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_ALTERA_SDRAM=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_SF_DEFAULT_MODE=0x2003
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_MII=y
+CONFIG_DM_RESET=y
+CONFIG_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_STORAGE=y
+# CONFIG_SPL_USE_TINY_PRINTF is not set
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+#ifndef __CONFIG_SOCFGPA_AGILEX_H__
+#define __CONFIG_SOCFGPA_AGILEX_H__
+
+#include <configs/socfpga_soc64_common.h>
+
+#endif	/* __CONFIG_SOCFGPA_AGILEX_H__ */
@@ -87,7 +87,7 @@
 	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
 	"bootfile=Image\0" \
 	"fdt_addr=8000000\0" \
-	"fdtimage=socfpga_stratix10_socdk.dtb.dtb\0" \" \
+	"fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb.dtb\0" \" \
 	"mmcroot=/dev/mmcblk0p2\0" \
 	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
 		" root=${mmcroot} rw rootwait;" \
  
@@ -155,9 +155,13 @@
 #define CONFIG_HW_WATCHDOG
 #define CONFIG_DESIGNWARE_WATCHDOG
 #define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
+#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 #ifndef __ASSEMBLY__
 unsigned int cm_get_l4_sys_free_clk_hz(void);
 #define CONFIG_DW_WDT_CLOCK_KHZ		(cm_get_l4_sys_free_clk_hz() / 1000)
+#endif
+#else
+#define CONFIG_DW_WDT_CLOCK_KHZ		100000
 #endif
 #endif
...	...	@@ -905,7 +905,7 @@
905	905	bool "Altera SOCFPGA family"
906	906	select ARCH_EARLY_INIT_R
907	907	select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
908		- select ARM64 if TARGET_SOCFPGA_STRATIX10
	908	+ select ARM64 if TARGET_SOCFPGA_STRATIX10 \|\| TARGET_SOCFPGA_AGILEX
909	909	select CPU_V7A if TARGET_SOCFPGA_GEN5 \|\| TARGET_SOCFPGA_ARRIA10
910	910	select DM
911	911	select DM_SERIAL
...	...	@@ -917,7 +917,7 @@
917	917	select SPL_LIBGENERIC_SUPPORT
918	918	select SPL_NAND_SUPPORT if SPL_NAND_DENALI
919	919	select SPL_OF_CONTROL
920		- select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10
	920	+ select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 \|\| TARGET_SOCFPGA_AGILEX
921	921	select SPL_SERIAL_SUPPORT
922	922	select SPL_SYSRESET
923	923	select SPL_WATCHDOG_SUPPORT
...	...	@@ -29,6 +29,15 @@
29	29	default 0x01000040 if TARGET_SOCFPGA_ARRIA10
30	30	default 0x01000040 if TARGET_SOCFPGA_GEN5
31	31
	32	+config TARGET_SOCFPGA_AGILEX
	33	+ bool
	34	+ select ARMV8_MULTIENTRY
	35	+ select ARMV8_SET_SMPEN
	36	+ select ARMV8_SPIN_TABLE
	37	+ select CLK
	38	+ select NCORE_CACHE
	39	+ select SPL_CLK if SPL
	40	+
32	41	config TARGET_SOCFPGA_ARRIA5
33	42	bool
34	43	select TARGET_SOCFPGA_GEN5
...	...	@@ -75,6 +84,10 @@
75	84	prompt "Altera SOCFPGA board select"
76	85	optional
77	86
	87	+config TARGET_SOCFPGA_AGILEX_SOCDK
	88	+ bool "Intel SOCFPGA SoCDK (Agilex)"
	89	+ select TARGET_SOCFPGA_AGILEX
	90	+
78	91	config TARGET_SOCFPGA_ARIES_MCVEVK
79	92	bool "Aries MCVEVK (Cyclone V)"
80	93	select TARGET_SOCFPGA_CYCLONE5
...	...	@@ -135,6 +148,7 @@
135	148	endchoice
136	149
137	150	config SYS_BOARD
	151	+ default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
138	152	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
139	153	default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
140	154	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
...	...	@@ -151,6 +165,7 @@
151	165	default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
152	166
153	167	config SYS_VENDOR
	168	+ default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
154	169	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
155	170	default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
156	171	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
...	...	@@ -168,6 +183,7 @@
168	183	default "socfpga"
169	184
170	185	config SYS_CONFIG_NAME
	186	+ default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
171	187	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
172	188	default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
173	189	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
...	...	@@ -41,6 +41,14 @@
41	41
42	42	ifdef CONFIG_TARGET_SOCFPGA_AGILEX
43	43	obj-y += clock_manager_agilex.o
	44	+obj-y += mailbox_s10.o
	45	+obj-y += misc_s10.o
	46	+obj-y += mmu-arm64_s10.o
	47	+obj-y += reset_manager_s10.o
	48	+obj-y += system_manager_s10.o
	49	+obj-y += timer_s10.o
	50	+obj-y += wrap_pinmux_config_s10.o
	51	+obj-y += wrap_pll_config_s10.o
44	52	endif
45	53
46	54	ifdef CONFIG_SPL_BUILD
...	...	@@ -59,6 +67,7 @@
59	67	obj-y += spl_s10.o
60	68	endif
61	69	ifdef CONFIG_TARGET_SOCFPGA_AGILEX
	70	+obj-y += firewall.o
62	71	obj-y += spl_agilex.o
63	72	endif
64	73	endif
	1	+CONFIG_ARM=y
	2	+CONFIG_ARCH_SOCFPGA=y
	3	+CONFIG_SYS_TEXT_BASE=0x1000
	4	+CONFIG_SYS_MALLOC_F_LEN=0x2000
	5	+CONFIG_ENV_SIZE=0x1000
	6	+CONFIG_ENV_OFFSET=0x200
	7	+CONFIG_NR_DRAM_BANKS=2
	8	+CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
	9	+CONFIG_IDENT_STRING="socfpga_agilex"
	10	+CONFIG_SPL_FS_FAT=y
	11	+CONFIG_SPL_TEXT_BASE=0xFFE00000
	12	+CONFIG_BOOTDELAY=5
	13	+CONFIG_SPL_CACHE=y
	14	+CONFIG_SPL_SPI_LOAD=y
	15	+CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c00000
	16	+CONFIG_HUSH_PARSER=y
	17	+CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # "
	18	+CONFIG_CMD_MEMTEST=y
	19	+# CONFIG_CMD_FLASH is not set
	20	+CONFIG_CMD_GPIO=y
	21	+CONFIG_CMD_I2C=y
	22	+CONFIG_CMD_MMC=y
	23	+CONFIG_CMD_SPI=y
	24	+CONFIG_CMD_USB=y
	25	+CONFIG_CMD_DHCP=y
	26	+CONFIG_CMD_MII=y
	27	+CONFIG_CMD_PING=y
	28	+CONFIG_CMD_CACHE=y
	29	+CONFIG_CMD_EXT4=y
	30	+CONFIG_CMD_FAT=y
	31	+CONFIG_CMD_FS_GENERIC=y
	32	+CONFIG_OF_EMBED=y
	33	+CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
	34	+CONFIG_ENV_IS_IN_MMC=y
	35	+CONFIG_NET_RANDOM_ETHADDR=y
	36	+CONFIG_SPL_DM_SEQ_ALIAS=y
	37	+CONFIG_SPL_ALTERA_SDRAM=y
	38	+CONFIG_DM_GPIO=y
	39	+CONFIG_DWAPB_GPIO=y
	40	+CONFIG_DM_I2C=y
	41	+CONFIG_SYS_I2C_DW=y
	42	+CONFIG_DM_MMC=y
	43	+CONFIG_MMC_DW=y
	44	+CONFIG_SF_DEFAULT_MODE=0x2003
	45	+CONFIG_SPI_FLASH_SPANSION=y
	46	+CONFIG_SPI_FLASH_STMICRO=y
	47	+CONFIG_PHY_MICREL=y
	48	+CONFIG_PHY_MICREL_KSZ90X1=y
	49	+CONFIG_DM_ETH=y
	50	+CONFIG_ETH_DESIGNWARE=y
	51	+CONFIG_MII=y
	52	+CONFIG_DM_RESET=y
	53	+CONFIG_SPI=y
	54	+CONFIG_CADENCE_QSPI=y
	55	+CONFIG_DESIGNWARE_SPI=y
	56	+CONFIG_USB=y
	57	+CONFIG_DM_USB=y
	58	+CONFIG_USB_DWC2=y
	59	+CONFIG_USB_STORAGE=y
	60	+# CONFIG_SPL_USE_TINY_PRINTF is not set
	1	+/* SPDX-License-Identifier: GPL-2.0
	2	+ *
	3	+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
	4	+ *
	5	+ */
	6	+
	7	+#ifndef __CONFIG_SOCFGPA_AGILEX_H__
	8	+#define __CONFIG_SOCFGPA_AGILEX_H__
	9	+
	10	+#include <configs/socfpga_soc64_common.h>
	11	+
	12	+#endif /* __CONFIG_SOCFGPA_AGILEX_H__ */
...	...	@@ -87,7 +87,7 @@
87	87	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
88	88	"bootfile=Image\0" \
89	89	"fdt_addr=8000000\0" \
90		- "fdtimage=socfpga_stratix10_socdk.dtb.dtb\0" \" \
	90	+ "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb.dtb\0" \" \
91	91	"mmcroot=/dev/mmcblk0p2\0" \
92	92	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
93	93	" root=${mmcroot} rw rootwait;" \
94	94
...	...	@@ -155,9 +155,13 @@
155	155	#define CONFIG_HW_WATCHDOG
156	156	#define CONFIG_DESIGNWARE_WATCHDOG
157	157	#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
	158	+#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
158	159	#ifndef __ASSEMBLY__
159	160	unsigned int cm_get_l4_sys_free_clk_hz(void);
160	161	#define CONFIG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000)
	162	+#endif
	163	+#else
	164	+#define CONFIG_DW_WDT_CLOCK_KHZ 100000
161	165	#endif
162	166	#endif
163	167