powerpc/mpc85xx/p1_p2_rdb_pc: convert from nand_spl to new spl

Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>

powerpc/mpc85xx/p1_p2_rdb_pc: convert from nand_spl to new spl
Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
Scott Wood
1 parent 7d4b79552d
Showing 3 changed files with 28 additions and 300 deletions Side-by-side Diff
include/configs/p1_p2_rdb_pc.h
nand_spl/board/freescale/p1_p2_rdb_pc/Makefile
nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c
@@ -140,16 +140,25 @@
 #define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
 #endif
  
-#if defined(CONFIG_NAND) && defined(CONFIG_NAND_FSL_ELBC)
-#define CONFIG_NAND_U_BOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_TEXT_BASE_SPL	0xff800000
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE_SPL
-#else
-#define CONFIG_SYS_TEXT_BASE		0x11001000
-#endif /* CONFIG_NAND_SPL */
+#ifdef CONFIG_NAND
+#define CONFIG_SPL
+#define CONFIG_SPL_INIT_MINIMAL
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_MINIMAL
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+
+#define CONFIG_SYS_TEXT_BASE		0x00201000
+#define CONFIG_SPL_TEXT_BASE		0xfffff000
+#define CONFIG_SPL_MAX_SIZE		(4 * 1024)
+#define CONFIG_SPL_RELOC_TEXT_BASE	0x00100000
+#define CONFIG_SPL_RELOC_STACK		0x00100000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) + CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x00200000 - CONFIG_SPL_MAX_SIZE)
+#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0
+#define CONFIG_SYS_LDSCRIPT		"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 #endif
  
 #ifndef CONFIG_SYS_TEXT_BASE
  
@@ -161,8 +170,12 @@
 #endif
  
 #ifndef CONFIG_SYS_MONITOR_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
+#else
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
 #endif
+#endif
  
 /* High Level Configuration Options */
 #define CONFIG_BOOKE
@@ -221,7 +234,7 @@
  
 /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
        SPL code*/
-#if defined(CONFIG_NAND_SPL)
+#ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #endif
  
@@ -392,15 +405,6 @@
 #define CONFIG_CMD_NAND
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(16 * 1024)
  
-/* NAND boot: 4K NAND loader config */
-#define CONFIG_SYS_NAND_SPL_SIZE	0x1000
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) + CONFIG_SYS_NAND_SPL_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_DST	(0x11000000 - CONFIG_SYS_NAND_SPL_SIZE)
-#define CONFIG_SYS_NAND_U_BOOT_START	0x11000000
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	(0)
-#define CONFIG_SYS_NAND_U_BOOT_RELOC	0x00010000
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
-
 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 	| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
 	| BR_PS_8	/* Port Size = 8 bit */ \
@@ -461,7 +465,7 @@
 				 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
 				 OR_GPCM_EAD)
  
-#ifdef CONFIG_NAND_U_BOOT
+#ifdef CONFIG_NAND
 #define CONFIG_SYS_BR0_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
 #define CONFIG_SYS_OR0_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 #define CONFIG_SYS_BR1_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
@@ -511,7 +515,7 @@
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-#ifdef CONFIG_NAND_SPL
+#ifdef CONFIG_SPL_BUILD
 #define CONFIG_NS16550_MIN_FUNCTIONS
 #endif
  
@@ -709,7 +713,6 @@
 /*
  * Environment
  */
-#ifdef CONFIG_SYS_RAMBOOT
 #ifdef CONFIG_RAMBOOT_SPIFLASH
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_SPI_BUS	0
  
  
@@ -724,16 +727,15 @@
 #define CONFIG_FSL_FIXED_MMC_LOCATION
 #define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_SYS_MMC_ENV_DEV	0
-#elif defined(CONFIG_NAND_U_BOOT)
+#elif defined(CONFIG_NAND)
 #define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
 #define CONFIG_ENV_OFFSET	((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
 #define CONFIG_ENV_RANGE	(3 * CONFIG_ENV_SIZE)
-#else
+#elif defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_ENV_IS_NOWHERE	/* Store ENV in memory only */
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
 #define CONFIG_ENV_SIZE		0x2000
-#endif
 #else
 #define CONFIG_ENV_IS_IN_FLASH
 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# Copyright 2011 Freescale Semiconductor, Inc.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-NAND_SPL := y
-CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
-PAD_TO := 0xff801000
-
-include $(TOPDIR)/config.mk
-
-nandobj	:= $(OBJTREE)/nand_spl/
-
-LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
-LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
-LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
-		$(LDFLAGS) $(LDFLAGS_FINAL)
-AFLAGS	+= -DCONFIG_NAND_SPL
-CFLAGS	+= -DCONFIG_NAND_SPL
-
-SOBJS	= start.o resetvec.o
-COBJS	= cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
-	  nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
-
-SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-__OBJS	:= $(SOBJS) $(COBJS)
-LNDIR	:= $(nandobj)board/$(BOARDDIR)
-
-ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-all:	$(obj).depend $(ALL)
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
-	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-
-$(nandobj)u-boot-spl:	$(OBJS) $(nandobj)u-boot-nand_spl.lds
-	cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
-		-Map $(nandobj)u-boot-spl.map \
-		-o $(nandobj)u-boot-spl
-
-# The following line expands into whole rule which generates $(LSTSCRIPT),
-# the file containing u-boots LG-array linker section. This is included into
-# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
-$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT)
-	$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@
-
-# create symbolic links for common files
-
-$(obj)cache.c:
-	@rm -f $(obj)cache.c
-	ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
-
-$(obj)cpu_init_early.c:
-	@rm -f $(obj)cpu_init_early.c
-	ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c
-
-$(obj)spl_minimal.c:
-	@rm -f $(obj)spl_minimal.c
-	ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $(obj)spl_minimal.c
-
-$(obj)fsl_law.c:
-	@rm -f $(obj)fsl_law.c
-	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
-
-$(obj)law.c:
-	@rm -f $(obj)law.c
-	ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
-
-$(obj)nand_boot_fsl_elbc.c:
-	@rm -f $(obj)nand_boot_fsl_elbc.c
-	ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
-	       $(obj)nand_boot_fsl_elbc.c
-
-$(obj)ns16550.c:
-	@rm -f $(obj)ns16550.c
-	ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
-
-$(obj)resetvec.S:
-	@rm -f $(obj)resetvec.S
-	ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S
-
-$(obj)fixed_ivor.S:
-	@rm -f $(obj)fixed_ivor.S
-	ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $(obj)fixed_ivor.S
-
-$(obj)start.S: $(obj)fixed_ivor.S
-	@rm -f $(obj)start.S
-	ln -sf $(SRCTREE)/$(CPUDIR)/start.S $(obj)start.S
-
-$(obj)tlb.c:
-	@rm -f $(obj)tlb.c
-	ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $(obj)tlb.c
-
-$(obj)tlb_table.c:
-	@rm -f $(obj)tlb_table.c
-	ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
-
-ifneq ($(OBJTREE), $(SRCTREE))
-$(obj)nand_boot.c:
-	@rm -f $(obj)nand_boot.c
-	ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
-endif
-
-#########################################################################
-
-$(obj)%.o:	$(obj)%.S
-	$(CC) $(AFLAGS) -c -o $@ $<
-
-$(obj)%.o:	$(obj)%.c
-	$(CC) $(CFLAGS) -c -o $@ $<
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- *
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-void sdram_init(void)
-{
-	ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
-
-	__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
-	__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
-#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
-	__raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
-	__raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
-#endif
-	__raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
-
-	__raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
-	__raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
-	__raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
-
-	__raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
-	__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
-	__raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
-
-	__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
-	__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
-	__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl);
-
-	/* Set, but do not enable the memory */
-	__raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
-
-	asm volatile("sync;isync");
-	udelay(500);
-
-	/* Let the controller go */
-	out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
-
-	set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1);
-}
-
-void board_init_f(ulong bootflag)
-{
-	u32 plat_ratio;
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-#ifndef CONFIG_QE
-	ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
-#endif
-
-	/* initialize selected port with appropriate baud rate */
-	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
-	plat_ratio >>= 1;
-	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
-
-	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
-			gd->bus_clk / 16 / CONFIG_BAUDRATE);
-
-	puts("\nNAND boot... ");
-
-#ifndef CONFIG_QE
-	/* init DDR3 reset signal */
-	__raw_writel(0x02000000, &pgpio->gpdir);
-	__raw_writel(0x00200000, &pgpio->gpodr);
-	__raw_writel(0x00000000, &pgpio->gpdat);
-	udelay(1000);
-	__raw_writel(0x00200000, &pgpio->gpdat);
-	udelay(1000);
-	__raw_writel(0x00000000, &pgpio->gpdir);
-#endif
-
-	/* Initialize the DDR3 */
-	sdram_init();
-
-	/* copy code to RAM and jump to it - this should not return */
-	/* NOTE - code has to be copied out of NAND buffer before
-	 * other blocks can be read.
-	 */
-	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
-			CONFIG_SYS_NAND_U_BOOT_RELOC);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
-	nand_boot();
-}
-
-void putc(char c)
-{
-	if (c == '\n')
-		NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
-	NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
-	while (*str)
-		putc(*str++);
-}
...	...	@@ -140,16 +140,25 @@
140	140	#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
141	141	#endif
142	142
143		-#if defined(CONFIG_NAND) && defined(CONFIG_NAND_FSL_ELBC)
144		-#define CONFIG_NAND_U_BOOT
145		-#define CONFIG_SYS_EXTRA_ENV_RELOC
146		-#define CONFIG_SYS_RAMBOOT
147		-#define CONFIG_SYS_TEXT_BASE_SPL 0xff800000
148		-#ifdef CONFIG_NAND_SPL
149		-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL
150		-#else
151		-#define CONFIG_SYS_TEXT_BASE 0x11001000
152		-#endif /* CONFIG_NAND_SPL */
	143	+#ifdef CONFIG_NAND
	144	+#define CONFIG_SPL
	145	+#define CONFIG_SPL_INIT_MINIMAL
	146	+#define CONFIG_SPL_SERIAL_SUPPORT
	147	+#define CONFIG_SPL_NAND_SUPPORT
	148	+#define CONFIG_SPL_NAND_MINIMAL
	149	+#define CONFIG_SPL_FLUSH_IMAGE
	150	+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
	151	+
	152	+#define CONFIG_SYS_TEXT_BASE 0x00201000
	153	+#define CONFIG_SPL_TEXT_BASE 0xfffff000
	154	+#define CONFIG_SPL_MAX_SIZE (4 * 1024)
	155	+#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
	156	+#define CONFIG_SPL_RELOC_STACK 0x00100000
	157	+#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SPL_MAX_SIZE)
	158	+#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
	159	+#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
	160	+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
	161	+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
153	162	#endif
154	163
155	164	#ifndef CONFIG_SYS_TEXT_BASE
156	165
...	...	@@ -161,8 +170,12 @@
161	170	#endif
162	171
163	172	#ifndef CONFIG_SYS_MONITOR_BASE
	173	+#ifdef CONFIG_SPL_BUILD
	174	+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
	175	+#else
164	176	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
165	177	#endif
	178	+#endif
166	179
167	180	/* High Level Configuration Options */
168	181	#define CONFIG_BOOKE
...	...	@@ -221,7 +234,7 @@
221	234
222	235	/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
223	236	SPL code*/
224		-#if defined(CONFIG_NAND_SPL)
	237	+#ifdef CONFIG_SPL_BUILD
225	238	#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
226	239	#endif
227	240
...	...	@@ -392,15 +405,6 @@
392	405	#define CONFIG_CMD_NAND
393	406	#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
394	407
395		-/* NAND boot: 4K NAND loader config */
396		-#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
397		-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SYS_NAND_SPL_SIZE)
398		-#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE)
399		-#define CONFIG_SYS_NAND_U_BOOT_START 0x11000000
400		-#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
401		-#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
402		-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
403		-
404	408	#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
405	409	\| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
406	410	\| BR_PS_8 /* Port Size = 8 bit */ \
...	...	@@ -461,7 +465,7 @@
461	465	OR_GPCM_SCY \| OR_GPCM_TRLX \| OR_GPCM_EHTR \| \
462	466	OR_GPCM_EAD)
463	467
464		-#ifdef CONFIG_NAND_U_BOOT
	468	+#ifdef CONFIG_NAND
465	469	#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
466	470	#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
467	471	#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
...	...	@@ -511,7 +515,7 @@
511	515	#define CONFIG_SYS_NS16550_SERIAL
512	516	#define CONFIG_SYS_NS16550_REG_SIZE 1
513	517	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
514		-#ifdef CONFIG_NAND_SPL
	518	+#ifdef CONFIG_SPL_BUILD
515	519	#define CONFIG_NS16550_MIN_FUNCTIONS
516	520	#endif
517	521
...	...	@@ -709,7 +713,6 @@
709	713	/*
710	714	* Environment
711	715	*/
712		-#ifdef CONFIG_SYS_RAMBOOT
713	716	#ifdef CONFIG_RAMBOOT_SPIFLASH
714	717	#define CONFIG_ENV_IS_IN_SPI_FLASH
715	718	#define CONFIG_ENV_SPI_BUS 0
716	719
717	720
...	...	@@ -724,16 +727,15 @@
724	727	#define CONFIG_FSL_FIXED_MMC_LOCATION
725	728	#define CONFIG_ENV_SIZE 0x2000
726	729	#define CONFIG_SYS_MMC_ENV_DEV 0
727		-#elif defined(CONFIG_NAND_U_BOOT)
	730	+#elif defined(CONFIG_NAND)
728	731	#define CONFIG_ENV_IS_IN_NAND
729	732	#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
730	733	#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
731	734	#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
732		-#else
	735	+#elif defined(CONFIG_SYS_RAMBOOT)
733	736	#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
734	737	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
735	738	#define CONFIG_ENV_SIZE 0x2000
736		-#endif
737	739	#else
738	740	#define CONFIG_ENV_IS_IN_FLASH
739	741	#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
1		-#
2		-# (C) Copyright 2007
3		-# Stefan Roese, DENX Software Engineering, sr@denx.de.
4		-#
5		-# Copyright 2011 Freescale Semiconductor, Inc.
6		-#
7		-# See file CREDITS for list of people who contributed to this
8		-# project.
9		-#
10		-# This program is free software; you can redistribute it and/or
11		-# modify it under the terms of the GNU General Public License as
12		-# published by the Free Software Foundation; either version 2 of
13		-# the License, or (at your option) any later version.
14		-#
15		-# This program is distributed in the hope that it will be useful,
16		-# but WITHOUT ANY WARRANTY; without even the implied warranty of
17		-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18		-# GNU General Public License for more details.
19		-#
20		-# You should have received a copy of the GNU General Public License
21		-# along with this program; if not, write to the Free Software
22		-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23		-# MA 02111-1307 USA
24		-#
25		-
26		-NAND_SPL := y
27		-CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
28		-PAD_TO := 0xff801000
29		-
30		-include $(TOPDIR)/config.mk
31		-
32		-nandobj := $(OBJTREE)/nand_spl/
33		-
34		-LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
35		-LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
36		-LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
37		- $(LDFLAGS) $(LDFLAGS_FINAL)
38		-AFLAGS += -DCONFIG_NAND_SPL
39		-CFLAGS += -DCONFIG_NAND_SPL
40		-
41		-SOBJS = start.o resetvec.o
42		-COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
43		- nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
44		-
45		-SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
46		-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
47		-__OBJS := $(SOBJS) $(COBJS)
48		-LNDIR := $(nandobj)board/$(BOARDDIR)
49		-
50		-ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
51		-
52		-all: $(obj).depend $(ALL)
53		-
54		-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
55		- $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
56		-
57		-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
58		- $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
59		-
60		-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
61		- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
62		- -Map $(nandobj)u-boot-spl.map \
63		- -o $(nandobj)u-boot-spl
64		-
65		-# The following line expands into whole rule which generates $(LSTSCRIPT),
66		-# the file containing u-boots LG-array linker section. This is included into
67		-# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
68		-$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
69		-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT)
70		- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@
71		-
72		-# create symbolic links for common files
73		-
74		-$(obj)cache.c:
75		- @rm -f $(obj)cache.c
76		- ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
77		-
78		-$(obj)cpu_init_early.c:
79		- @rm -f $(obj)cpu_init_early.c
80		- ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c
81		-
82		-$(obj)spl_minimal.c:
83		- @rm -f $(obj)spl_minimal.c
84		- ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $(obj)spl_minimal.c
85		-
86		-$(obj)fsl_law.c:
87		- @rm -f $(obj)fsl_law.c
88		- ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $(obj)fsl_law.c
89		-
90		-$(obj)law.c:
91		- @rm -f $(obj)law.c
92		- ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
93		-
94		-$(obj)nand_boot_fsl_elbc.c:
95		- @rm -f $(obj)nand_boot_fsl_elbc.c
96		- ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
97		- $(obj)nand_boot_fsl_elbc.c
98		-
99		-$(obj)ns16550.c:
100		- @rm -f $(obj)ns16550.c
101		- ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
102		-
103		-$(obj)resetvec.S:
104		- @rm -f $(obj)resetvec.S
105		- ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S
106		-
107		-$(obj)fixed_ivor.S:
108		- @rm -f $(obj)fixed_ivor.S
109		- ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $(obj)fixed_ivor.S
110		-
111		-$(obj)start.S: $(obj)fixed_ivor.S
112		- @rm -f $(obj)start.S
113		- ln -sf $(SRCTREE)/$(CPUDIR)/start.S $(obj)start.S
114		-
115		-$(obj)tlb.c:
116		- @rm -f $(obj)tlb.c
117		- ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $(obj)tlb.c
118		-
119		-$(obj)tlb_table.c:
120		- @rm -f $(obj)tlb_table.c
121		- ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
122		-
123		-ifneq ($(OBJTREE), $(SRCTREE))
124		-$(obj)nand_boot.c:
125		- @rm -f $(obj)nand_boot.c
126		- ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
127		-endif
128		-
129		-#########################################################################
130		-
131		-$(obj)%.o: $(obj)%.S
132		- $(CC) $(AFLAGS) -c -o $@ $<
133		-
134		-$(obj)%.o: $(obj)%.c
135		- $(CC) $(CFLAGS) -c -o $@ $<
136		-
137		-# defines $(obj).depend target
138		-include $(SRCTREE)/rules.mk
139		-
140		-sinclude $(obj).depend
141		-
142		-#########################################################################
1		-/*
2		- * Copyright 2011 Freescale Semiconductor, Inc.
3		- *
4		- * This program is free software; you can redistribute it and/or
5		- * modify it under the terms of the GNU General Public License as
6		- * published by the Free Software Foundation; either version 2 of
7		- * the License, or (at your option) any later version.
8		- *
9		- * This program is distributed in the hope that it will be useful,
10		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
11		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12		- *
13		- * GNU General Public License for more details.
14		- *
15		- * You should have received a copy of the GNU General Public License
16		- * along with this program; if not, write to the Free Software
17		- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18		- * MA 02111-1307 USA
19		- *
20		- */
21		-
22		-#include <common.h>
23		-#include <ns16550.h>
24		-#include <asm/io.h>
25		-#include <nand.h>
26		-#include <asm/fsl_law.h>
27		-#include <asm/fsl_ddr_sdram.h>
28		-#include <asm/global_data.h>
29		-
30		-DECLARE_GLOBAL_DATA_PTR;
31		-
32		-/*
33		- * Fixed sdram init -- doesn't use serial presence detect.
34		- */
35		-void sdram_init(void)
36		-{
37		- ccsr_ddr_t ddr = (ccsr_ddr_t )CONFIG_SYS_MPC85xx_DDR_ADDR;
38		-
39		- __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
40		- __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
41		-#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
42		- __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
43		- __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
44		-#endif
45		- __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
46		- __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
47		- __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
48		- __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
49		-
50		- __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
51		- __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
52		- __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
53		-
54		- __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
55		- __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
56		- __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
57		-
58		- __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
59		- __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
60		- __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
61		- __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl);
62		-
63		- /* Set, but do not enable the memory */
64		- __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
65		-
66		- asm volatile("sync;isync");
67		- udelay(500);
68		-
69		- /* Let the controller go */
70		- out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) \| SDRAM_CFG_MEM_EN);
71		-
72		- set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1);
73		-}
74		-
75		-void board_init_f(ulong bootflag)
76		-{
77		- u32 plat_ratio;
78		- ccsr_gur_t gur = (void )CONFIG_SYS_MPC85xx_GUTS_ADDR;
79		-#ifndef CONFIG_QE
80		- ccsr_gpio_t pgpio = (void )(CONFIG_SYS_MPC85xx_GPIO_ADDR);
81		-#endif
82		-
83		- /* initialize selected port with appropriate baud rate */
84		- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
85		- plat_ratio >>= 1;
86		- gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
87		-
88		- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
89		- gd->bus_clk / 16 / CONFIG_BAUDRATE);
90		-
91		- puts("\nNAND boot... ");
92		-
93		-#ifndef CONFIG_QE
94		- /* init DDR3 reset signal */
95		- __raw_writel(0x02000000, &pgpio->gpdir);
96		- __raw_writel(0x00200000, &pgpio->gpodr);
97		- __raw_writel(0x00000000, &pgpio->gpdat);
98		- udelay(1000);
99		- __raw_writel(0x00200000, &pgpio->gpdat);
100		- udelay(1000);
101		- __raw_writel(0x00000000, &pgpio->gpdir);
102		-#endif
103		-
104		- /* Initialize the DDR3 */
105		- sdram_init();
106		-
107		- /* copy code to RAM and jump to it - this should not return */
108		- /* NOTE - code has to be copied out of NAND buffer before
109		- * other blocks can be read.
110		- */
111		- relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
112		- CONFIG_SYS_NAND_U_BOOT_RELOC);
113		-}
114		-
115		-void board_init_r(gd_t *gd, ulong dest_addr)
116		-{
117		- nand_boot();
118		-}
119		-
120		-void putc(char c)
121		-{
122		- if (c == '\n')
123		- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
124		-
125		- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
126		-}
127		-
128		-void puts(const char *str)
129		-{
130		- while (*str)
131		- putc(*str++);
132		-}