Eric Lee / smarc-uboot

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Commit a807645ee6a36218b18e52d2039984f27288a14d

Authored by wdenk
1 parent 91a0ce965d

Add support for EXBITGEN board

Showing 13 changed files with 2233 additions and 6 deletions Side-by-side Diff

... ... @@ -2,6 +2,8 @@
2 2 Changes since U-Boot 0.4.0:
3 3 ======================================================================
4 4  
  5 +* Add support for EXBITGEN board
  6 +
5 7 * Add support for SL8245 board
6 8  
7 9 ======================================================================
... ... @@ -94,6 +94,8 @@
94 94 PCIPPC2 MPC750
95 95 PCIPPC6 MPC750
96 96  
  97 + EXBITGEN PPC405GP
  98 +
97 99 Jon Diekema <jon.diekema@smiths-aerospace.com>
98 100  
99 101 sbc8260 MPC8260
... ... @@ -37,8 +37,8 @@
37 37 SM850 SPD823TS svm_sc8xx SXNI855T \
38 38 TOP860 TQM823L TQM823L_LCD TQM850L \
39 39 TQM855L TQM860L TTTech v37 \
40   -"
41 40  
  41 +
42 42 #########################################################################
43 43 ## PPC4xx Systems
44 44 #########################################################################
... ... @@ -47,10 +47,10 @@
47 47 ADCIOP AR405 ASH405 BUBINGA405EP \
48 48 CANBT CPCI405 CPCI4052 CPCI405AB \
49 49 CPCI440 CPCIISER4 CRAYL1 DASA_SIM \
50   - DU405 EBONY ERIC MIP405 \
51   - MIP405T ML2 OCRTC ORSG \
52   - PCI405 PIP405 PMC405 W7OLMC \
53   - W7OLMG WALNUT405 \
  50 + DU405 EBONY ERIC EXBITGEN \
  51 + MIP405 MIP405T ML2 OCRTC \
  52 + ORSG PCI405 PIP405 PMC405 \
  53 + W7OLMC W7OLMG WALNUT405 \
54 54 "
55 55  
56 56 #########################################################################
... ... @@ -466,6 +466,9 @@
466 466 ERIC_config:unconfig
467 467 @./mkconfig $(@:_config=) ppc ppc4xx eric
468 468  
  469 +EXBITGEN_config:unconfig
  470 + @./mkconfig $(@:_config=) ppc ppc4xx exbitgen
  471 +
469 472 MIP405_config:unconfig
470 473 @./mkconfig $(@:_config=) ppc ppc4xx mip405 mpl
471 474  
board/exbitgen/Makefile
Diff comments   View file @ a807645
  1 +#
  2 +# (C) Copyright 2000
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +include $(TOPDIR)/config.mk
  25 +
  26 +LIB = lib$(BOARD).a
  27 +
  28 +OBJS = $(BOARD).o flash.o
  29 +
  30 +SOBJS = init.o
  31 +
  32 +
  33 +$(LIB): $(OBJS) $(SOBJS)
  34 + $(AR) crv $@ $^
  35 +
  36 +clean:
  37 + rm -f $(SOBJS) $(OBJS)
  38 +
  39 +distclean: clean
  40 + rm -f $(LIB) core *.bak .depend
  41 +
  42 +#########################################################################
  43 +
  44 +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
  45 + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
  46 +
  47 +sinclude .depend
  48 +
  49 +#########################################################################
board/exbitgen/config.mk
Diff comments   View file @ a807645
  1 +#
  2 +# (C) Copyright 2000
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +#
  25 +# ExbitGen board
  26 +#
  27 +
  28 +LDFLAGS += $(LINKER_UNDEFS)
  29 +
  30 +TEXT_BASE := 0xFFF80000
  31 +#TEXT_BASE := 0x00100000
  32 +
  33 +PLATFORM_RELFLAGS := $(PLATFORM_RELFLAGS)
board/exbitgen/exbitgen.c
Diff comments   View file @ a807645
  1 +#include <asm/u-boot.h>
  2 +#include <asm/processor.h>
  3 +#include <common.h>
  4 +#include "exbitgen.h"
  5 +
  6 +/* ************************************************************************ */
  7 +int board_pre_init (void)
  8 +/* ------------------------------------------------------------------------ --
  9 + * Purpose :
  10 + * Remarks :
  11 + * Restrictions:
  12 + * See also :
  13 + * Example :
  14 + * ************************************************************************ */
  15 +{
  16 + unsigned long i;
  17 +
  18 + /*-------------------------------------------------------------------------+
  19 + | Interrupt controller setup for the Walnut board.
  20 + | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
  21 + | IRQ 16 405GP internally generated; active low; level sensitive
  22 + | IRQ 17-24 RESERVED
  23 + | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
  24 + | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
  25 + | IRQ 27 (EXT IRQ 2) Not Used
  26 + | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
  27 + | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
  28 + | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
  29 + | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
  30 + | Note for Walnut board:
  31 + | An interrupt taken for the FPGA (IRQ 25) indicates that either
  32 + | the Mouse, Keyboard, IRDA, or External Expansion caused the
  33 + | interrupt. The FPGA must be read to determine which device
  34 + | caused the interrupt. The default setting of the FPGA clears
  35 + |
  36 + +-------------------------------------------------------------------------*/
  37 +
  38 + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
  39 + mtdcr (uicer, 0x00000000); /* disable all ints */
  40 + mtdcr (uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */
  41 + mtdcr (uicpr, 0xFFFFFF90); /* set int polarities */
  42 + mtdcr (uictr, 0x10000000); /* set int trigger levels */
  43 + mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
  44 + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
  45 +
  46 + /* Perform reset of PHY connected to PPC via register in CPLD */
  47 + out8 (PHY_CTRL_ADDR, 0x2e); /* activate nRESET,FDX,F100,ANEN, enable output */
  48 + for (i = 0; i < 10000000; i++) {
  49 + ;
  50 + }
  51 + out8 (PHY_CTRL_ADDR, 0x2f); /* deactivate nRESET */
  52 +
  53 + return 0;
  54 +}
  55 +
  56 +
  57 +/* ************************************************************************ */
  58 +int checkboard (void)
  59 +/* ------------------------------------------------------------------------ --
  60 + * Purpose :
  61 + * Remarks :
  62 + * Restrictions:
  63 + * See also :
  64 + * Example :
  65 + * ************************************************************************ */
  66 +{
  67 + printf ("Exbit H/W id: %d\n", in8 (HW_ID_ADDR));
  68 + return (0);
  69 +}
  70 +
  71 +/* ************************************************************************ */
  72 +long int initdram (int board_type)
  73 +/* ------------------------------------------------------------------------ --
  74 + * Purpose : Determines size of mounted DRAM.
  75 + * Remarks : Size is determined by reading SDRAM configuration registers as
  76 + * set up by sdram_init.
  77 + * Restrictions:
  78 + * See also :
  79 + * Example :
  80 + * ************************************************************************ */
  81 +{
  82 + ulong tot_size;
  83 + ulong bank_size;
  84 + ulong tmp;
  85 +
  86 + tot_size = 0;
  87 +
  88 + mtdcr (memcfga, mem_mb0cf);
  89 + tmp = mfdcr (memcfgd);
  90 + if (tmp & 0x00000001) {
  91 + bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
  92 + tot_size += bank_size;
  93 + }
  94 +
  95 + mtdcr (memcfga, mem_mb1cf);
  96 + tmp = mfdcr (memcfgd);
  97 + if (tmp & 0x00000001) {
  98 + bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
  99 + tot_size += bank_size;
  100 + }
  101 +
  102 + mtdcr (memcfga, mem_mb2cf);
  103 + tmp = mfdcr (memcfgd);
  104 + if (tmp & 0x00000001) {
  105 + bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
  106 + tot_size += bank_size;
  107 + }
  108 +
  109 + mtdcr (memcfga, mem_mb3cf);
  110 + tmp = mfdcr (memcfgd);
  111 + if (tmp & 0x00000001) {
  112 + bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
  113 + tot_size += bank_size;
  114 + }
  115 +
  116 + return tot_size;
  117 +}
board/exbitgen/exbitgen.h
Diff comments   View file @ a807645
  1 +/*
  2 + * (C) Copyright 2003
  3 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#define GPIO_CPU_LED GPIO_3
  25 +
  26 +
  27 +#define CPLD_BASE 0x10000000 /* t.b.m. */
  28 +#define DEBUG_LEDS_ADDR CPLD_BASE + 0x01
  29 +#define HW_ID_ADDR CPLD_BASE + 0x02
  30 +#define DIP_SWITCH_ADDR CPLD_BASE + 0x04
  31 +#define PHY_CTRL_ADDR CPLD_BASE + 0x05
  32 +#define SPI_OUT_ADDR CPLD_BASE + 0x07
  33 +#define SPI_IN_ADDR CPLD_BASE + 0x08
  34 +#define MDIO_OUT_ADDR CPLD_BASE + 0x09
  35 +#define MDIO_IN_ADDR CPLD_BASE + 0x0A
  36 +#define MISC_OUT_ADDR CPLD_BASE + 0x0B
  37 +
  38 +/* Addresses used on I2C bus */
  39 +#define LM75_CHIP_ADDR 0x9C
  40 +#define LM75_CPU_ADDR 0x9E
  41 +#define SDRAM_SPD_ADDR 0xA0
  42 +
  43 +#define SDRAM_SPD_WRITE_ADDRESS (SDRAM_SPD_ADDR)
  44 +#define SDRAM_SPD_READ_ADDRESS (SDRAM_SPD_ADDR+1)
  45 +
  46 +#ifndef FALSE
  47 +#define FALSE 0
  48 +#endif
  49 +
  50 +#ifndef TRUE
  51 +#define TRUE 1
  52 +#endif
board/exbitgen/flash.c
Diff comments   View file @ a807645
  1 +/*
  2 + * (C) Copyright 2003
  3 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +/*
  25 + * Modified 4/5/2001
  26 + * Wait for completion of each sector erase command issued
  27 + * 4/5/2001
  28 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
  29 + */
  30 +
  31 +#include <asm/u-boot.h>
  32 +#include <asm/processor.h>
  33 +#include <ppc4xx.h>
  34 +#include <common.h>
  35 +
  36 +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
  37 +
  38 +/*-----------------------------------------------------------------------
  39 + * Functions
  40 + */
  41 +static ulong flash_get_size (vu_long *addr, flash_info_t *info);
  42 +static int write_word (flash_info_t *info, ulong dest, ulong data);
  43 +
  44 +#ifdef MEIGSBOARD_ONBOARD_FLASH /* onboard = 2MB */
  45 +# ifdef CONFIG_EXBITGEN
  46 +# define FLASH_WORD_SIZE unsigned long
  47 +# endif
  48 +#else /* Meigsboard socket flash = 512KB */
  49 +# ifdef CONFIG_EXBITGEN
  50 +# define FLASH_WORD_SIZE unsigned char
  51 +# endif
  52 +#endif
  53 +
  54 +#ifdef CONFIG_EXBITGEN
  55 +#define ADDR0 0x5555
  56 +#define ADDR1 0x2aaa
  57 +#define FLASH_WORD_SIZE unsigned char
  58 +#endif
  59 +
  60 +/*-----------------------------------------------------------------------
  61 + */
  62 +
  63 +unsigned long flash_init (void)
  64 +{
  65 + unsigned long bank_size;
  66 + unsigned long tot_size;
  67 + unsigned long bank_addr;
  68 + int i;
  69 +
  70 + /* Init: no FLASHes known */
  71 + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
  72 + flash_info[i].flash_id = FLASH_UNKNOWN;
  73 + flash_info[i].size = 0;
  74 + }
  75 +
  76 + tot_size = 0;
  77 +
  78 + /* Detect Boot Flash */
  79 + bank_addr = CFG_FLASH0_BASE;
  80 + bank_size = flash_get_size((vu_long *)bank_addr, &flash_info[0]);
  81 + if (bank_size > 0) {
  82 + (void)flash_protect(FLAG_PROTECT_CLEAR,
  83 + bank_addr,
  84 + bank_addr + bank_size - 1,
  85 + &flash_info[0]);
  86 + }
  87 + if (flash_info[0].flash_id == FLASH_UNKNOWN) {
  88 + printf ("## Unknown FLASH on Boot Flash Bank\n");
  89 + }
  90 + flash_info[0].size = bank_size;
  91 + tot_size += bank_size;
  92 +
  93 + /* Detect Application Flash */
  94 + bank_addr = CFG_FLASH1_BASE;
  95 + for (i = 1; i < CFG_MAX_FLASH_BANKS; ++i) {
  96 + bank_size = flash_get_size((vu_long *)bank_addr, &flash_info[i]);
  97 + if (flash_info[i].flash_id == FLASH_UNKNOWN) {
  98 + break;
  99 + }
  100 + if (bank_size > 0) {
  101 + (void)flash_protect(FLAG_PROTECT_CLEAR,
  102 + bank_addr,
  103 + bank_addr + bank_size - 1,
  104 + &flash_info[i]);
  105 + }
  106 + flash_info[i].size = bank_size;
  107 + tot_size += bank_size;
  108 + bank_addr += bank_size;
  109 + }
  110 + if (flash_info[1].flash_id == FLASH_UNKNOWN) {
  111 + printf ("## Unknown FLASH on Application Flash Bank\n");
  112 + }
  113 +
  114 + /* Protect monitor and environment sectors */
  115 +#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
  116 + flash_protect(FLAG_PROTECT_SET,
  117 + CFG_MONITOR_BASE,
  118 + CFG_MONITOR_BASE + monitor_flash_len - 1,
  119 + &flash_info[0]);
  120 +#if 0xfffffffc >= CFG_FLASH0_BASE
  121 +#if 0xfffffffc <= CFG_FLASH0_BASE + CFG_FLASH0_SIZE - 1
  122 + flash_protect(FLAG_PROTECT_SET,
  123 + 0xfffffffc, 0xffffffff,
  124 + &flash_info[0]);
  125 +#endif
  126 +#endif
  127 +#endif
  128 +
  129 +#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
  130 + flash_protect(FLAG_PROTECT_SET,
  131 + CFG_ENV_ADDR,
  132 + CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
  133 + &flash_info[0]);
  134 +#endif
  135 +
  136 + return tot_size;
  137 +}
  138 +
  139 +/*-----------------------------------------------------------------------
  140 + */
  141 +void flash_print_info (flash_info_t *info)
  142 +{
  143 + int i;
  144 +
  145 + if (info->flash_id == FLASH_UNKNOWN) {
  146 + printf ("missing or unknown FLASH type\n");
  147 + return;
  148 + }
  149 +
  150 + switch (info->flash_id & FLASH_VENDMASK) {
  151 + case FLASH_MAN_AMD: printf ("AMD "); break;
  152 + case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
  153 + case FLASH_MAN_SST: printf ("SST "); break;
  154 + default: printf ("Unknown Vendor "); break;
  155 + }
  156 +
  157 + switch (info->flash_id & FLASH_TYPEMASK) {
  158 + case FLASH_AM040: printf ("AM29F040 (512 Kbit, uniform sector size)\n");
  159 + break;
  160 + case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
  161 + break;
  162 + case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
  163 + break;
  164 + case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
  165 + break;
  166 + case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
  167 + break;
  168 + case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
  169 + break;
  170 + case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
  171 + break;
  172 + case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
  173 + break;
  174 + case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
  175 + break;
  176 + case FLASH_AMDLV033C: printf ("AM29LV033C (32 Mbit, uniform sector size)\n");
  177 + break;
  178 + case FLASH_AMDLV065D: printf ("AM29LV065D (64 Mbit, uniform sector size)\n");
  179 + break;
  180 + case FLASH_SST800A: printf ("SST39LF/VF800 (8 Mbit, uniform sector size)\n");
  181 + break;
  182 + case FLASH_SST160A: printf ("SST39LF/VF160 (16 Mbit, uniform sector size)\n");
  183 + break;
  184 + case FLASH_SST040: printf ("SST39LF/VF040 (4 Mbit, uniform sector size)\n");
  185 + break;
  186 + default: printf ("Unknown Chip Type\n");
  187 + break;
  188 + }
  189 +
  190 + printf (" Size: %ld KB in %d Sectors\n",
  191 + info->size >> 10, info->sector_count);
  192 +
  193 + printf (" Sector Start Addresses:");
  194 + for (i=0; i<info->sector_count; ++i) {
  195 + if ((i % 5) == 0)
  196 + printf ("\n ");
  197 + printf (" %08lX%s",
  198 + info->start[i],
  199 + info->protect[i] ? " (RO)" : " "
  200 + );
  201 + }
  202 + printf ("\n");
  203 +}
  204 +
  205 +/*-----------------------------------------------------------------------
  206 + */
  207 +
  208 +
  209 +/*-----------------------------------------------------------------------
  210 + */
  211 +
  212 +/*
  213 + * The following code cannot be run from FLASH!
  214 + */
  215 +static ulong flash_get_size (vu_long *addr, flash_info_t *info)
  216 +{
  217 + short i;
  218 + FLASH_WORD_SIZE value;
  219 + ulong base = (ulong)addr;
  220 + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
  221 +
  222 + /* Write auto select command: read Manufacturer ID */
  223 + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
  224 + addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
  225 + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00900090;
  226 +
  227 + value = addr2[0];
  228 +
  229 + switch (value) {
  230 + case (FLASH_WORD_SIZE)AMD_MANUFACT:
  231 + info->flash_id = FLASH_MAN_AMD;
  232 + break;
  233 + case (FLASH_WORD_SIZE)FUJ_MANUFACT:
  234 + info->flash_id = FLASH_MAN_FUJ;
  235 + break;
  236 + case (FLASH_WORD_SIZE)SST_MANUFACT:
  237 + info->flash_id = FLASH_MAN_SST;
  238 + break;
  239 + default:
  240 + info->flash_id = FLASH_UNKNOWN;
  241 + info->sector_count = 0;
  242 + info->size = 0;
  243 + return (0); /* no or unknown flash */
  244 + }
  245 +
  246 + value = addr2[1]; /* device ID */
  247 +
  248 + switch (value) {
  249 + case (FLASH_WORD_SIZE)AMD_ID_F040B:
  250 + info->flash_id += FLASH_AM040;
  251 + info->sector_count = 8;
  252 + info->size = 0x0080000; /* => 512 ko */
  253 + break;
  254 + case (FLASH_WORD_SIZE)AMD_ID_LV400T:
  255 + info->flash_id += FLASH_AM400T;
  256 + info->sector_count = 11;
  257 + info->size = 0x00080000;
  258 + break; /* => 0.5 MB */
  259 +
  260 + case (FLASH_WORD_SIZE)AMD_ID_LV400B:
  261 + info->flash_id += FLASH_AM400B;
  262 + info->sector_count = 11;
  263 + info->size = 0x00080000;
  264 + break; /* => 0.5 MB */
  265 +
  266 + case (FLASH_WORD_SIZE)AMD_ID_LV800T:
  267 + info->flash_id += FLASH_AM800T;
  268 + info->sector_count = 19;
  269 + info->size = 0x00100000;
  270 + break; /* => 1 MB */
  271 +
  272 + case (FLASH_WORD_SIZE)AMD_ID_LV800B:
  273 + info->flash_id += FLASH_AM800B;
  274 + info->sector_count = 19;
  275 + info->size = 0x00100000;
  276 + break; /* => 1 MB */
  277 +
  278 + case (FLASH_WORD_SIZE)AMD_ID_LV160T:
  279 + info->flash_id += FLASH_AM160T;
  280 + info->sector_count = 35;
  281 + info->size = 0x00200000;
  282 + break; /* => 2 MB */
  283 +
  284 + case (FLASH_WORD_SIZE)AMD_ID_LV160B:
  285 + info->flash_id += FLASH_AM160B;
  286 + info->sector_count = 35;
  287 + info->size = 0x00200000;
  288 + break; /* => 2 MB */
  289 +
  290 + case (FLASH_WORD_SIZE)AMD_ID_LV033C:
  291 + info->flash_id += FLASH_AMDLV033C;
  292 + info->sector_count = 64;
  293 + info->size = 0x00400000;
  294 + break; /* => 4 MB */
  295 +
  296 + case (FLASH_WORD_SIZE)AMD_ID_LV065D:
  297 + info->flash_id += FLASH_AMDLV065D;
  298 + info->sector_count = 128;
  299 + info->size = 0x00800000;
  300 + break; /* => 8 MB */
  301 +
  302 + case (FLASH_WORD_SIZE)AMD_ID_LV320T:
  303 + info->flash_id += FLASH_AM320T;
  304 + info->sector_count = 67;
  305 + info->size = 0x00400000;
  306 + break; /* => 4 MB */
  307 +
  308 + case (FLASH_WORD_SIZE)AMD_ID_LV320B:
  309 + info->flash_id += FLASH_AM320B;
  310 + info->sector_count = 67;
  311 + info->size = 0x00400000;
  312 + break; /* => 4 MB */
  313 +
  314 + case (FLASH_WORD_SIZE)SST_ID_xF800A:
  315 + info->flash_id += FLASH_SST800A;
  316 + info->sector_count = 16;
  317 + info->size = 0x00100000;
  318 + break; /* => 1 MB */
  319 +
  320 + case (FLASH_WORD_SIZE)SST_ID_xF160A:
  321 + info->flash_id += FLASH_SST160A;
  322 + info->sector_count = 32;
  323 + info->size = 0x00200000;
  324 + break; /* => 2 MB */
  325 + case (FLASH_WORD_SIZE)SST_ID_xF040:
  326 + info->flash_id += FLASH_SST040;
  327 + info->sector_count = 128;
  328 + info->size = 0x00080000;
  329 + break; /* => 512KB */
  330 +
  331 + default:
  332 + info->flash_id = FLASH_UNKNOWN;
  333 + return (0); /* => no or unknown flash */
  334 +
  335 + }
  336 +
  337 + /* set up sector start address table */
  338 + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
  339 + (info->flash_id == FLASH_AM040) ||
  340 + (info->flash_id == FLASH_AMDLV033C) ||
  341 + (info->flash_id == FLASH_AMDLV065D)) {
  342 + ulong sectsize = info->size / info->sector_count;
  343 + for (i = 0; i < info->sector_count; i++)
  344 + info->start[i] = base + (i * sectsize);
  345 + } else {
  346 + if (info->flash_id & FLASH_BTYPE) {
  347 + /* set sector offsets for bottom boot block type */
  348 + info->start[0] = base + 0x00000000;
  349 + info->start[1] = base + 0x00004000;
  350 + info->start[2] = base + 0x00006000;
  351 + info->start[3] = base + 0x00008000;
  352 + for (i = 4; i < info->sector_count; i++) {
  353 + info->start[i] = base + (i * 0x00010000) - 0x00030000;
  354 + }
  355 + } else {
  356 + /* set sector offsets for top boot block type */
  357 + i = info->sector_count - 1;
  358 + info->start[i--] = base + info->size - 0x00004000;
  359 + info->start[i--] = base + info->size - 0x00006000;
  360 + info->start[i--] = base + info->size - 0x00008000;
  361 + for (; i >= 0; i--) {
  362 + info->start[i] = base + i * 0x00010000;
  363 + }
  364 + }
  365 + }
  366 +
  367 + /* check for protected sectors */
  368 + for (i = 0; i < info->sector_count; i++) {
  369 + /* read sector protection at sector address, (A7 .. A0) = 0x02 */
  370 + /* D0 = 1 if protected */
  371 +
  372 + addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
  373 + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
  374 + info->protect[i] = 0;
  375 + else
  376 + info->protect[i] = addr2[2] & 1;
  377 + }
  378 +
  379 + /* switch to the read mode */
  380 + if (info->flash_id != FLASH_UNKNOWN) {
  381 + addr2 = (FLASH_WORD_SIZE *)info->start[0];
  382 + *addr2 = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
  383 + }
  384 +
  385 + return (info->size);
  386 +}
  387 +
  388 +/*-----------------------------------------------------------------------
  389 + */
  390 +
  391 +int flash_erase (flash_info_t *info, int s_first, int s_last)
  392 +{
  393 + volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
  394 + volatile FLASH_WORD_SIZE *addr2;
  395 + int flag, prot, sect;
  396 + ulong start, now, last;
  397 +
  398 + if ((s_first < 0) || (s_first > s_last)) {
  399 + if (info->flash_id == FLASH_UNKNOWN) {
  400 + printf ("- missing\n");
  401 + } else {
  402 + printf ("- no sectors to erase\n");
  403 + }
  404 + return 1;
  405 + }
  406 +
  407 + if (info->flash_id == FLASH_UNKNOWN) {
  408 + printf ("Can't erase unknown flash type - aborted\n");
  409 + return 1;
  410 + }
  411 +
  412 + prot = 0;
  413 + for (sect=s_first; sect<=s_last; ++sect) {
  414 + if (info->protect[sect]) {
  415 + prot++;
  416 + }
  417 + }
  418 +
  419 + if (prot) {
  420 + printf ("- Warning: %d protected sectors will not be erased!\n",
  421 + prot);
  422 + } else {
  423 + printf ("\n");
  424 + }
  425 +
  426 + start = get_timer (0);
  427 + last = start;
  428 + /* Start erase on unprotected sectors */
  429 + for (sect = s_first; sect <= s_last; sect++) {
  430 + if (info->protect[sect] == 0) { /* not protected */
  431 + addr2 = (FLASH_WORD_SIZE *)(info->start[sect]);
  432 +
  433 + /* Disable interrupts which might cause a timeout here */
  434 + flag = disable_interrupts();
  435 +
  436 + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
  437 + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
  438 + addr[ADDR0] = (FLASH_WORD_SIZE)0x00800080;
  439 + addr[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
  440 + addr[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
  441 + addr2[0] = (FLASH_WORD_SIZE)0x00300030;
  442 +
  443 + /* re-enable interrupts if necessary */
  444 + if (flag)
  445 + enable_interrupts();
  446 +
  447 + /* wait at least 80us - let's wait 1 ms */
  448 + udelay (1000);
  449 +
  450 + while ((addr2[0] & 0x00800080) !=
  451 + (FLASH_WORD_SIZE) 0x00800080) {
  452 + if ((now=get_timer(start)) >
  453 + CFG_FLASH_ERASE_TOUT) {
  454 + printf ("Timeout\n");
  455 + addr[0] = (FLASH_WORD_SIZE)0x00F000F0;
  456 + return 1;
  457 + }
  458 +
  459 + /* show that we're waiting */
  460 + if ((now - last) > 1000) { /* every second */
  461 + putc ('.');
  462 + last = now;
  463 + }
  464 + }
  465 +
  466 + addr[0] = (FLASH_WORD_SIZE)0x00F000F0;
  467 + }
  468 + }
  469 +
  470 + printf (" done\n");
  471 +
  472 + return 0;
  473 +}
  474 +
  475 +/*-----------------------------------------------------------------------
  476 + * Copy memory to flash, returns:
  477 + * 0 - OK
  478 + * 1 - write timeout
  479 + * 2 - Flash not erased
  480 + */
  481 +
  482 +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
  483 +{
  484 + ulong cp, wp, data;
  485 + int i, l, rc;
  486 +
  487 + wp = (addr & ~3); /* get lower word aligned address */
  488 +
  489 + /*
  490 + * handle unaligned start bytes
  491 + */
  492 + if ((l = addr - wp) != 0) {
  493 + data = 0;
  494 + for (i=0, cp=wp; i<l; ++i, ++cp) {
  495 + data = (data << 8) | (*(uchar *)cp);
  496 + }
  497 + for (; i<4 && cnt>0; ++i) {
  498 + data = (data << 8) | *src++;
  499 + --cnt;
  500 + ++cp;
  501 + }
  502 + for (; cnt==0 && i<4; ++i, ++cp) {
  503 + data = (data << 8) | (*(uchar *)cp);
  504 + }
  505 +
  506 + if ((rc = write_word(info, wp, data)) != 0) {
  507 + return (rc);
  508 + }
  509 + wp += 4;
  510 + }
  511 +
  512 + /*
  513 + * handle word aligned part
  514 + */
  515 + while (cnt >= 4) {
  516 + data = 0;
  517 + for (i=0; i<4; ++i) {
  518 + data = (data << 8) | *src++;
  519 + }
  520 + if ((rc = write_word(info, wp, data)) != 0) {
  521 + return (rc);
  522 + }
  523 + wp += 4;
  524 + cnt -= 4;
  525 + }
  526 +
  527 + if (cnt == 0) {
  528 + return (0);
  529 + }
  530 +
  531 + /*
  532 + * handle unaligned tail bytes
  533 + */
  534 + data = 0;
  535 + for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
  536 + data = (data << 8) | *src++;
  537 + --cnt;
  538 + }
  539 + for (; i<4; ++i, ++cp) {
  540 + data = (data << 8) | (*(uchar *)cp);
  541 + }
  542 +
  543 + return (write_word(info, wp, data));
  544 +}
  545 +
  546 +/*-----------------------------------------------------------------------
  547 + * Write a word to Flash, returns:
  548 + * 0 - OK
  549 + * 1 - write timeout
  550 + * 2 - Flash not erased
  551 + */
  552 +static int write_word (flash_info_t *info, ulong dest, ulong data)
  553 +{
  554 + volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]);
  555 + volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest;
  556 + volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
  557 + ulong start;
  558 + int flag;
  559 + int i;
  560 +
  561 + /* Check if Flash is (sufficiently) erased */
  562 + if ((*((volatile ulong *)dest) & data) != data) {
  563 + printf("dest = %08lx, *dest = %08lx, data = %08lx\n",
  564 + dest, *(volatile ulong *)dest, data);
  565 + return 2;
  566 + }
  567 +
  568 + for (i=0; i < 4/sizeof(FLASH_WORD_SIZE); i++) {
  569 + /* Disable interrupts which might cause a timeout here */
  570 + flag = disable_interrupts();
  571 +
  572 + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
  573 + addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
  574 + addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0;
  575 + dest2[i] = data2[i];
  576 +
  577 + /* re-enable interrupts if necessary */
  578 + if (flag)
  579 + enable_interrupts();
  580 +
  581 + /* data polling for D7 */
  582 + start = get_timer (0);
  583 + while ((dest2[i] & 0x00800080) != (data2[i] & 0x00800080)) {
  584 + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
  585 + addr2[0] = (FLASH_WORD_SIZE)0x00F000F0;
  586 + return (1);
  587 + }
  588 + }
  589 + }
  590 +
  591 + addr2[0] = (FLASH_WORD_SIZE)0x00F000F0;
  592 +
  593 + return (0);
  594 +}
  595 +
  596 +/*-----------------------------------------------------------------------
  597 + */
board/exbitgen/init.S
Diff comments   View file @ a807645
Changes suppressed. Click to show
  1 +/*----------------------------------------------------------------------+
  2 + *
  3 + * This source code has been made available to you by IBM on an AS-IS
  4 + * basis. Anyone receiving this source is licensed under IBM
  5 + * copyrights to use it in any way he or she deems fit, including
  6 + * copying it, modifying it, compiling it, and redistributing it either
  7 + * with or without modifications. No license under IBM patents or
  8 + * patent applications is to be implied by the copyright license.
  9 + *
  10 + * Any user of this software should understand that IBM cannot provide
  11 + * technical support for this software and will not be responsible for
  12 + * any consequences resulting from the use of this software.
  13 + *
  14 + * Any person who transfers this source code or any derivative work
  15 + * must include the IBM copyright notice, this paragraph, and the
  16 + * preceding two paragraphs in the transferred software.
  17 + *
  18 + * COPYRIGHT I B M CORPORATION 1995
  19 + * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
  20 + *-----------------------------------------------------------------------
  21 + */
  22 +
  23 +#include <config.h>
  24 +#include <ppc4xx.h>
  25 +#include "config.h"
  26 +
  27 +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
  28 +#define FPGA_BRDC 0xF0300004
  29 +
  30 +#include <ppc_asm.tmpl>
  31 +#include <ppc_defs.h>
  32 +
  33 +#include <asm/cache.h>
  34 +#include <asm/mmu.h>
  35 +
  36 +#include "exbitgen.h"
  37 +
  38 +/* IIC declarations (This is an extract from 405gp_i2c.h, which also contains some */
  39 +/* c-code declarations and consequently can't be included here). */
  40 +/* (Possibly to be solved somehow else). */
  41 +/*--------------------------------------------------------------------- */
  42 +#define I2C_REGISTERS_BASE_ADDRESS 0xEF600500
  43 +#define IIC_MDBUF (I2C_REGISTERS_BASE_ADDRESS+IICMDBUF)
  44 +#define IIC_SDBUF (I2C_REGISTERS_BASE_ADDRESS+IICSDBUF)
  45 +#define IIC_LMADR (I2C_REGISTERS_BASE_ADDRESS+IICLMADR)
  46 +#define IIC_HMADR (I2C_REGISTERS_BASE_ADDRESS+IICHMADR)
  47 +#define IIC_CNTL (I2C_REGISTERS_BASE_ADDRESS+IICCNTL)
  48 +#define IIC_MDCNTL (I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL)
  49 +#define IIC_STS (I2C_REGISTERS_BASE_ADDRESS+IICSTS)
  50 +#define IIC_EXTSTS (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)
  51 +#define IIC_LSADR (I2C_REGISTERS_BASE_ADDRESS+IICLSADR)
  52 +#define IIC_HSADR (I2C_REGISTERS_BASE_ADDRESS+IICHSADR)
  53 +#define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV)
  54 +#define IIC_INTRMSK (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)
  55 +#define IIC_XFRCNT (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)
  56 +#define IIC_XTCNTLSS (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)
  57 +#define IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL)
  58 +
  59 +/* MDCNTL Register Bit definition */
  60 +#define IIC_MDCNTL_HSCL 0x01
  61 +#define IIC_MDCNTL_EUBS 0x02
  62 +#define IIC_MDCNTL_FMDB 0x40
  63 +#define IIC_MDCNTL_FSDB 0x80
  64 +
  65 +/* CNTL Register Bit definition */
  66 +#define IIC_CNTL_PT 0x01
  67 +#define IIC_CNTL_READ 0x02
  68 +#define IIC_CNTL_CHT 0x04
  69 +
  70 +/* STS Register Bit definition */
  71 +#define IIC_STS_PT 0X01
  72 +#define IIC_STS_ERR 0X04
  73 +#define IIC_STS_MDBS 0X20
  74 +
  75 +/* EXTSTS Register Bit definition */
  76 +#define IIC_EXTSTS_XFRA 0X01
  77 +#define IIC_EXTSTS_ICT 0X02
  78 +#define IIC_EXTSTS_LA 0X04
  79 +
  80 +/* LED codes used for inditing progress and errors during read of DIMM SPD. */
  81 +/*--------------------------------------------------------------------- */
  82 +#define LED_SDRAM_CODE_1 0xef
  83 +#define LED_SDRAM_CODE_2 0xee
  84 +#define LED_SDRAM_CODE_3 0xed
  85 +#define LED_SDRAM_CODE_4 0xec
  86 +#define LED_SDRAM_CODE_5 0xeb
  87 +#define LED_SDRAM_CODE_6 0xea
  88 +#define LED_SDRAM_CODE_7 0xe9
  89 +#define LED_SDRAM_CODE_8 0xe8
  90 +#define LED_SDRAM_CODE_9 0xe7
  91 +#define LED_SDRAM_CODE_10 0xe6
  92 +#define LED_SDRAM_CODE_11 0xe5
  93 +#define LED_SDRAM_CODE_12 0xe4
  94 +#define LED_SDRAM_CODE_13 0xe3
  95 +#define LED_SDRAM_CODE_14 0xe2
  96 +#define LED_SDRAM_CODE_15 0xe1
  97 +#define LED_SDRAM_CODE_16 0xe0
  98 +
  99 +
  100 +#define TIMEBASE_10PS (1000000000 / CONFIG_SYS_CLK_FREQ) * 100
  101 +
  102 +#define FLASH_8bit_AP 0x9B015480
  103 +#define FLASH_8bit_CR 0xFFF18000 /* 1MB(min), 8bit, R/W */
  104 +
  105 +#define FLASH_32bit_AP 0x9B015480
  106 +#define FLASH_32bit_CR 0xFFE3C000 /* 2MB, 32bit, R/W */
  107 +
  108 +
  109 +#define WDCR_EBC(reg,val) addi r4,0,reg;\
  110 + mtdcr ebccfga,r4;\
  111 + addis r4,0,val@h;\
  112 + ori r4,r4,val@l;\
  113 + mtdcr ebccfgd,r4
  114 +
  115 +/*---------------------------------------------------------------------
  116 + * Function: ext_bus_cntlr_init
  117 + * Description: Initializes the External Bus Controller for the external
  118 + * peripherals. IMPORTANT: For pass1 this code must run from
  119 + * cache since you can not reliably change a peripheral banks
  120 + * timing register (pbxap) while running code from that bank.
  121 + * For ex., since we are running from ROM on bank 0, we can NOT
  122 + * execute the code that modifies bank 0 timings from ROM, so
  123 + * we run it from cache.
  124 + * Bank 0 - Boot flash
  125 + * Bank 1-4 - application flash
  126 + * Bank 5 - CPLD
  127 + * Bank 6 - not used
  128 + * Bank 7 - Heathrow chip
  129 + *---------------------------------------------------------------------
  130 + */
  131 + .globl ext_bus_cntlr_init
  132 +ext_bus_cntlr_init:
  133 + mflr r4 /* save link register */
  134 + bl ..getAddr
  135 +..getAddr:
  136 + mflr r3 /* get address of ..getAddr */
  137 + mtlr r4 /* restore link register */
  138 + addi r4,0,14 /* set ctr to 10; used to prefetch */
  139 + mtctr r4 /* 10 cache lines to fit this function */
  140 + /* in cache (gives us 8x10=80 instrctns) */
  141 +..ebcloop:
  142 + icbt r0,r3 /* prefetch cache line for addr in r3 */
  143 + addi r3,r3,32 /* move to next cache line */
  144 + bdnz ..ebcloop /* continue for 10 cache lines */
  145 +
  146 + mflr r31 /* save link register */
  147 +
  148 + /*-----------------------------------------------------------
  149 + * Delay to ensure all accesses to ROM are complete before changing
  150 + * bank 0 timings. 200usec should be enough.
  151 + * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
  152 + *-----------------------------------------------------------
  153 + */
  154 +
  155 + addis r3,0,0x0
  156 + ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
  157 + mtctr r3
  158 +..spinlp:
  159 + bdnz ..spinlp /* spin loop */
  160 +
  161 + /*---------------------------------------------------------------
  162 + * Memory Bank 0 (Boot Flash) initialization
  163 + *---------------------------------------------------------------
  164 + */
  165 + WDCR_EBC(pb0ap, FLASH_32bit_AP)
  166 + WDCR_EBC(pb0cr, 0xffe38000)
  167 +/*pnc WDCR_EBC(pb0cr, FLASH_32bit_CR) */
  168 +
  169 + /*---------------------------------------------------------------
  170 + * Memory Bank 5 (CPLD) initialization
  171 + *---------------------------------------------------------------
  172 + */
  173 + WDCR_EBC(pb5ap, 0x01010040)
  174 +/*jsa recommendation: WDCR_EBC(pb5ap, 0x00010040) */
  175 + WDCR_EBC(pb5cr, 0x10038000)
  176 +
  177 + /*--------------------------------------------------------------- */
  178 + /* Memory Bank 6 (not used) initialization */
  179 + /*--------------------------------------------------------------- */
  180 + WDCR_EBC(pb6cr, 0x00000000)
  181 +
  182 + /* Read HW ID to determine whether old H2 board or new generic CPU board */
  183 + addis r3, 0, HW_ID_ADDR@h
  184 + ori r3, r3, HW_ID_ADDR@l
  185 + lbz r3,0x0000(r3)
  186 + cmpi 0, r3, 1 /* if (HW_ID==1) */
  187 + beq setup_h2evalboard /* then jump */
  188 + cmpi 0, r3, 2 /* if (HW_ID==2) */
  189 + beq setup_genieboard /* then jump */
  190 + cmpi 0, r3, 3 /* if (HW_ID==3) */
  191 + beq setup_genieboard /* then jump */
  192 +
  193 +setup_genieboard:
  194 + /*--------------------------------------------------------------- */
  195 + /* Memory Bank 1 (Application Flash) initialization for generic CPU board */
  196 + /*--------------------------------------------------------------- */
  197 +/* WDCR_EBC(pb1ap, 0x7b015480) /###* T.B.M. */
  198 +/* WDCR_EBC(pb1ap, 0x7F8FFE80) /###* T.B.M. */
  199 + WDCR_EBC(pb1ap, 0x9b015480) /* hlb-20020207: burst 8 bit 6 cycles */
  200 +
  201 +/* WDCR_EBC(pb1cr, 0x20098000) /###* 16 MB */
  202 + WDCR_EBC(pb1cr, 0x200B8000) /* 32 MB */
  203 +
  204 + /*--------------------------------------------------------------- */
  205 + /* Memory Bank 4 (Onboard FPGA) initialization for generic CPU board */
  206 + /*--------------------------------------------------------------- */
  207 + WDCR_EBC(pb4ap, 0x01010000) /* */
  208 + WDCR_EBC(pb4cr, 0x1021c000) /* */
  209 +
  210 + /*--------------------------------------------------------------- */
  211 + /* Memory Bank 7 (Heathrow chip on Reference board) initialization */
  212 + /*--------------------------------------------------------------- */
  213 + WDCR_EBC(pb7ap, 0x200ffe80) /* No Ready, many wait states (let reflections die out) */
  214 + WDCR_EBC(pb7cr, 0X4001A000)
  215 +
  216 + bl setup_continue
  217 +
  218 +
  219 +setup_h2evalboard:
  220 + /*--------------------------------------------------------------- */
  221 + /* Memory Bank 1 (Application Flash) initialization */
  222 + /*--------------------------------------------------------------- */
  223 + WDCR_EBC(pb1ap, 0x7b015480) /* T.B.M. */
  224 +/*3010 WDCR_EBC(pb1ap, 0x7F8FFE80) /###* T.B.M. */
  225 + WDCR_EBC(pb1cr, 0x20058000)
  226 +
  227 + /*--------------------------------------------------------------- */
  228 + /* Memory Bank 2 (Application Flash) initialization */
  229 + /*--------------------------------------------------------------- */
  230 + WDCR_EBC(pb2ap, 0x7b015480) /* T.B.M. */
  231 +/*3010 WDCR_EBC(pb2ap, 0x7F8FFE80) /###* T.B.M. */
  232 + WDCR_EBC(pb2cr, 0x20458000)
  233 +
  234 + /*--------------------------------------------------------------- */
  235 + /* Memory Bank 3 (Application Flash) initialization */
  236 + /*--------------------------------------------------------------- */
  237 + WDCR_EBC(pb3ap, 0x7b015480) /* T.B.M. */
  238 +/*3010 WDCR_EBC(pb3ap, 0x7F8FFE80) /###* T.B.M. */
  239 + WDCR_EBC(pb3cr, 0x20858000)
  240 +
  241 + /*--------------------------------------------------------------- */
  242 + /* Memory Bank 4 (Application Flash) initialization */
  243 + /*--------------------------------------------------------------- */
  244 + WDCR_EBC(pb4ap, 0x7b015480) /* T.B.M. */
  245 +/*3010 WDCR_EBC(pb4ap, 0x7F8FFE80) /###* T.B.M. */
  246 + WDCR_EBC(pb4cr, 0x20C58000)
  247 +
  248 + /*--------------------------------------------------------------- */
  249 + /* Memory Bank 7 (Heathrow chip) initialization */
  250 + /*--------------------------------------------------------------- */
  251 + WDCR_EBC(pb7ap, 0x02000280) /* No Ready, 4 wait states */
  252 + WDCR_EBC(pb7cr, 0X4001A000)
  253 +
  254 +setup_continue:
  255 +
  256 +
  257 + mtlr r31 /* restore lr */
  258 + nop /* pass2 DCR errata #8 */
  259 + blr
  260 +
  261 +/*--------------------------------------------------------------------- */
  262 +/* Function: sdram_init */
  263 +/* Description: Configures SDRAM memory banks. */
  264 +/*--------------------------------------------------------------------- */
  265 + .globl sdram_init
  266 +
  267 +sdram_init:
  268 +#if CFG_MONITOR_BASE < CFG_FLASH_BASE
  269 + blr
  270 +#else
  271 + mflr r31
  272 +
  273 + /* output SDRAM code on LEDs */
  274 + addi r4, 0, LED_SDRAM_CODE_1
  275 + addis r5, 0, 0x1000
  276 + ori r5, r5, 0x0001
  277 + stb r4,0(r5)
  278 + eieio
  279 +
  280 + /* Read contents of spd */
  281 + /*--------------------- */
  282 + bl read_spd
  283 +
  284 + /*----------------------------------------------------------- */
  285 + /* */
  286 + /* */
  287 + /* Update SDRAM timing register */
  288 + /* */
  289 + /* */
  290 + /*----------------------------------------------------------- */
  291 +
  292 + /* Read PLL feedback divider and calculate clock period of local bus in */
  293 + /* granularity of 10 ps. Save clock period in r30 */
  294 + /*-------------------------------------------------------------- */
  295 + mfdcr r4, pllmd
  296 + addi r9, 0, 25
  297 + srw r4, r4, r9
  298 + andi. r4, r4, 0x07
  299 + addis r5, 0, TIMEBASE_10PS@h
  300 + ori r5, r5, TIMEBASE_10PS@l
  301 + divwu r30, r5, r4
  302 +
  303 + /* Determine CASL */
  304 + /*--------------- */
  305 + bl find_casl /* Returns CASL in r3 */
  306 +
  307 + /* Calc trp_clocks = (trp * 100 + (clk - 1)) / clk */
  308 + /* (trp read from byte 27 in granularity of 1 ns) */
  309 + /*------------------------------------------------ */
  310 + mulli r16, r16, 100
  311 + add r16, r16, r30
  312 + addi r6, 0, 1
  313 + subf r16, r6, r16
  314 + divwu r16, r16, r30
  315 +
  316 + /* Calc trcd_clocks = (trcd * 100 + (clk - 1) ) / clk */
  317 + /* (trcd read from byte 29 in granularity of 1 ns) */
  318 + /*--------------------------------------------------- */
  319 + mulli r17, r17, 100
  320 + add r17, r17, r30
  321 + addi r6, 0, 1
  322 + subf r17, r6, r17
  323 + divwu r17, r17, r30
  324 +
  325 + /* Calc tras_clocks = (tras * 100 + (clk - 1) ) / clk */
  326 + /* (tras read from byte 30 in granularity of 1 ns) */
  327 + /*--------------------------------------------------- */
  328 + mulli r18, r18, 100
  329 + add r18, r18, r30
  330 + addi r6, 0, 1
  331 + subf r18, r6, r18
  332 + divwu r18, r18, r30
  333 +
  334 + /* Calc trc_clocks = trp_clocks + tras_clocks */
  335 + /*------------------------------------------- */
  336 + add r18, r18, r16
  337 +
  338 + /* CASL value */
  339 + /*----------- */
  340 + addi r9, 0, 23
  341 + slw r4, r3, r9
  342 +
  343 + /* PTA = trp_clocks - 1 */
  344 + /*--------------------- */
  345 + addi r6, 0, 1
  346 + subf r5, r6, r16
  347 + addi r9, 0, 18
  348 + slw r5, r5, r9
  349 + or r4, r4, r5
  350 +
  351 + /* CTP = trc_clocks - trp_clocks - trcd_clocks - 1 */
  352 + /*------------------------------------------------ */
  353 + addi r5, r18, 0
  354 + subf r5, r16, r5
  355 + subf r5, r17, r5
  356 + addi r6, 0, 1
  357 + subf r5, r6, r5
  358 + addi r9, 0, 16
  359 + slw r5, r5, r9
  360 + or r4, r4, r5
  361 +
  362 + /* LDF = 1 */
  363 + /*-------- */
  364 + ori r4, r4, 0x4000
  365 +
  366 + /* RFTA = trc_clocks - 4 */
  367 + /*---------------------- */
  368 + addi r6, 0, 4
  369 + subf r5, r6, r18
  370 + addi r9, 0, 2
  371 + slw r5, r5, r9
  372 + or r4, r4, r5
  373 +
  374 + /* RCD = trcd_clocks - 1 */
  375 + /*---------------------- */
  376 + addi r6, 0, 1
  377 + subf r5, r6, r17
  378 + or r4, r4, r5
  379 +
  380 + /*----------------------------------------------------------- */
  381 + /* Set SDTR1 */
  382 + /*----------------------------------------------------------- */
  383 + addi r5,0,mem_sdtr1
  384 + mtdcr memcfga,r5
  385 + mtdcr memcfgd,r4
  386 +
  387 + /*----------------------------------------------------------- */
  388 + /* */
  389 + /* */
  390 + /* Update memory bank 0-3 configuration registers */
  391 + /* */
  392 + /* */
  393 + /*----------------------------------------------------------- */
  394 +
  395 + /* Build contents of configuration register for bank 0 into r6 */
  396 + /*------------------------------------------------------------ */
  397 + bl find_mode /* returns addressing mode in r3 */
  398 + addi r29, r3, 0 /* save mode temporarily in r29 */
  399 + bl find_size_code /* returns size code in r3 */
  400 + addi r9, 0, 17 /* bit offset of size code in configuration register */
  401 + slw r3, r3, r9 /* */
  402 + addi r9, 0, 13 /* bit offset of addressing mode in configuration register */
  403 + slw r29, r29, r9 /* */
  404 + or r3, r29, r3 /* merge size code and addressing mode */
  405 + ori r6, r3, CFG_SDRAM_BASE + 1 /* insert base address and enable bank */
  406 +
  407 + /* Calculate banksize r15 = (density << 22) / 2 */
  408 + /*--------------------------------------------- */
  409 + addi r9, 0, 21
  410 + slw r15, r15, r9
  411 +
  412 + /* Set SDRAM bank 0 register and adjust r6 for next bank */
  413 + /*------------------------------------------------------ */
  414 + addi r7,0,mem_mb0cf
  415 + mtdcr memcfga,r7
  416 + mtdcr memcfgd,r6
  417 +
  418 + add r6, r6, r15 /* add bank size to base address for next bank */
  419 +
  420 + /* If two rows/banks then set SDRAM bank 1 register and adjust r6 for next bank */
  421 + /*---------------------------------------------------------------------------- */
  422 + cmpi 0, r12, 2
  423 + bne b1skip
  424 +
  425 + addi r7,0,mem_mb1cf
  426 + mtdcr memcfga,r7
  427 + mtdcr memcfgd,r6
  428 +
  429 + add r6, r6, r15 /* add bank size to base address for next bank */
  430 +
  431 + /* Set SDRAM bank 2 register and adjust r6 for next bank */
  432 + /*------------------------------------------------------ */
  433 +b1skip: addi r7,0,mem_mb2cf
  434 + mtdcr memcfga,r7
  435 + mtdcr memcfgd,r6
  436 +
  437 + add r6, r6, r15 /* add bank size to base address for next bank */
  438 +
  439 + /* If two rows/banks then set SDRAM bank 3 register */
  440 + /*------------------------------------------------ */
  441 + cmpi 0, r12, 2
  442 + bne b3skip
  443 +
  444 + addi r7,0,mem_mb3cf
  445 + mtdcr memcfga,r7
  446 + mtdcr memcfgd,r6
  447 +b3skip:
  448 +
  449 + /*----------------------------------------------------------- */
  450 + /* Set RTR */
  451 + /*----------------------------------------------------------- */
  452 + cmpi 0, r30, 1600
  453 + bge rtr_1
  454 + addis r7, 0, 0x05F0 /* RTR value for 100Mhz */
  455 + bl rtr_2
  456 +rtr_1: addis r7, 0, 0x03F8
  457 +rtr_2: addi r4,0,mem_rtr
  458 + mtdcr memcfga,r4
  459 + mtdcr memcfgd,r7
  460 +
  461 + /*----------------------------------------------------------- */
  462 + /* Delay to ensure 200usec have elapsed since reset. Assume worst */
  463 + /* case that the core is running 200Mhz: */
  464 + /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
  465 + /*----------------------------------------------------------- */
  466 + addis r3,0,0x0000
  467 + ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
  468 + mtctr r3
  469 +..spinlp2:
  470 + bdnz ..spinlp2 /* spin loop */
  471 +
  472 + /*----------------------------------------------------------- */
  473 + /* Set memory controller options reg, MCOPT1. */
  474 + /* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */
  475 + /* read/prefetch. */
  476 + /*----------------------------------------------------------- */
  477 + addi r4,0,mem_mcopt1
  478 + mtdcr memcfga,r4
  479 + addis r4,0,0x80C0 /* set DC_EN=1 */
  480 + ori r4,r4,0x0000
  481 + mtdcr memcfgd,r4
  482 +
  483 +
  484 + /*----------------------------------------------------------- */
  485 + /* Delay to ensure 10msec have elapsed since reset. This is */
  486 + /* required for the MPC952 to stabalize. Assume worst */
  487 + /* case that the core is running 200Mhz: */
  488 + /* 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles */
  489 + /* This delay should occur before accessing SDRAM. */
  490 + /*----------------------------------------------------------- */
  491 + addis r3,0,0x001E
  492 + ori r3,r3,0x8480 /* ensure 10msec have passed since reset */
  493 + mtctr r3
  494 +..spinlp3:
  495 + bdnz ..spinlp3 /* spin loop */
  496 +
  497 + /* output SDRAM code on LEDs */
  498 + addi r4, 0, LED_SDRAM_CODE_16
  499 + addis r5, 0, 0x1000
  500 + ori r5, r5, 0x0001
  501 + stb r4,0(r5)
  502 + eieio
  503 +
  504 + mtlr r31 /* restore lr */
  505 + blr
  506 +
  507 +/*--------------------------------------------------------------------- */
  508 +/* Function: read_spd */
  509 +/* Description: Reads contents of SPD and saves parameters to be used for */
  510 +/* configuration in dedicated registers (see code below). */
  511 +/*--------------------------------------------------------------------- */
  512 +
  513 +#define WRITE_I2C(reg,val) \
  514 + addi r3,0,val;\
  515 + addis r4, 0, 0xef60;\
  516 + ori r4, r4, 0x0500 + reg;\
  517 + stb r3, 0(r4);\
  518 + eieio
  519 +
  520 +#define READ_I2C(reg) \
  521 + addis r3, 0, 0xef60;\
  522 + ori r3, r3, 0x0500 + reg;\
  523 + lbz r3, 0x0000(r3);\
  524 + eieio
  525 +
  526 +read_spd:
  527 +
  528 + mflr r5
  529 +
  530 + /* Initialize i2c */
  531 + /*--------------- */
  532 + WRITE_I2C(IICLMADR, 0x00) /* clear lo master address */
  533 + WRITE_I2C(IICHMADR, 0x00) /* clear hi master address */
  534 + WRITE_I2C(IICLSADR, 0x00) /* clear lo slave address */
  535 + WRITE_I2C(IICHSADR, 0x00) /* clear hi slave address */
  536 + WRITE_I2C(IICSTS, 0x08) /* update status register */
  537 + WRITE_I2C(IICEXTSTS, 0x8f)
  538 + WRITE_I2C(IICCLKDIV, 0x05)
  539 + WRITE_I2C(IICINTRMSK, 0x00) /* no interrupts */
  540 + WRITE_I2C(IICXFRCNT, 0x00) /* clear transfer count */
  541 + WRITE_I2C(IICXTCNTLSS, 0xf0) /* clear extended control & stat */
  542 + WRITE_I2C(IICMDCNTL, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB) /* mode control */
  543 + READ_I2C(IICMDCNTL)
  544 + ori r3, r3, IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL
  545 + WRITE_I2C(IICMDCNTL, r3) /* mode control */
  546 + WRITE_I2C(IICCNTL, 0x00) /* clear control reg */
  547 +
  548 + /* Wait until initialization completed */
  549 + /*------------------------------------ */
  550 + bl wait_i2c_transfer_done
  551 +
  552 + WRITE_I2C(IICHMADR, 0x00) /* 7-bit addressing */
  553 + WRITE_I2C(IICLMADR, SDRAM_SPD_WRITE_ADDRESS)
  554 +
  555 + /* Write 0 into buffer(start address) */
  556 + /*----------------------------------- */
  557 + WRITE_I2C(IICMDBUF, 0x00);
  558 +
  559 + /* Wait a little */
  560 + /*-------------- */
  561 + addis r3,0,0x0000
  562 + ori r3,r3,0xA000
  563 + mtctr r3
  564 +in02: bdnz in02
  565 +
  566 + /* Issue write command */
  567 + /*-------------------- */
  568 + WRITE_I2C(IICCNTL, IIC_CNTL_PT)
  569 + bl wait_i2c_transfer_done
  570 +
  571 + /* Read 128 bytes */
  572 + /*--------------- */
  573 + addi r7, 0, 0 /* byte counter in r7 */
  574 + addi r8, 0, 0 /* checksum in r8 */
  575 +rdlp:
  576 + /* issue read command */
  577 + /*------------------- */
  578 + cmpi 0, r7, 127
  579 + blt rd01
  580 + WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_PT)
  581 + bl rd02
  582 +rd01: WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_CHT | IIC_CNTL_PT)
  583 +rd02: bl wait_i2c_transfer_done
  584 +
  585 + /* Fetch byte from buffer */
  586 + /*----------------------- */
  587 + READ_I2C(IICMDBUF)
  588 +
  589 + /* Retrieve parameters that are going to be used during configuration. */
  590 + /* Save them in dedicated registers. */
  591 + /*------------------------------------------------------------ */
  592 + cmpi 0, r7, 3 /* Save byte 3 in r10 */
  593 + bne rd10
  594 + addi r10, r3, 0
  595 +rd10: cmpi 0, r7, 4 /* Save byte 4 in r11 */
  596 + bne rd11
  597 + addi r11, r3, 0
  598 +rd11: cmpi 0, r7, 5 /* Save byte 5 in r12 */
  599 + bne rd12
  600 + addi r12, r3, 0
  601 +rd12: cmpi 0, r7, 17 /* Save byte 17 in r13 */
  602 + bne rd13
  603 + addi r13, r3, 0
  604 +rd13: cmpi 0, r7, 18 /* Save byte 18 in r14 */
  605 + bne rd14
  606 + addi r14, r3, 0
  607 +rd14: cmpi 0, r7, 31 /* Save byte 31 in r15 */
  608 + bne rd15
  609 + addi r15, r3, 0
  610 +rd15: cmpi 0, r7, 27 /* Save byte 27 in r16 */
  611 + bne rd16
  612 + addi r16, r3, 0
  613 +rd16: cmpi 0, r7, 29 /* Save byte 29 in r17 */
  614 + bne rd17
  615 + addi r17, r3, 0
  616 +rd17: cmpi 0, r7, 30 /* Save byte 30 in r18 */
  617 + bne rd18
  618 + addi r18, r3, 0
  619 +rd18: cmpi 0, r7, 9 /* Save byte 9 in r19 */
  620 + bne rd19
  621 + addi r19, r3, 0
  622 +rd19: cmpi 0, r7, 23 /* Save byte 23 in r20 */
  623 + bne rd20
  624 + addi r20, r3, 0
  625 +rd20: cmpi 0, r7, 25 /* Save byte 25 in r21 */
  626 + bne rd21
  627 + addi r21, r3, 0
  628 +rd21:
  629 +
  630 + /* Calculate checksum of the first 63 bytes */
  631 + /*----------------------------------------- */
  632 + cmpi 0, r7, 63
  633 + bgt rd31
  634 + beq rd30
  635 + add r8, r8, r3
  636 + bl rd31
  637 +
  638 + /* Verify checksum at byte 63 */
  639 + /*--------------------------- */
  640 +rd30: andi. r8, r8, 0xff /* use only 8 bits */
  641 + cmp 0, r8, r3
  642 + beq rd31
  643 + addi r4, 0, LED_SDRAM_CODE_8
  644 + addis r5, 0, 0x1000
  645 + ori r5, r5, 0x0001
  646 + stb r4,0(r5)
  647 + eieio
  648 +rderr: bl rderr
  649 +
  650 +rd31:
  651 +
  652 + /* Increment byte counter and check whether all bytes have been read. */
  653 + /*------------------------------------------------------------------- */
  654 + addi r7, r7, 1
  655 + cmpi 0, r7, 127
  656 + bgt rd05
  657 + bl rdlp
  658 +rd05:
  659 + mtlr r5 /* restore lr */
  660 + blr
  661 +
  662 +wait_i2c_transfer_done:
  663 + mflr r6
  664 +wt01: READ_I2C(IICSTS)
  665 + andi. r4, r3, IIC_STS_PT
  666 + cmpi 0, r4, IIC_STS_PT
  667 + beq wt01
  668 + mtlr r6 /* restore lr */
  669 + blr
  670 +
  671 +/*--------------------------------------------------------------------- */
  672 +/* Function: find_mode */
  673 +/* Description: Determines addressing mode to be used dependent on */
  674 +/* number of rows (r10 = byte 3 from SPD), number of columns (r11 = */
  675 +/* byte 4 from SPD) and number of banks (r13 = byte 17 from SPD). */
  676 +/* mode is returned in r3. */
  677 +/* (It would be nicer having a table, pnc). */
  678 +/*--------------------------------------------------------------------- */
  679 +find_mode:
  680 +
  681 + mflr r5
  682 +
  683 + cmpi 0, r10, 11
  684 + bne fm01
  685 + cmpi 0, r11, 9
  686 + bne fm01
  687 + cmpi 0, r13, 2
  688 + bne fm01
  689 + addi r3, 0, 1
  690 + bl fmfound
  691 +
  692 +fm01: cmpi 0, r10, 11
  693 + bne fm02
  694 + cmpi 0, r11, 10
  695 + bne fm02
  696 + cmpi 0, r13, 2
  697 + bne fm02
  698 + addi r3, 0, 1
  699 + bl fmfound
  700 +
  701 +fm02: cmpi 0, r10, 12
  702 + bne fm03
  703 + cmpi 0, r11, 9
  704 + bne fm03
  705 + cmpi 0, r13, 4
  706 + bne fm03
  707 + addi r3, 0, 2
  708 + bl fmfound
  709 +
  710 +fm03: cmpi 0, r10, 12
  711 + bne fm04
  712 + cmpi 0, r11, 10
  713 + bne fm04
  714 + cmpi 0, r13, 4
  715 + bne fm04
  716 + addi r3, 0, 2
  717 + bl fmfound
  718 +
  719 +fm04: cmpi 0, r10, 13
  720 + bne fm05
  721 + cmpi 0, r11, 9
  722 + bne fm05
  723 + cmpi 0, r13, 4
  724 + bne fm05
  725 + addi r3, 0, 3
  726 + bl fmfound
  727 +
  728 +fm05: cmpi 0, r10, 13
  729 + bne fm06
  730 + cmpi 0, r11, 10
  731 + bne fm06
  732 + cmpi 0, r13, 4
  733 + bne fm06
  734 + addi r3, 0, 3
  735 + bl fmfound
  736 +
  737 +fm06: cmpi 0, r10, 13
  738 + bne fm07
  739 + cmpi 0, r11, 11
  740 + bne fm07
  741 + cmpi 0, r13, 4
  742 + bne fm07
  743 + addi r3, 0, 3
  744 + bl fmfound
  745 +
  746 +fm07: cmpi 0, r10, 12
  747 + bne fm08
  748 + cmpi 0, r11, 8
  749 + bne fm08
  750 + cmpi 0, r13, 2
  751 + bne fm08
  752 + addi r3, 0, 4
  753 + bl fmfound
  754 +
  755 +fm08: cmpi 0, r10, 12
  756 + bne fm09
  757 + cmpi 0, r11, 8
  758 + bne fm09
  759 + cmpi 0, r13, 4
  760 + bne fm09
  761 + addi r3, 0, 4
  762 + bl fmfound
  763 +
  764 +fm09: cmpi 0, r10, 11
  765 + bne fm10
  766 + cmpi 0, r11, 8
  767 + bne fm10
  768 + cmpi 0, r13, 2
  769 + bne fm10
  770 + addi r3, 0, 5
  771 + bl fmfound
  772 +
  773 +fm10: cmpi 0, r10, 11
  774 + bne fm11
  775 + cmpi 0, r11, 8
  776 + bne fm11
  777 + cmpi 0, r13, 4
  778 + bne fm11
  779 + addi r3, 0, 5
  780 + bl fmfound
  781 +
  782 +fm11: cmpi 0, r10, 13
  783 + bne fm12
  784 + cmpi 0, r11, 8
  785 + bne fm12
  786 + cmpi 0, r13, 2
  787 + bne fm12
  788 + addi r3, 0, 6
  789 + bl fmfound
  790 +
  791 +fm12: cmpi 0, r10, 13
  792 + bne fm13
  793 + cmpi 0, r11, 8
  794 + bne fm13
  795 + cmpi 0, r13, 4
  796 + bne fm13
  797 + addi r3, 0, 6
  798 + bl fmfound
  799 +
  800 +fm13: cmpi 0, r10, 13
  801 + bne fm14
  802 + cmpi 0, r11, 9
  803 + bne fm14
  804 + cmpi 0, r13, 2
  805 + bne fm14
  806 + addi r3, 0, 7
  807 + bl fmfound
  808 +
  809 +fm14: cmpi 0, r10, 13
  810 + bne fm15
  811 + cmpi 0, r11, 10
  812 + bne fm15
  813 + cmpi 0, r13, 2
  814 + bne fm15
  815 + addi r3, 0, 7
  816 + bl fmfound
  817 +
  818 +fm15:
  819 + /* not found, error code to be issued on LEDs */
  820 + addi r7, 0, LED_SDRAM_CODE_2
  821 + addis r6, 0, 0x1000
  822 + ori r6, r6, 0x0001
  823 + stb r7,0(r6)
  824 + eieio
  825 +fmerr: bl fmerr
  826 +
  827 +fmfound:addi r6, 0, 1
  828 + subf r3, r6, r3
  829 +
  830 + mtlr r5 /* restore lr */
  831 + blr
  832 +
  833 +/*--------------------------------------------------------------------- */
  834 +/* Function: find_size_code */
  835 +/* Description: Determines size code to be used in configuring SDRAM controller */
  836 +/* dependent on density (r15 = byte 31 from SPD) */
  837 +/*--------------------------------------------------------------------- */
  838 +find_size_code:
  839 +
  840 + mflr r5
  841 +
  842 + addi r3, r15, 0 /* density */
  843 + addi r7, 0, 0
  844 +fs01: andi. r6, r3, 0x01
  845 + cmpi 0, r6, 1
  846 + beq fs04
  847 +
  848 + addi r7, r7, 1
  849 + cmpi 0, r7, 7
  850 + bge fs02
  851 + addi r9, 0, 1
  852 + srw r3, r3, r9
  853 + bl fs01
  854 +
  855 + /* not found, error code to be issued on LEDs */
  856 +fs02: addi r4, 0, LED_SDRAM_CODE_3
  857 + addis r8, 0, 0x1000
  858 + ori r8, r8, 0x0001
  859 + stb r4,0(r8)
  860 + eieio
  861 +fs03: bl fs03
  862 +
  863 +fs04: addi r3, r7, 0
  864 + cmpi 0, r3, 0
  865 + beq fs05
  866 + addi r6, 0, 1
  867 + subf r3, r6, r3
  868 +fs05:
  869 + mtlr r5 /* restore lr */
  870 + blr
  871 +
  872 +/*--------------------------------------------------------------------- */
  873 +/* Function: find_casl */
  874 +/* Description: Determines CAS latency */
  875 +/*--------------------------------------------------------------------- */
  876 +find_casl:
  877 +
  878 + mflr r5
  879 +
  880 + andi. r14, r14, 0x7f /* r14 holds supported CAS latencies */
  881 + addi r3, 0, 0xff /* preset determined CASL */
  882 + addi r4, 0, 6 /* Start at bit 6 of supported CAS latencies */
  883 + addi r2, 0, 0 /* Start finding highest CAS latency */
  884 +
  885 +fc01: srw r6, r14, r4 /* */
  886 + andi. r6, r6, 0x01 /* */
  887 + cmpi 0, r6, 1 /* Check bit for current latency */
  888 + bne fc06 /* If not supported, go to next */
  889 +
  890 + cmpi 0, r2, 2 /* Check if third-highest latency */
  891 + bge fc04 /* If so, go calculate with another format */
  892 +
  893 + cmpi 0, r2, 0 /* Check if highest latency */
  894 + bgt fc02 /* */
  895 + addi r7, r19, 0 /* SDRAM cycle time for highest CAS latenty */
  896 +
  897 + bl fc03
  898 +fc02:
  899 + addi r7, r20, 0 /* SDRAM cycle time for next-highest CAS latenty */
  900 +fc03:
  901 + addi r8, r7, 0
  902 + addi r9, 0, 4
  903 + srw r7, r7, r9
  904 + andi. r7, r7, 0x0f
  905 + mulli r7, r7, 100
  906 + andi. r8, r8, 0x0f
  907 + mulli r8, r8, 10
  908 + add r7, r7, r8
  909 + cmp 0, r7, r30
  910 + bgt fc05
  911 + addi r3, r2, 0
  912 + bl fc05
  913 +fc04:
  914 + addi r7, r21, 0 /* SDRAM cycle time for third-highest CAS latenty */
  915 + addi r8, r7, 0
  916 + addi r9, 0, 2
  917 + srw r7, r7, r9
  918 + andi. r7, r7, 0x3f
  919 + mulli r7, r7, 100
  920 + andi. r8, r8, 0x03
  921 + mulli r8, r8, 25
  922 + add r7, r7, r8
  923 +
  924 + cmp 0, r7, r30
  925 + bgt fc05
  926 + addi r3, r2, 0
  927 +
  928 +fc05: addi r2, r2, 1 /* next latency */
  929 + cmpi 0, r2, 3
  930 + bge fc07
  931 +fc06: addi r6, 0, 1
  932 + subf r4, r6, r4
  933 + cmpi 0, r4, 0
  934 + bne fc01
  935 +
  936 +fc07:
  937 +
  938 + mtlr r5 /* restore lr */
  939 + blr
  940 +#endif
  941 +
  942 +
  943 +/* Peripheral Bank 1 Access Parameters */
  944 +/* 0 BME = 1 ; burstmode enabled */
  945 +/* " 1:8" TWT=00110110 ;Transfer wait (details below) */
  946 +/* 1:5 FWT=00110 ; first wait = 6 cycles */
  947 +/* 6:8 BWT=110 ; burst wait = 6 cycles */
  948 +/* 9:11 000 ; reserved */
  949 +/* 12:13 CSN=00 ; chip select on timing = 0 */
  950 +/* 14:15 OEN=01 ; output enable */
  951 +/* 16:17 WBN=01 ; write byte enable on timing 1 cycle */
  952 +/* 18:19 WBF=01 ; write byte enable off timing 1 cycle */
  953 +/* 20:22 TH=010 ; transfer hold = 2 cycles */
  954 +/* 23 RE=0 ; ready enable = disabled */
  955 +/* 24 SOR=1 ; sample on ready = same PerClk */
  956 +/* 25 BEM=0 ; byte enable mode = only for write cycles */
  957 +/* 26 PEN=0 ; parity enable = disable */
  958 +/* 27:31 00000 ;reserved */
  959 +/* */
  960 +/* 1 + 00110 + 110 + 000 + 00 + 01 + 01 + 01 + 010 + 0 + 1 + 0 + 0 + 00000 = 0x9b015480 */
  961 +/* */
  962 +/* */
  963 +/* Code for BDI probe: */
  964 +/* */
  965 +/* WDCR 18 0x00000011 ;Select PB1AP */
  966 +/* WDCR 19 0x1b015480 ;PB1AP: Flash */
  967 +/* */
  968 +/* Peripheral Bank 0 Access Parameters */
  969 +/* 0:11 BAS=0x200 ; base address select = 0x200 * 0x100000 (1MB) = */
  970 +/* 12:14 BS=100 ; bank size = 16MB (100) / 32MB (101) */
  971 +/* 15:16 BU=11 ; bank usage = read/write */
  972 +/* 17:18 BW=00 ; bus width = 8-bit */
  973 +/* 19:31 ; reserved */
  974 +/* */
  975 +/* 0x200 + 100 + 11 + 00 + 0 0000 0000 0000 = 0x20098000 */
  976 +/* WDCR 18 0x00000001 ;Select PB1CR */
  977 +/* WDCR 19 0x20098000 ;PB1CR: 1MB at 0x00100000, r/w, 8bit */
  978 +
  979 +/* For CPLD */
  980 +/* 0 + 00000 + 010 + 000 + 00 + 01 + 00 + 00 + 000 + 0 + 0 + 1 + 0 + 00000 */
  981 +/* WDCR_EBC(pb5ap, 0x01010040) */
  982 +/*jsa recommendation: WDCR_EBC(pb5ap, 0x00010040) */
  983 +/* WDCR_EBC(pb5cr, 0X10018000) */
  984 +/* Access parms */
  985 +/* 100 3 8 0 0 0 */
  986 +/* 0x100 + 001 + 11 + 00 + 0 0000 0000 0000 = 0x10038000 */
  987 +/* Address : 0x10000000 */
  988 +/* Size: 2 MB */
  989 +/* Usage: read/write */
  990 +/* Width: 32 bit */
  991 +
  992 +/* For Genie onboard fpga 32 bit interface */
  993 +/* 0 1 0 1 0 0 0 0 */
  994 +/* 0 + 00000 + 010 + 000 + 00 + 01 + 00 + 00 + 000 + 0 + 0 + 0 + 0 + 00000 */
  995 +/* 0x01010000 */
  996 +/* Access parms */
  997 +/* 102 1 c 0 0 0 */
  998 +/* 0x102 + 000 + 11 + 10 + 0 0000 0000 0000 = 0x1021c000 */
  999 +/* Address : 0x10200000 */
  1000 +/* Size: 2 MB */
  1001 +/* Usage: read/write */
  1002 +/* Width: 32 bit */
  1003 +
  1004 +/* Walnut fpga pb7ap */
  1005 +/* 0 1 8 1 5 2 8 0 */
  1006 +/* 0 + 00000 + 011 + 000 + 00 + 01 + 01 + 01 + 001 + 0 + 1 + 0 + 0 + 00000 */
  1007 +/* Walnut fpga pb7cr */
  1008 +/* 0xF0318000 */
  1009 +/* */
board/exbitgen/u-boot.lds
Diff comments   View file @ a807645
  1 +/*
  2 + * (C) Copyright 2000
  3 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +OUTPUT_ARCH(powerpc)
  25 +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
  26 +/* Do we need any of these for elf?
  27 + __DYNAMIC = 0; */
  28 +SECTIONS
  29 +{
  30 + .resetvec 0xFFFFFFFC :
  31 + {
  32 + *(.resetvec)
  33 + } = 0xffff
  34 +
  35 + /* Read-only sections, merged into text segment: */
  36 + . = + SIZEOF_HEADERS;
  37 + .interp : { *(.interp) }
  38 + .hash : { *(.hash) }
  39 + .dynsym : { *(.dynsym) }
  40 + .dynstr : { *(.dynstr) }
  41 + .rel.text : { *(.rel.text) }
  42 + .rela.text : { *(.rela.text) }
  43 + .rel.data : { *(.rel.data) }
  44 + .rela.data : { *(.rela.data) }
  45 + .rel.rodata : { *(.rel.rodata) }
  46 + .rela.rodata : { *(.rela.rodata) }
  47 + .rel.got : { *(.rel.got) }
  48 + .rela.got : { *(.rela.got) }
  49 + .rel.ctors : { *(.rel.ctors) }
  50 + .rela.ctors : { *(.rela.ctors) }
  51 + .rel.dtors : { *(.rel.dtors) }
  52 + .rela.dtors : { *(.rela.dtors) }
  53 + .rel.bss : { *(.rel.bss) }
  54 + .rela.bss : { *(.rela.bss) }
  55 + .rel.plt : { *(.rel.plt) }
  56 + .rela.plt : { *(.rela.plt) }
  57 + .init : { *(.init) }
  58 + .plt : { *(.plt) }
  59 + .text :
  60 + {
  61 + /* WARNING - the following is hand-optimized to fit within */
  62 + /* the sector layout of our flash chips! XXX FIXME XXX */
  63 +
  64 + cpu/ppc4xx/start.o (.text)
  65 + board/exbitgen/init.o (.text)
  66 + cpu/ppc4xx/kgdb.o (.text)
  67 + cpu/ppc4xx/traps.o (.text)
  68 + cpu/ppc4xx/interrupts.o (.text)
  69 + cpu/ppc4xx/serial.o (.text)
  70 + cpu/ppc4xx/cpu_init.o (.text)
  71 + cpu/ppc4xx/speed.o (.text)
  72 + common/dlmalloc.o (.text)
  73 + lib_generic/crc32.o (.text)
  74 + lib_ppc/extable.o (.text)
  75 + lib_generic/zlib.o (.text)
  76 +
  77 +/* . = env_offset;*/
  78 + common/environment.o(.text)
  79 +
  80 + *(.text)
  81 + *(.fixup)
  82 + *(.got1)
  83 + }
  84 + _etext = .;
  85 + PROVIDE (etext = .);
  86 + .rodata :
  87 + {
  88 + *(.rodata)
  89 + *(.rodata1)
  90 + }
  91 + .fini : { *(.fini) } =0
  92 + .ctors : { *(.ctors) }
  93 + .dtors : { *(.dtors) }
  94 +
  95 + /* Read-write section, merged into data segment: */
  96 + . = (. + 0x00FF) & 0xFFFFFF00;
  97 + _erotext = .;
  98 + PROVIDE (erotext = .);
  99 + .reloc :
  100 + {
  101 + *(.got)
  102 + _GOT2_TABLE_ = .;
  103 + *(.got2)
  104 + _FIXUP_TABLE_ = .;
  105 + *(.fixup)
  106 + }
  107 + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
  108 + __fixup_entries = (. - _FIXUP_TABLE_)>>2;
  109 +
  110 + .data :
  111 + {
  112 + *(.data)
  113 + *(.data1)
  114 + *(.sdata)
  115 + *(.sdata2)
  116 + *(.dynamic)
  117 + CONSTRUCTORS
  118 + }
  119 + _edata = .;
  120 + PROVIDE (edata = .);
  121 +
  122 + __start___ex_table = .;
  123 + __ex_table : { *(__ex_table) }
  124 + __stop___ex_table = .;
  125 +
  126 + . = ALIGN(256);
  127 + __init_begin = .;
  128 + .text.init : { *(.text.init) }
  129 + .data.init : { *(.data.init) }
  130 + . = ALIGN(256);
  131 + __init_end = .;
  132 +
  133 + __bss_start = .;
  134 + .bss :
  135 + {
  136 + *(.sbss) *(.scommon)
  137 + *(.dynbss)
  138 + . = ALIGN(4);
  139 + *(.bss)
  140 + *(COMMON)
  141 + }
  142 + _end = . ;
  143 + PROVIDE (end = .);
  144 +}
include/configs/EXBITGEN.h
Diff comments   View file @ a807645
  1 +/*
  2 + * (C) Copyright 2000
  3 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +/*
  25 + * board/config.h - configuration options, board specific
  26 + */
  27 +
  28 +#ifndef __CONFIG_H
  29 +#define __CONFIG_H
  30 +
  31 +/*
  32 + * High Level Configuration Options
  33 + * (easy to change)
  34 + */
  35 +
  36 +#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
  37 +#define CONFIG_4xx 1 /* ...member of PPC4xx family */
  38 +#define CONFIG_EXBITGEN 1 /* on a Exbit Generic board */
  39 +
  40 +#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
  41 +
  42 +#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
  43 +
  44 +/* I2C configuration */
  45 +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
  46 +#define CFG_I2C_SPEED 40000 /* I2C speed */
  47 +#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
  48 +
  49 +/* environment is in EEPROM */
  50 +#define CFG_ENV_IS_IN_EEPROM 1
  51 +#undef CFG_ENV_IS_IN_FLASH
  52 +#undef CFG_ENV_IS_IN_NVRAM
  53 +
  54 +#ifdef CFG_ENV_IS_IN_EEPROM
  55 +#define CFG_I2C_EEPROM_ADDR 0x56 /* 1010110 */
  56 +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* 8-bit internal addressing */
  57 +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 1 /* ... and 1 bit in I2C address */
  58 +#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* 4 bytes per page */
  59 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 40 /* write takes up to 40 msec */
  60 +#define CFG_ENV_OFFSET 4 /* Offset of Environment Sector */
  61 +#define CFG_ENV_SIZE 350 /* that is 350 bytes only! */
  62 +#endif
  63 +
  64 +#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
  65 +/* Explanation:
  66 + autbooting is altogether disabled and cannot be
  67 + enabled if CONFIG_BOOTDELAY is negative.
  68 + If you want shorter bootdelay, then
  69 + - "setenv bootdelay <delay>" to the proper value
  70 +*/
  71 +
  72 +#define CONFIG_BOOTCOMMAND "bootm 20400000 20800000"
  73 +
  74 +#define CONFIG_BOOTARGS "root=/dev/ram " \
  75 + "ramdisk_size=32768 " \
  76 + "console=ttyS0,115200 " \
  77 + "ram=128M debug"
  78 +
  79 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  80 +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  81 +
  82 +#define CONFIG_MII 1 /* MII PHY management */
  83 +#define CONFIG_PHY_ADDR 0 /* PHY address */
  84 +
  85 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL)
  86 +
  87 +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  88 +#include <cmd_confdefs.h>
  89 +
  90 +#undef CONFIG_WATCHDOG /* watchdog disabled */
  91 +
  92 +/*
  93 + * Miscellaneous configurable options
  94 + */
  95 +#define CFG_LONGHELP /* undef to save memory */
  96 +#define CFG_PROMPT "=> " /* Monitor Command Prompt */
  97 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  98 +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  99 +#else
  100 +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  101 +#endif
  102 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  103 +#define CFG_MAXARGS 16 /* max number of command args */
  104 +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  105 +
  106 +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
  107 +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  108 +
  109 +/* UART configuration */
  110 +#define CFG_BASE_BAUD 691200
  111 +
  112 +/* Default baud rate */
  113 +#define CONFIG_BAUDRATE 115200
  114 +
  115 +/* The following table includes the supported baudrates */
  116 +#define CFG_BAUDRATE_TABLE \
  117 + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
  118 + 57600, 115200, 230400, 460800, 921600 }
  119 +
  120 +#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */
  121 +
  122 +#define CFG_LOAD_ADDR 0x100000 /* default load address */
  123 +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
  124 +
  125 +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  126 +
  127 +/*-----------------------------------------------------------------------
  128 + * PCI stuff
  129 + *-----------------------------------------------------------------------
  130 + */
  131 +#undef CONFIG_PCI /* no pci support */
  132 +
  133 +/*-----------------------------------------------------------------------
  134 + * External peripheral base address
  135 + *-----------------------------------------------------------------------
  136 + */
  137 +#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
  138 +#undef CONFIG_IDE_LED /* no led for ide supported */
  139 +#undef CONFIG_IDE_RESET /* no reset for ide supported */
  140 +
  141 +#define CFG_KEY_REG_BASE_ADDR 0xF0100000
  142 +#define CFG_IR_REG_BASE_ADDR 0xF0200000
  143 +#define CFG_FPGA_REG_BASE_ADDR 0xF0300000
  144 +
  145 +/*-----------------------------------------------------------------------
  146 + * Start addresses for the final memory configuration
  147 + * (Set up by the startup code)
  148 + * Please note that CFG_SDRAM_BASE _must_ start at 0
  149 + */
  150 +#define CFG_SDRAM_BASE 0x00000000
  151 +#define CFG_FLASH0_BASE 0xFFF80000
  152 +#define CFG_FLASH0_SIZE 0x00080000
  153 +#define CFG_FLASH1_BASE 0x20000000
  154 +#define CFG_FLASH1_SIZE 0x02000000
  155 +#define CFG_FLASH_BASE CFG_FLASH0_BASE
  156 +#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
  157 +#define CFG_MONITOR_BASE TEXT_BASE
  158 +#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
  159 +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
  160 +
  161 +#if CFG_MONITOR_BASE < CFG_FLASH0_BASE
  162 +#define CFG_RAMSTART
  163 +#endif
  164 +
  165 +/*
  166 + * For booting Linux, the board info and command line data
  167 + * have to be in the first 8 MB of memory, since this is
  168 + * the maximum mapped by the Linux kernel during initialization.
  169 + */
  170 +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  171 +/*-----------------------------------------------------------------------
  172 + * FLASH organization
  173 + */
  174 +#define CFG_MAX_FLASH_BANKS 5 /* max number of memory banks */
  175 +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
  176 +
  177 +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  178 +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  179 +
  180 +#ifdef CFG_ENV_IS_IN_FLASH
  181 +#define CFG_ENV_OFFSET 0x00060000 /* Offset of Environment Sector */
  182 +#define CFG_ENV_SIZE 0x00010000 /* Total Size of Environment Sector */
  183 +#define CFG_ENV_SECT_SIZE 0x00010000 /* see README - env sector total size */
  184 +#endif
  185 +
  186 +/* On Chip Memory location/size */
  187 +#define CFG_OCM_DATA_ADDR 0xF8000000
  188 +#define CFG_OCM_DATA_SIZE 0x1000
  189 +
  190 +/* Global info and initial stack */
  191 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of on-chip SRAM */
  192 +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
  193 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  194 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  195 +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  196 +
  197 +/* Cache configuration */
  198 +#define CFG_DCACHE_SIZE 8192
  199 +#define CFG_CACHELINE_SIZE 32
  200 +
  201 +/*
  202 + * Internal Definitions
  203 + *
  204 + * Boot Flags
  205 + */
  206 +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  207 +#define BOOTFLAG_WARM 0x02 /* Software reboot */
  208 +
  209 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  210 +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  211 +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  212 +#endif
  213 +#endif /* __CONFIG_H */
... ... @@ -139,7 +139,8 @@
139 139 #define AMD_ID_LV400T 0x22B922B9 /* 29LV400T ID ( 4 M, top boot sector) */
140 140 #define AMD_ID_LV400B 0x22BA22BA /* 29LV400B ID ( 4 M, bottom boot sect) */
141 141  
142   -#define AMD_ID_LV033C 0xA3 /* 29LV033C ID ( 4M x 8 ) */
  142 +#define AMD_ID_LV033C 0xA3 /* 29LV033C ID ( 4 M x 8) */
  143 +#define AMD_ID_LV065D 0x93 /* 29LV065D ID ( 8 M x 8) */
143 144  
144 145 #define AMD_ID_LV800T 0x22DA22DA /* 29LV800T ID ( 8 M, top boot sector) */
145 146 #define AMD_ID_LV800B 0x225B225B /* 29LV800B ID ( 8 M, bottom boot sect) */
... ... @@ -174,6 +175,7 @@
174 175 #define SST_ID_xF400A 0x27802780 /* 39xF400A ID ( 4M = 256K x 16 ) */
175 176 #define SST_ID_xF800A 0x27812781 /* 39xF800A ID ( 8M = 512K x 16 ) */
176 177 #define SST_ID_xF160A 0x27822782 /* 39xF800A ID (16M = 1M x 16 ) */
  178 +#define SST_ID_xF040 0xBFD7BFD7 /* 39xF040 ID (512KB = 4Mbit x 8) */
177 179  
178 180 #define STM_ID_F040B 0xE2 /* M29F040B ID ( 4M = 512K x 8 ) */
179 181 /* 8 64K x 8 uniform sectors */
... ... @@ -255,6 +257,9 @@
255 257 #define FLASH_AMDL324T 0x0014 /* AMD AM29DL324 */
256 258 #define FLASH_AMDL324B 0x0015
257 259  
  260 +#define FLASH_AMDLV033C 0x0018
  261 +#define FLASH_AMDLV065D 0x001A
  262 +
258 263 #define FLASH_AMDL640 0x0016 /* AMD AM29DL640D */
259 264 #define FLASH_AMD016 0x0018 /* AMD AM29F016D */
260 265  
... ... @@ -262,6 +267,7 @@
262 267 #define FLASH_SST400A 0x0042 /* SST 39xF400A ID ( 4M = 256K x 16 ) */
263 268 #define FLASH_SST800A 0x0044 /* SST 39xF800A ID ( 8M = 512K x 16 ) */
264 269 #define FLASH_SST160A 0x0046 /* SST 39xF160A ID ( 16M = 1M x 16 ) */
  270 +#define FLASH_SST040 0x000E /* SST 39xF040 ID (512KB = 4Mbit x 8 ) */
265 271  
266 272 #define FLASH_STM800AB 0x0051 /* STM M29WF800AB ( 8M = 512K x 16 ) */
267 273 #define FLASH_STMW320DT 0x0052 /* STM M29W320DT (32 M, top boot sector) */