Eric Lee / smarc-uboot | Embedian Git Server

Commit a80a661989d35620465da85d9d9f8179e9c9e843

Authored by Nobuhiro Iwamatsu 2012-05-16 09:23:21 +0800

Exists in master and in 56 other branches

sh: Set CONFIG_SH_ETHER_PHY_MODE and CONFIG_SH_ETHER_SH7734_MII to boards with sh_eth

The board with sh_eth needs to set CONFIG_SH_ETHER_PHY_MODE.
And SH7734 needs to set value of CONFIG_SH_ETHER_SH7734_MII.

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Showing 5 changed files with 6 additions and 0 deletions Inline Diff

include/configs/ecovec.h
include/configs/espt.h
include/configs/r0p7734.h
include/configs/sh7757lcr.h
include/configs/sh7763rdp.h

include/configs/ecovec.h

Diff comments View file @ a80a661

 /*
  * Configuation settings for the Renesas Solutions ECOVEC board
  *
  * Copyright (C) 2009 - 2011 Renesas Solutions Corp.
  * Copyright (C) 2009 Kuninori Morimoto <morimoto.kuninori@renesas.com>
  * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #ifndef __ECOVEC_H
 #define __ECOVEC_H
 /*
  *  Address      Interface        BusWidth
  *-----------------------------------------
  *  0x0000_0000  U-Boot           16bit
  *  0x0004_0000  Linux romImage   16bit
  *  0x0014_0000  MTD for Linux    16bit
  *  0x0400_0000  Internal I/O     16/32bit
  *  0x0800_0000  DRAM             32bit
  *  0x1800_0000  MFI              16bit
  */
 #undef DEBUG
 #define CONFIG_SH		1
 #define CONFIG_SH4		1
 #define CONFIG_SH4A		1
 #define CONFIG_CPU_SH7724	1
 #define CONFIG_BOARD_LATE_INIT		1
 #define CONFIG_ECOVEC		1
 #define CONFIG_ECOVEC_ROMIMAGE_ADDR 0xA0040000
 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_USB
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_SAVEENV
 #define CONFIG_USB_STORAGE
 #define CONFIG_DOS_PARTITION
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		"console=ttySC0,115200"
 #define CONFIG_VERSION_VARIABLE
 #undef  CONFIG_SHOW_BOOT_PROGRESS
 /* I2C */
 #define CONFIG_CMD_I2C
 #define CONFIG_SH_I2C 1
 #define CONFIG_HARD_I2C		1
 #define CONFIG_I2C_MULTI_BUS	1
 #define CONFIG_SYS_MAX_I2C_BUS	2
 #define CONFIG_SYS_I2C_MODULE	1
 #define CONFIG_SYS_I2C_SPEED	100000 /* 100 kHz */
 #define CONFIG_SYS_I2C_SLAVE	0x7F
 #define CONFIG_SH_I2C_DATA_HIGH	4
 #define CONFIG_SH_I2C_DATA_LOW 	5
 #define CONFIG_SH_I2C_CLOCK  	41666666
 #define CONFIG_SH_I2C_BASE0		0xA4470000
 #define CONFIG_SH_I2C_BASE1		0xA4750000
 /* Ether */
 #define CONFIG_SH_ETHER 1
 #define CONFIG_SH_ETHER_USE_PORT (0)
 #define CONFIG_SH_ETHER_PHY_ADDR (0x1f)
 #define CONFIG_PHY_SMSC 1
 #define CONFIG_PHYLIB
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
 /* USB / R8A66597 */
 #define CONFIG_USB_R8A66597_HCD
 #define CONFIG_R8A66597_BASE_ADDR   0xA4D80000
 #define CONFIG_R8A66597_XTAL        0x0000  /* 12MHz */
 #define CONFIG_R8A66597_LDRV        0x8000  /* 3.3V */
 #define CONFIG_R8A66597_ENDIAN      0x0000  /* little */
 #define CONFIG_SUPERH_ON_CHIP_R8A66597
 /* undef to save memory	*/
 #define CONFIG_SYS_LONGHELP
 /* Monitor Command Prompt */
 #define CONFIG_SYS_PROMPT		"=> "
 /* Buffer size for input from the Console */
 #define CONFIG_SYS_CBSIZE		256
 /* Buffer size for Console output */
 #define CONFIG_SYS_PBSIZE		256
 /* max args accepted for monitor commands */
 #define CONFIG_SYS_MAXARGS		16
 /* Buffer size for Boot Arguments passed to kernel */
 #define CONFIG_SYS_BARGSIZE	512
 /* List of legal baudrate settings for this board */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
 /* SCIF */
 #define CONFIG_SCIF_CONSOLE	1
 #define CONFIG_SCIF		1
 #define CONFIG_CONS_SCIF0	1
 /* Suppress display of console information at boot */
 #undef  CONFIG_SYS_CONSOLE_INFO_QUIET
 #undef  CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 #undef  CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 /* SDRAM */
 #define CONFIG_SYS_SDRAM_BASE	(0x88000000)
 #define CONFIG_SYS_SDRAM_SIZE	(256 * 1024 * 1024)
 #define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
 #define CONFIG_SYS_MEMTEST_END	 (CONFIG_SYS_MEMTEST_START + 200 * 1024 * 1024)
 /* Enable alternate, more extensive, memory test */
 #undef  CONFIG_SYS_ALT_MEMTEST
 /* Scratch address used by the alternate memory test */
 #undef  CONFIG_SYS_MEMTEST_SCRATCH
 /* Enable temporary baudrate change while serial download */
 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE
 /* FLASH */
 #define CONFIG_FLASH_CFI_DRIVER 1
 #define CONFIG_SYS_FLASH_CFI
 #undef  CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BASE	(0xA0000000)
 #define CONFIG_SYS_MAX_FLASH_SECT	512
 /* if you use all NOR Flash , you change dip-switch. Please see Manual. */
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 /* Timeout for Flash erase operations (in ms) */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
 /* Timeout for Flash write operations (in ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
 /* Timeout for Flash set sector lock bit operations (in ms) */
 #define CONFIG_SYS_FLASH_LOCK_TOUT	(3 * 1000)
 /* Timeout for Flash clear lock bit operations (in ms) */
 #define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
 /*
  * Use hardware flash sectors protection instead
  * of U-Boot software protection
  */
 #undef  CONFIG_SYS_FLASH_PROTECTION
 #undef  CONFIG_SYS_DIRECT_FLASH_TFTP
 /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
 #define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
 /* Monitor size */
 #define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
 /* Size of DRAM reserved for malloc() use */
 #define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
 /* size in bytes reserved for initial data */
 #define CONFIG_SYS_GBL_DATA_SIZE	(256)
 #define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)
 /* ENV setting */
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_OVERWRITE	1
 #define CONFIG_ENV_SECT_SIZE	(128 * 1024)
 #define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
 /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
 #define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ 41666666
 #define CONFIG_SYS_TMU_CLK_DIV      4
 #define CONFIG_SYS_HZ       1000
 #endif	/* __ECOVEC_H */

include/configs/espt.h

Diff comments View file @ a80a661

 /*
  * Configuation settings for the ESPT-GIGA board
  *
  * Copyright (C) 2008 Renesas Solutions Corp.
  * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #ifndef __ESPT_H
 #define __ESPT_H
 #define CONFIG_SH		1
 #define CONFIG_SH4		1
 #define CONFIG_CPU_SH7763	1
 #define CONFIG_ESPT	1
 #define __LITTLE_ENDIAN		1
 /*
  * Command line configuration.
  */
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_SAVEENV
 #define CONFIG_BOOTDELAY        -1
 #define CONFIG_BOOTARGS         "console=ttySC0,115200 root=1f01"
 #define CONFIG_ENV_OVERWRITE    1
 #define CONFIG_VERSION_VARIABLE
 #undef  CONFIG_SHOW_BOOT_PROGRESS
 /* SCIF */
 #define CONFIG_SCIF_CONSOLE		1
 #define CONFIG_BAUDRATE         115200
 #define CONFIG_CONS_SCIF0		1
 #define CONFIG_SYS_TEXT_BASE	0x8FFC0000
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 #define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		256	/* Buffer size for input from the Console */
 #define CONFIG_SYS_PBSIZE		256	/* Buffer size for Console output */
 #define CONFIG_SYS_MAXARGS		16	/* max args accepted for monitor commands */
 #define CONFIG_SYS_BARGSIZE	512	/* Buffer size for Boot Arguments
 								passed to kernel */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate
 												settings for this board */
 /* SDRAM */
 #define CONFIG_SYS_SDRAM_BASE		(0x8C000000)
 #define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)
 #define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE)
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
 /* Flash(NOR) S29JL064H */
 #define CONFIG_SYS_FLASH_BASE		(0xA0000000)
 #define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
 #define CONFIG_SYS_MAX_FLASH_BANKS (1)
 #define CONFIG_SYS_MAX_FLASH_SECT  (150)
 /* U-boot setting */
 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
 #define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
 #define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
 /* Size of DRAM reserved for malloc() use */
 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
 #define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
 #undef  CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
 /* Timeout for Flash erase operations (in ms) */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
 /* Timeout for Flash write operations (in ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
 /* Timeout for Flash set sector lock bit operations (in ms) */
 #define CONFIG_SYS_FLASH_LOCK_TOUT		(3 * 1000)
 /* Timeout for Flash clear lock bit operations (in ms) */
 #define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
 /* Use hardware flash sectors protection instead of U-Boot software protection */
 #undef  CONFIG_SYS_FLASH_PROTECTION
 #undef  CONFIG_SYS_DIRECT_FLASH_TFTP
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	(128 * 1024)
 #define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
 /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
 #define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
 /* Clock */
 #define CONFIG_SYS_CLK_FREQ	66666666
 #define CONFIG_SYS_TMU_CLK_DIV      4
 #define CONFIG_SYS_HZ       1000
 /* Ether */
 #define CONFIG_SH_ETHER 1
 #define CONFIG_SH_ETHER_USE_PORT (1)
 #define CONFIG_SH_ETHER_PHY_ADDR (0x00)
 #define CONFIG_PHYLIB
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
 #endif /* __SH7763RDP_H */

include/configs/r0p7734.h

Diff comments View file @ a80a661

 /*
  * Configuation settings for the Renesas Solutions r0p7734 board
  *
  * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #ifndef __R0P7734_H
 #define __R0P7734_H
 #undef DEBUG
 #define CONFIG_SH		1
 #define CONFIG_SH4		1
 #define CONFIG_SH4A		1
 #define CONFIG_CPU_SH7734	1
 #define CONFIG_R0P7734		1
 #define CONFIG_400MHZ_MODE	1
 /* #define CONFIG_533MHZ_MODE	1 */
 #define CONFIG_BOARD_LATE_INIT
 #define CONFIG_SYS_TEXT_BASE 0x8FFC0000
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_SAVEENV
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		"console=ttySC3,115200"
 #define CONFIG_VERSION_VARIABLE
 #undef  CONFIG_SHOW_BOOT_PROGRESS
 /* Ether */
 #define CONFIG_SH_ETHER 1
 #define CONFIG_SH_ETHER_USE_PORT (0)
 #define CONFIG_SH_ETHER_PHY_ADDR (0x0)
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_SMSC 1
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
+#define CONFIG_SH_ETHER_SH7734_MII (0x00) /* MII */
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
 #ifndef CONFIG_SH_ETHER
 # define CONFIG_SMC911X
 # define CONFIG_SMC911X_16_BIT
 # define CONFIG_SMC911X_BASE (0x84000000)
 #endif
 /* I2C */
 #define CONFIG_CMD_I2C
 #define CONFIG_SH_SH7734_I2C	1
 #define CONFIG_HARD_I2C			1
 #define CONFIG_I2C_MULTI_BUS	1
 #define CONFIG_SYS_MAX_I2C_BUS	2
 #define CONFIG_SYS_I2C_MODULE	0
 #define CONFIG_SYS_I2C_SPEED	100000 /* 100 kHz */
 #define CONFIG_SYS_I2C_SLAVE	0x50
 #define CONFIG_SH_I2C_DATA_HIGH	4
 #define CONFIG_SH_I2C_DATA_LOW	5
 #define CONFIG_SH_I2C_CLOCK		500000000
 #define CONFIG_SH_I2C_BASE0		0xFFC70000
 #define CONFIG_SH_I2C_BASE1		0xFFC7100
 /* undef to save memory	*/
 #define CONFIG_SYS_LONGHELP
 /* Monitor Command Prompt */
 #define CONFIG_SYS_PROMPT		"=> "
 /* Buffer size for input from the Console */
 #define CONFIG_SYS_CBSIZE		256
 /* Buffer size for Console output */
 #define CONFIG_SYS_PBSIZE		256
 /* max args accepted for monitor commands */
 #define CONFIG_SYS_MAXARGS		16
 /* Buffer size for Boot Arguments passed to kernel */
 #define CONFIG_SYS_BARGSIZE	512
 /* List of legal baudrate settings for this board */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
 /* SCIF */
 #define CONFIG_SCIF_CONSOLE	1
 #define CONFIG_SCIF			1
 #define CONFIG_CONS_SCIF3	1
 /* Suppress display of console information at boot */
 #undef  CONFIG_SYS_CONSOLE_INFO_QUIET
 #undef  CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 #undef  CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 /* SDRAM */
 #define CONFIG_SYS_SDRAM_BASE	(0x88000000)
 #define CONFIG_SYS_SDRAM_SIZE	(128 * 1024 * 1024)
 #define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
 #define CONFIG_SYS_MEMTEST_END	 (CONFIG_SYS_MEMTEST_START + 100 * 1024 * 1024)
 /* Enable alternate, more extensive, memory test */
 #undef  CONFIG_SYS_ALT_MEMTEST
 /* Scratch address used by the alternate memory test */
 #undef  CONFIG_SYS_MEMTEST_SCRATCH
 /* Enable temporary baudrate change while serial download */
 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE
 /* FLASH */
 #define CONFIG_FLASH_CFI_DRIVER 1
 #define CONFIG_SYS_FLASH_CFI
 #undef  CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BASE	(0xA0000000)
 #define CONFIG_SYS_MAX_FLASH_SECT	512
 /* if you use all NOR Flash , you change dip-switch. Please see Manual. */
 #define CONFIG_SYS_MAX_FLASH_BANKS	1
 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 /* Timeout for Flash erase operations (in ms) */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
 /* Timeout for Flash write operations (in ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
 /* Timeout for Flash set sector lock bit operations (in ms) */
 #define CONFIG_SYS_FLASH_LOCK_TOUT	(3 * 1000)
 /* Timeout for Flash clear lock bit operations (in ms) */
 #define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
 /*
  * Use hardware flash sectors protection instead
  * of U-Boot software protection
  */
 #undef  CONFIG_SYS_FLASH_PROTECTION
 #undef  CONFIG_SYS_DIRECT_FLASH_TFTP
 /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
 #define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
 /* Monitor size */
 #define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
 /* Size of DRAM reserved for malloc() use */
 #define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
 /* size in bytes reserved for initial data */
 #define CONFIG_SYS_GBL_DATA_SIZE	(256)
 #define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)
 /* ENV setting */
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_OVERWRITE	1
 #define CONFIG_ENV_SECT_SIZE	(128 * 1024)
 #define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
 /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
 #define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
 /* Board Clock */
 #if defined(CONFIG_400MHZ_MODE)
 #define CONFIG_SYS_CLK_FREQ 50000000
 #else
 #define CONFIG_SYS_CLK_FREQ 44444444
 #endif
 #define CONFIG_SYS_TMU_CLK_DIV      4
 #define CONFIG_SYS_HZ       1000
 #endif	/* __R0P7734_H */

include/configs/sh7757lcr.h

Diff comments View file @ a80a661

 /*
  * Configuation settings for the sh7757lcr board
  *
  * Copyright (C) 2011 Renesas Solutions Corp.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #ifndef __SH7757LCR_H
 #define __SH7757LCR_H
 #undef DEBUG
 #define CONFIG_SH		1
 #define CONFIG_SH4A		1
 #define CONFIG_SH_32BIT		1
 #define CONFIG_CPU_SH7757	1
 #define CONFIG_SH7757LCR	1
 #define CONFIG_SH7757LCR_DDR_ECC	1
 #define CONFIG_SYS_TEXT_BASE	0x8ef80000
 #define CONFIG_SYS_LDSCRIPT	"board/renesas/sh7757lcr/u-boot.lds"
 #define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_SF
 #define CONFIG_CMD_RUN
 #define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_MD5SUM
 #define CONFIG_MD5
 #define CONFIG_CMD_LOADS
 #define CONFIG_CMD_MMC
 #define CONFIG_CMD_EXT2
 #define CONFIG_DOS_PARTITION
 #define CONFIG_MAC_PARTITION
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTARGS		"console=ttySC2,115200 root=/dev/nfs ip=dhcp"
 #define CONFIG_VERSION_VARIABLE
 #undef	CONFIG_SHOW_BOOT_PROGRESS
 /* MEMORY */
 #define SH7757LCR_SDRAM_BASE		(0x80000000)
 #define SH7757LCR_SDRAM_SIZE		(240 * 1024 * 1024)
 #define SH7757LCR_SDRAM_ECC_SETTING	0x0f000000	/* 240MByte */
 #define SH7757LCR_SDRAM_DVC_SIZE	(16 * 1024 * 1024)
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_SYS_PROMPT		"=> "
 #define CONFIG_SYS_CBSIZE		256
 #define CONFIG_SYS_PBSIZE		256
 #define CONFIG_SYS_MAXARGS		16
 #define CONFIG_SYS_BARGSIZE		512
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
 /* SCIF */
 #define CONFIG_SCIF_CONSOLE	1
 #define CONFIG_CONS_SCIF2	1
 #undef	CONFIG_SYS_CONSOLE_INFO_QUIET
 #undef	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 #undef	CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 #define CONFIG_SYS_MEMTEST_START	(SH7757LCR_SDRAM_BASE)
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
 					 224 * 1024 * 1024)
 #undef	CONFIG_SYS_ALT_MEMTEST
 #undef	CONFIG_SYS_MEMTEST_SCRATCH
 #undef	CONFIG_SYS_LOADS_BAUD_CHANGE
 #define CONFIG_SYS_SDRAM_BASE		(SH7757LCR_SDRAM_BASE)
 #define CONFIG_SYS_SDRAM_SIZE		(SH7757LCR_SDRAM_SIZE)
 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + \
 					 (128 + 16) * 1024 * 1024)
 #define CONFIG_SYS_MONITOR_BASE		0x00000000
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
 #define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
 /* FLASH */
 #define CONFIG_SYS_NO_FLASH
 /* Ether */
 #define CONFIG_SH_ETHER			1
 #define CONFIG_SH_ETHER_USE_PORT	0
 #define CONFIG_SH_ETHER_PHY_ADDR	1
 #define CONFIG_SH_ETHER_CACHE_WRITEBACK	1
 #define CONFIG_PHYLIB
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
 #define SH7757LCR_ETHERNET_MAC_BASE_SPI	0x000b0000
 #define SH7757LCR_SPI_SECTOR_SIZE	(64 * 1024)
 #define SH7757LCR_ETHERNET_MAC_BASE	SH7757LCR_ETHERNET_MAC_BASE_SPI
 #define SH7757LCR_ETHERNET_MAC_SIZE	17
 #define SH7757LCR_ETHERNET_NUM_CH	2
 #define CONFIG_BOARD_LATE_INIT
 /* Gigabit Ether */
 #define SH7757LCR_GIGA_ETHERNET_NUM_CH	2
 /* SPI */
 #define CONFIG_SH_SPI			1
 #define CONFIG_SH_SPI_BASE		0xfe002000
 #define CONFIG_SPI_FLASH
 #define CONFIG_SPI_FLASH_STMICRO	1
 /* MMCIF */
 #define CONFIG_MMC			1
 #define CONFIG_GENERIC_MMC		1
 #define CONFIG_SH_MMCIF			1
 #define CONFIG_SH_MMCIF_ADDR		0xffcb0000
 #define CONFIG_SH_MMCIF_CLK		48000000
 /* SH7757 board */
 #define SH7757LCR_SDRAM_PHYS_TOP	0x40000000
 #define SH7757LCR_GRA_OFFSET		0x1f000000
 #define SH7757LCR_PCIEBRG_ADDR_B0	0x000a0000
 #define SH7757LCR_PCIEBRG_SIZE_B0	(64 * 1024)
 #define SH7757LCR_PCIEBRG_ADDR		0x00090000
 #define SH7757LCR_PCIEBRG_SIZE		(96 * 1024)
 /* ENV setting */
 #define CONFIG_ENV_IS_EMBEDDED
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_ENV_SECT_SIZE	(64 * 1024)
 #define CONFIG_ENV_ADDR		(0x00080000)
 #define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
 #define CONFIG_ENV_OVERWRITE	1
 #define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
 #define CONFIG_EXTRA_ENV_SETTINGS				\
 		"netboot=bootp; bootm\0"
 /* Board Clock */
 #define CONFIG_SYS_CLK_FREQ	48000000
 #define CONFIG_SYS_TMU_CLK_DIV	4
 #define CONFIG_SYS_HZ		1000
 #endif	/* __SH7757LCR_H */

include/configs/sh7763rdp.h

Diff comments View file @ a80a661

 /*
  * Configuation settings for the Renesas SH7763RDP board
  *
  * Copyright (C) 2008 Renesas Solutions Corp.
  * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #ifndef __SH7763RDP_H
 #define __SH7763RDP_H
 #define CONFIG_SH		1
 #define CONFIG_SH4		1
 #define CONFIG_CPU_SH7763	1
 #define CONFIG_SH7763RDP	1
 #define __LITTLE_ENDIAN		1
 /*
  * Command line configuration.
  */
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_FLASH
 #define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_NFS
 #define CONFIG_CMD_JFFS2
 #define CONFIG_BOOTDELAY        -1
 #define CONFIG_BOOTARGS         "console=ttySC2,115200 root=1f01"
 #define CONFIG_ENV_OVERWRITE    1
 #define CONFIG_VERSION_VARIABLE
 #undef  CONFIG_SHOW_BOOT_PROGRESS
 /* SCIF */
 #define CONFIG_SCIF_CONSOLE        1
 #define CONFIG_BAUDRATE         115200
 #define CONFIG_CONS_SCIF2		1
 #define CONFIG_SYS_TEXT_BASE	0x8FFC0000
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 #define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		256	/* Buffer size for input from the Console */
 #define CONFIG_SYS_PBSIZE		256	/* Buffer size for Console output */
 #define CONFIG_SYS_MAXARGS		16	/* max args accepted for monitor commands */
 #define CONFIG_SYS_BARGSIZE	512	/* Buffer size for Boot Arguments
 								passed to kernel */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }	/* List of legal baudrate
 												settings for this board */
 /* SDRAM */
 #define CONFIG_SYS_SDRAM_BASE		(0x8C000000)
 #define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024)
 #define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE)
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
 /* Flash(NOR) */
 #define CONFIG_SYS_FLASH_BASE		(0xA0000000)
 #define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
 #define CONFIG_SYS_MAX_FLASH_BANKS (1)
 #define CONFIG_SYS_MAX_FLASH_SECT  (520)
 /* U-boot setting */
 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
 #define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE)
 #define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
 /* Size of DRAM reserved for malloc() use */
 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
 #define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_FLASH_CFI_DRIVER
 #undef  CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
 /* Timeout for Flash erase operations (in ms) */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
 /* Timeout for Flash write operations (in ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
 /* Timeout for Flash set sector lock bit operations (in ms) */
 #define CONFIG_SYS_FLASH_LOCK_TOUT		(3 * 1000)
 /* Timeout for Flash clear lock bit operations (in ms) */
 #define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
 /* Use hardware flash sectors protection instead of U-Boot software protection */
 #undef  CONFIG_SYS_FLASH_PROTECTION
 #undef  CONFIG_SYS_DIRECT_FLASH_TFTP
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE	(128 * 1024)
 #define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
 /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
 #define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
 /* Clock */
 #define CONFIG_SYS_CLK_FREQ	66666666
 #define CONFIG_SYS_TMU_CLK_DIV		(4)	/* 4 (default), 16, 64, 256 or 1024 */
 #define CONFIG_SYS_HZ		1000
 /* Ether */
 #define CONFIG_SH_ETHER 1
 #define CONFIG_SH_ETHER_USE_PORT (1)
 #define CONFIG_SH_ETHER_PHY_ADDR (0x01)
 #define CONFIG_PHYLIB
 #define CONFIG_BITBANGMII
 #define CONFIG_BITBANGMII_MULTI
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
 #endif /* __SH7763RDP_H */