Merge with /home/wd/git/u-boot/custodian/u-boot-mpc86xx

Wolfgang Denk
2 parents 1d10b9e99d 3d98b85800
Showing 8 changed files Side-by-side Diff
board/freescale/common/pixis.c
board/freescale/common/pixis.h
board/mpc8641hpcn/Makefile
board/mpc8641hpcn/mpc8641hpcn.c
board/mpc8641hpcn/pixis.c
board/mpc8641hpcn/pixis.h
cpu/mpc86xx/cpu.c
doc/README.mpc8641hpcn
+/*
+ * Copyright 2006 Freescale Semiconductor
+ * Jeff Brown
+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <watchdog.h>
+#include <asm/cache.h>
+
+#include "pixis.h"
+
+
+static ulong strfractoint(uchar *strptr);
+
+
+/*
+ * Simple board reset.
+ */
+void pixis_reset(void)
+{
+    out8(PIXIS_BASE + PIXIS_RST, 0);
+}
+
+
+/*
+ * Per table 27, page 58 of MPC8641HPCN spec.
+ */
+int set_px_sysclk(ulong sysclk)
+{
+	u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
+
+	switch (sysclk) {
+	case 33:
+		sysclk_s = 0x04;
+		sysclk_r = 0x04;
+		sysclk_v = 0x07;
+		sysclk_aux = 0x00;
+		break;
+	case 40:
+		sysclk_s = 0x01;
+		sysclk_r = 0x1F;
+		sysclk_v = 0x20;
+		sysclk_aux = 0x01;
+		break;
+	case 50:
+		sysclk_s = 0x01;
+		sysclk_r = 0x1F;
+		sysclk_v = 0x2A;
+		sysclk_aux = 0x02;
+		break;
+	case 66:
+		sysclk_s = 0x01;
+		sysclk_r = 0x04;
+		sysclk_v = 0x04;
+		sysclk_aux = 0x03;
+		break;
+	case 83:
+		sysclk_s = 0x01;
+		sysclk_r = 0x1F;
+		sysclk_v = 0x4B;
+		sysclk_aux = 0x04;
+		break;
+	case 100:
+		sysclk_s = 0x01;
+		sysclk_r = 0x1F;
+		sysclk_v = 0x5C;
+		sysclk_aux = 0x05;
+		break;
+	case 134:
+		sysclk_s = 0x06;
+		sysclk_r = 0x1F;
+		sysclk_v = 0x3B;
+		sysclk_aux = 0x06;
+		break;
+	case 166:
+		sysclk_s = 0x06;
+		sysclk_r = 0x1F;
+		sysclk_v = 0x4B;
+		sysclk_aux = 0x07;
+		break;
+	default:
+		printf("Unsupported SYSCLK frequency.\n");
+		return 0;
+	}
+
+	vclkh = (sysclk_s << 5) | sysclk_r;
+	vclkl = sysclk_v;
+
+	out8(PIXIS_BASE + PIXIS_VCLKH, vclkh);
+	out8(PIXIS_BASE + PIXIS_VCLKL, vclkl);
+
+	out8(PIXIS_BASE + PIXIS_AUX, sysclk_aux);
+
+	return 1;
+}
+
+
+int set_px_mpxpll(ulong mpxpll)
+{
+	u8 tmp;
+	u8 val;
+
+	switch (mpxpll) {
+	case 2:
+	case 4:
+	case 6:
+	case 8:
+	case 10:
+	case 12:
+	case 14:
+	case 16:
+		val = (u8) mpxpll;
+		break;
+	default:
+		printf("Unsupported MPXPLL ratio.\n");
+		return 0;
+	}
+
+	tmp = in8(PIXIS_BASE + PIXIS_VSPEED1);
+	tmp = (tmp & 0xF0) | (val & 0x0F);
+	out8(PIXIS_BASE + PIXIS_VSPEED1, tmp);
+
+	return 1;
+}
+
+
+int set_px_corepll(ulong corepll)
+{
+	u8 tmp;
+	u8 val;
+
+	switch ((int)corepll) {
+	case 20:
+		val = 0x08;
+		break;
+	case 25:
+		val = 0x0C;
+		break;
+	case 30:
+		val = 0x10;
+		break;
+	case 35:
+		val = 0x1C;
+		break;
+	case 40:
+		val = 0x14;
+		break;
+	case 45:
+		val = 0x0E;
+		break;
+	default:
+		printf("Unsupported COREPLL ratio.\n");
+		return 0;
+	}
+
+	tmp = in8(PIXIS_BASE + PIXIS_VSPEED0);
+	tmp = (tmp & 0xE0) | (val & 0x1F);
+	out8(PIXIS_BASE + PIXIS_VSPEED0, tmp);
+
+	return 1;
+}
+
+
+void read_from_px_regs(int set)
+{
+	u8 mask = 0x1C;
+	u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN0);
+
+	if (set)
+		tmp = tmp | mask;
+	else
+		tmp = tmp & ~mask;
+	out8(PIXIS_BASE + PIXIS_VCFGEN0, tmp);
+}
+
+
+void read_from_px_regs_altbank(int set)
+{
+	u8 mask = 0x04;
+	u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN1);
+
+	if (set)
+		tmp = tmp | mask;
+	else
+		tmp = tmp & ~mask;
+	out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
+}
+
+
+void set_altbank(void)
+{
+	u8 tmp;
+
+	tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
+	tmp ^= 0x40;
+
+	out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
+}
+
+
+void set_px_go(void)
+{
+	u8 tmp;
+
+	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+	tmp = tmp & 0x1E;
+	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+
+	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+	tmp = tmp | 0x01;
+	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+}
+
+
+void set_px_go_with_watchdog(void)
+{
+	u8 tmp;
+
+	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+	tmp = tmp & 0x1E;
+	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+
+	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+	tmp = tmp | 0x09;
+	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+}
+
+
+int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp,
+			       int flag, int argc, char *argv[])
+{
+	u8 tmp;
+
+	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+	tmp = tmp & 0x1E;
+	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+
+	/* setting VCTL[WDEN] to 0 to disable watch dog */
+	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
+	tmp &= ~0x08;
+	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	   diswd, 1, 0, pixis_disable_watchdog_cmd,
+	   "diswd	- Disable watchdog timer \n",
+	   NULL);
+
+/*
+ * This function takes the non-integral cpu:mpx pll ratio
+ * and converts it to an integer that can be used to assign
+ * FPGA register values.
+ * input: strptr i.e. argv[2]
+ */
+
+static ulong strfractoint(uchar *strptr)
+{
+	int i, j, retval;
+	int mulconst;
+	int intarr_len = 0, decarr_len = 0, no_dec = 0;
+	ulong intval = 0, decval = 0;
+	uchar intarr[3], decarr[3];
+
+	/* Assign the integer part to intarr[]
+	 * If there is no decimal point i.e.
+	 * if the ratio is an integral value
+	 * simply create the intarr.
+	 */
+	i = 0;
+	while (strptr[i] != 46) {
+		if (strptr[i] == 0) {
+			no_dec = 1;
+			break;
+		}
+		intarr[i] = strptr[i];
+		i++;
+	}
+
+	/* Assign length of integer part to intarr_len. */
+	intarr_len = i;
+	intarr[i] = '\0';
+
+	if (no_dec) {
+		/* Currently needed only for single digit corepll ratios */
+		mulconst = 10;
+		decval = 0;
+	} else {
+		j = 0;
+		i++;		/* Skipping the decimal point */
+		while ((strptr[i] > 47) && (strptr[i] < 58)) {
+			decarr[j] = strptr[i];
+			i++;
+			j++;
+		}
+
+		decarr_len = j;
+		decarr[j] = '\0';
+
+		mulconst = 1;
+		for (i = 0; i < decarr_len; i++)
+			mulconst *= 10;
+		decval = simple_strtoul(decarr, NULL, 10);
+	}
+
+	intval = simple_strtoul(intarr, NULL, 10);
+	intval = intval * mulconst;
+
+	retval = intval + decval;
+
+	return retval;
+}
+
+
+int
+pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	ulong val;
+	ulong corepll;
+
+	/*
+	 * No args is a simple reset request.
+	 */
+	if (argc <= 1) {
+		pixis_reset();
+		/* not reached */
+	}
+
+	if (strcmp(argv[1], "cf") == 0) {
+
+		/*
+		 * Reset with frequency changed:
+		 *    cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+		 */
+		if (argc < 5) {
+			puts(cmdtp->usage);
+			return 1;
+		}
+
+		read_from_px_regs(0);
+
+		val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
+
+		corepll = strfractoint(argv[3]);
+		val = val + set_px_corepll(corepll);
+		val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
+		if (val == 3) {
+			puts("Setting registers VCFGEN0 and VCTL\n");
+			read_from_px_regs(1);
+			puts("Resetting board with values from ");
+			puts("VSPEED0, VSPEED1, VCLKH, and VCLKL \n");
+			set_px_go();
+		} else {
+			puts(cmdtp->usage);
+			return 1;
+		}
+
+		while (1) ;	/* Not reached */
+
+	} else if (strcmp(argv[1], "altbank") == 0) {
+
+		/*
+		 * Reset using alternate flash bank:
+		 */
+		if (argv[2] == 0) {
+			/*
+			 * Reset from alternate bank without changing
+			 * frequency and without watchdog timer enabled.
+			 *	altbank
+			 */
+			read_from_px_regs(0);
+			read_from_px_regs_altbank(0);
+			if (argc > 2) {
+				puts(cmdtp->usage);
+				return 1;
+			}
+			puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
+			set_altbank();
+			read_from_px_regs_altbank(1);
+			puts("Resetting board to boot from the other bank.\n");
+			set_px_go();
+
+		} else if (strcmp(argv[2], "cf") == 0) {
+			/*
+			 * Reset with frequency changed
+			 *    altbank cf <SYSCLK freq> <COREPLL ratio>
+			 *				<MPXPLL ratio>
+			 */
+			read_from_px_regs(0);
+			read_from_px_regs_altbank(0);
+			val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
+			corepll = strfractoint(argv[4]);
+			val = val + set_px_corepll(corepll);
+			val = val + set_px_mpxpll(simple_strtoul(argv[5],
+								 NULL, 10));
+			if (val == 3) {
+				puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
+				set_altbank();
+				read_from_px_regs(1);
+				read_from_px_regs_altbank(1);
+				puts("Enabling watchdog timer on the FPGA\n");
+				puts("Resetting board with values from ");
+				puts("VSPEED0, VSPEED1, VCLKH and VCLKL ");
+				puts("to boot from the other bank.\n");
+				set_px_go_with_watchdog();
+			} else {
+				puts(cmdtp->usage);
+				return 1;
+			}
+
+			while (1) ;	/* Not reached */
+
+		} else if (strcmp(argv[2], "wd") == 0) {
+			/*
+			 * Reset from alternate bank without changing
+			 * frequencies but with watchdog timer enabled:
+			 *    altbank wd
+			 */
+			read_from_px_regs(0);
+			read_from_px_regs_altbank(0);
+			puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
+			set_altbank();
+			read_from_px_regs_altbank(1);
+			puts("Enabling watchdog timer on the FPGA\n");
+			puts("Resetting board to boot from the other bank.\n");
+			set_px_go_with_watchdog();
+			while (1) ;	/* Not reached */
+
+		} else {
+			puts(cmdtp->usage);
+			return 1;
+		}
+
+	} else {
+		puts(cmdtp->usage);
+		return 1;
+	}
+
+	return 0;
+}
+
+
+U_BOOT_CMD(
+	pixis_reset, CFG_MAXARGS, 1, pixis_reset_cmd,
+	"pixis_reset - Reset the board using the FPGA sequencer\n",
+	"    pixis_reset\n"
+	"    pixis_reset [altbank]\n"
+	"    pixis_reset altbank wd\n"
+	"    pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
+	"    pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
+	);
+/*
+ * Copyright 2006 Freescale Semiconductor
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+extern void pixis_reset(void);
+extern int set_px_sysclk(ulong sysclk);
+extern int set_px_mpxpll(ulong mpxpll);
+extern int set_px_corepll(ulong corepll);
+extern void read_from_px_regs(int set);
+extern void read_from_px_regs_altbank(int set);
+extern void set_altbank(void);
+extern void set_px_go(void);
+extern void set_px_go_with_watchdog(void);
@@ -25,7 +25,9 @@
  
 LIB	= $(obj)lib$(BOARD).a
  
-COBJS	:= $(BOARD).o pixis.o sys_eeprom.o
+COBJS	:= $(BOARD).o sys_eeprom.o \
+		../freescale/common/pixis.o
+
 SOBJS	:= init.o
  
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 /*
- * Copyright 2004 Freescale Semiconductor.
- * Jeff Brown
- * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
+ * Copyright 2006, 2007 Freescale Semiconductor.
  *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  
  
@@ -25,18 +21,18 @@
  */
  
 #include <common.h>
-#include <command.h>
 #include <pci.h>
 #include <asm/processor.h>
 #include <asm/immap_86xx.h>
 #include <spd.h>
+#include <asm/io.h>
  
 #if defined(CONFIG_OF_FLAT_TREE)
 #include <ft_build.h>
 extern void ft_cpu_setup(void *blob, bd_t *bd);
 #endif
  
-#include "pixis.h"
+#include "../freescale/common/pixis.h"
  
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
@@ -256,109 +252,6 @@
 	}
 }
 #endif
-
-
-void
-mpc8641_reset_board(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
-{
-	char cmd;
-	ulong val;
-	ulong corepll;
-
-	/*
-	 * No args is a simple reset request.
-	 */
-	if (argc <= 1) {
-		out8(PIXIS_BASE + PIXIS_RST, 0);
-		/* not reached */
-	}
-
-	cmd = argv[1][1];
-	switch (cmd) {
-	case 'f':		/* reset with frequency changed */
-		if (argc < 5)
-			goto my_usage;
-		read_from_px_regs(0);
-
-		val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
-
-		corepll = strfractoint(argv[3]);
-		val = val + set_px_corepll(corepll);
-		val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
-		if (val == 3) {
-			puts("Setting registers VCFGEN0 and VCTL\n");
-			read_from_px_regs(1);
-			puts("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
-			set_px_go();
-		} else
-			goto my_usage;
-
-		while (1) ;	/* Not reached */
-
-	case 'l':
-		if (argv[2][1] == 'f') {
-			read_from_px_regs(0);
-			read_from_px_regs_altbank(0);
-			/* reset with frequency changed */
-			val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
-
-			corepll = strfractoint(argv[4]);
-			val = val + set_px_corepll(corepll);
-			val = val + set_px_mpxpll(simple_strtoul(argv[5],
-								 NULL, 10));
-			if (val == 3) {
-				puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
-				set_altbank();
-				read_from_px_regs(1);
-				read_from_px_regs_altbank(1);
-				puts("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
-				set_px_go_with_watchdog();
-			} else
-				goto my_usage;
-
-			while (1) ;	/* Not reached */
-
-		} else if (argv[2][1] == 'd') {
-			/*
-			 * Reset from alternate bank without changing
-			 * frequencies but with watchdog timer enabled.
-			 */
-			read_from_px_regs(0);
-			read_from_px_regs_altbank(0);
-			puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
-			set_altbank();
-			read_from_px_regs_altbank(1);
-			puts("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
-			set_px_go_with_watchdog();
-			while (1) ;	/* Not reached */
-
-		} else {
-			/*
-			 * Reset from next bank without changing
-			 * frequency and without watchdog timer enabled.
-			 */
-			read_from_px_regs(0);
-			read_from_px_regs_altbank(0);
-			if (argc > 2)
-				goto my_usage;
-			puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
-			set_altbank();
-			read_from_px_regs_altbank(1);
-			puts("Resetting board to boot from the other bank....\n");
-			set_px_go();
-		}
-
-	default:
-		goto my_usage;
-	}
-
-my_usage:
-	puts("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
-	puts("       reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
-	puts("       reset altbank [wd]\n");
-	puts("For example:   reset cf 40 2.5 10\n");
-	puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
-}
  
  
 /*
-/*
- * Copyright 2006 Freescale Semiconductor
- * Jeff Brown
- * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <watchdog.h>
-#include <command.h>
-#include <asm/cache.h>
-#include <mpc86xx.h>
-
-#include "pixis.h"
-
-
-/*
- * Per table 27, page 58 of MPC8641HPCN spec.
- */
-int set_px_sysclk(ulong sysclk)
-{
-	u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
-
-	switch (sysclk) {
-	case 33:
-		sysclk_s = 0x04;
-		sysclk_r = 0x04;
-		sysclk_v = 0x07;
-		sysclk_aux = 0x00;
-		break;
-	case 40:
-		sysclk_s = 0x01;
-		sysclk_r = 0x1F;
-		sysclk_v = 0x20;
-		sysclk_aux = 0x01;
-		break;
-	case 50:
-		sysclk_s = 0x01;
-		sysclk_r = 0x1F;
-		sysclk_v = 0x2A;
-		sysclk_aux = 0x02;
-		break;
-	case 66:
-		sysclk_s = 0x01;
-		sysclk_r = 0x04;
-		sysclk_v = 0x04;
-		sysclk_aux = 0x03;
-		break;
-	case 83:
-		sysclk_s = 0x01;
-		sysclk_r = 0x1F;
-		sysclk_v = 0x4B;
-		sysclk_aux = 0x04;
-		break;
-	case 100:
-		sysclk_s = 0x01;
-		sysclk_r = 0x1F;
-		sysclk_v = 0x5C;
-		sysclk_aux = 0x05;
-		break;
-	case 134:
-		sysclk_s = 0x06;
-		sysclk_r = 0x1F;
-		sysclk_v = 0x3B;
-		sysclk_aux = 0x06;
-		break;
-	case 166:
-		sysclk_s = 0x06;
-		sysclk_r = 0x1F;
-		sysclk_v = 0x4B;
-		sysclk_aux = 0x07;
-		break;
-	default:
-		printf("Unsupported SYSCLK frequency.\n");
-		return 0;
-	}
-
-	vclkh = (sysclk_s << 5) | sysclk_r;
-	vclkl = sysclk_v;
-
-	out8(PIXIS_BASE + PIXIS_VCLKH, vclkh);
-	out8(PIXIS_BASE + PIXIS_VCLKL, vclkl);
-
-	out8(PIXIS_BASE + PIXIS_AUX, sysclk_aux);
-
-	return 1;
-}
-
-
-int set_px_mpxpll(ulong mpxpll)
-{
-	u8 tmp;
-	u8 val;
-
-	switch (mpxpll) {
-	case 2:
-	case 4:
-	case 6:
-	case 8:
-	case 10:
-	case 12:
-	case 14:
-	case 16:
-		val = (u8) mpxpll;
-		break;
-	default:
-		printf("Unsupported MPXPLL ratio.\n");
-		return 0;
-	}
-
-	tmp = in8(PIXIS_BASE + PIXIS_VSPEED1);
-	tmp = (tmp & 0xF0) | (val & 0x0F);
-	out8(PIXIS_BASE + PIXIS_VSPEED1, tmp);
-
-	return 1;
-}
-
-
-int set_px_corepll(ulong corepll)
-{
-	u8 tmp;
-	u8 val;
-
-	switch ((int)corepll) {
-	case 20:
-		val = 0x08;
-		break;
-	case 25:
-		val = 0x0C;
-		break;
-	case 30:
-		val = 0x10;
-		break;
-	case 35:
-		val = 0x1C;
-		break;
-	case 40:
-		val = 0x14;
-		break;
-	case 45:
-		val = 0x0E;
-		break;
-	default:
-		printf("Unsupported COREPLL ratio.\n");
-		return 0;
-	}
-
-	tmp = in8(PIXIS_BASE + PIXIS_VSPEED0);
-	tmp = (tmp & 0xE0) | (val & 0x1F);
-	out8(PIXIS_BASE + PIXIS_VSPEED0, tmp);
-
-	return 1;
-}
-
-
-void read_from_px_regs(int set)
-{
-	u8 mask = 0x1C;
-	u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN0);
-
-	if (set)
-		tmp = tmp | mask;
-	else
-		tmp = tmp & ~mask;
-	out8(PIXIS_BASE + PIXIS_VCFGEN0, tmp);
-}
-
-
-void read_from_px_regs_altbank(int set)
-{
-	u8 mask = 0x04;
-	u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN1);
-
-	if (set)
-		tmp = tmp | mask;
-	else
-		tmp = tmp & ~mask;
-	out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
-}
-
-
-void set_altbank(void)
-{
-	u8 tmp;
-
-	tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
-	tmp ^= 0x40;
-
-	out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
-}
-
-
-void set_px_go(void)
-{
-	u8 tmp;
-
-	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
-	tmp = tmp & 0x1E;
-	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
-
-	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
-	tmp = tmp | 0x01;
-	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
-}
-
-
-void set_px_go_with_watchdog(void)
-{
-	u8 tmp;
-
-	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
-	tmp = tmp & 0x1E;
-	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
-
-	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
-	tmp = tmp | 0x09;
-	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
-}
-
-
-int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-	u8 tmp;
-
-	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
-	tmp = tmp & 0x1E;
-	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
-
-	/* setting VCTL[WDEN] to 0 to disable watch dog */
-	tmp = in8(PIXIS_BASE + PIXIS_VCTL);
-	tmp &= ~0x08;
-	out8(PIXIS_BASE + PIXIS_VCTL, tmp);
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	   diswd, 1, 0, disable_watchdog,
-	   "diswd	- Disable watchdog timer \n",
-	   NULL);
-
-/*
- * This function takes the non-integral cpu:mpx pll ratio
- * and converts it to an integer that can be used to assign
- * FPGA register values.
- * input: strptr i.e. argv[2]
- */
-
-ulong strfractoint(uchar *strptr)
-{
-	int i, j, retval;
-	int mulconst;
-	int intarr_len = 0, decarr_len = 0, no_dec = 0;
-	ulong intval = 0, decval = 0;
-	uchar intarr[3], decarr[3];
-
-	/* Assign the integer part to intarr[]
-	 * If there is no decimal point i.e.
-	 * if the ratio is an integral value
-	 * simply create the intarr.
-	 */
-	i = 0;
-	while (strptr[i] != 46) {
-		if (strptr[i] == 0) {
-			no_dec = 1;
-			break;
-		}
-		intarr[i] = strptr[i];
-		i++;
-	}
-
-	/* Assign length of integer part to intarr_len. */
-	intarr_len = i;
-	intarr[i] = '\0';
-
-	if (no_dec) {
-		/* Currently needed only for single digit corepll ratios */
-		mulconst = 10;
-		decval = 0;
-	} else {
-		j = 0;
-		i++;		/* Skipping the decimal point */
-		while ((strptr[i] > 47) && (strptr[i] < 58)) {
-			decarr[j] = strptr[i];
-			i++;
-			j++;
-		}
-
-		decarr_len = j;
-		decarr[j] = '\0';
-
-		mulconst = 1;
-		for (i = 0; i < decarr_len; i++)
-			mulconst *= 10;
-		decval = simple_strtoul(decarr, NULL, 10);
-	}
-
-	intval = simple_strtoul(intarr, NULL, 10);
-	intval = intval * mulconst;
-
-	retval = intval + decval;
-
-	return retval;
-}
-/*
- * Copyright 2006 Freescale Semiconductor
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-extern int set_px_sysclk(ulong sysclk);
-extern int set_px_mpxpll(ulong mpxpll);
-extern int set_px_corepll(ulong corepll);
-extern void read_from_px_regs(int set);
-extern void read_from_px_regs_altbank(int set);
-extern void set_altbank(void);
-extern void set_px_go(void);
-extern void set_px_go_with_watchdog(void);
-extern int disable_watchdog(cmd_tbl_t *cmdtp,
-			    int flag, int argc, char *argv[]);
-extern ulong strfractoint(uchar *strptr);
@@ -32,12 +32,6 @@
 #include <ft_build.h>
 #endif
  
-#ifdef CONFIG_MPC8641HPCN
-extern void mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag,
-				int argc, char *argv[]);
-#endif
-
-
 int
 checkcpu(void)
 {
@@ -185,7 +179,7 @@
  
 #else /* CONFIG_MPC8641HPCN */
  
-	mpc8641_reset_board(cmdtp, flag, argc, argv);
+	out8(PIXIS_BASE + PIXIS_RST, 0);
  
 #endif /* !CONFIG_MPC8641HPCN */
  
@@ -121,4 +121,38 @@
 	0xe300_0000	0xe3ff_ffff	PCI2/PEX2 IO	16M
 	0xfe00_0000	0xfeff_ffff	Flash(alternate)16M
 	0xff00_0000	0xffff_ffff	Flash(boot bank)16M
+
+5. pixis_reset command
+--------------------
+A new command, "pixis_reset", is introduced to reset mpc8641hpcn board
+using the FPGA sequencer.  When the board restarts, it has the option
+of using either the current or alternate flash bank as the boot
+image, with or without the watchdog timer enabled, and finally with
+or without frequency changes.
+
+Usage is;
+
+	pixis_reset
+	pixis_reset altbank
+	pixis_reset altbank wd
+	pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+	pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+
+Examples;
+
+	/* reset to current bank, like "reset" command */
+	pixis_reset
+
+	/* reset board but use the to alternate flash bank */
+	pixis_reset altbank
+
+	/* reset board, use alternate flash bank with watchdog timer enabled*/
+	pixis_reset altbank wd
+
+	/* reset board to alternate bank with frequency changed.
+	 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
+	 */
+	pixis-reset altbank cf 40 2.5 10
+
+Valid clock choices are in the 8641 Reference Manuals.
	1	+/*
	2	+ * Copyright 2006 Freescale Semiconductor
	3	+ * Jeff Brown
	4	+ * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
	5	+ *
	6	+ * See file CREDITS for list of people who contributed to this
	7	+ * project.
	8	+ *
	9	+ * This program is free software; you can redistribute it and/or
	10	+ * modify it under the terms of the GNU General Public License as
	11	+ * published by the Free Software Foundation; either version 2 of
	12	+ * the License, or (at your option) any later version.
	13	+ *
	14	+ * This program is distributed in the hope that it will be useful,
	15	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	+ * GNU General Public License for more details.
	18	+ *
	19	+ * You should have received a copy of the GNU General Public License
	20	+ * along with this program; if not, write to the Free Software
	21	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	+ * MA 02111-1307 USA
	23	+ */
	24	+
	25	+#include <common.h>
	26	+#include <command.h>
	27	+#include <watchdog.h>
	28	+#include <asm/cache.h>
	29	+
	30	+#include "pixis.h"
	31	+
	32	+
	33	+static ulong strfractoint(uchar *strptr);
	34	+
	35	+
	36	+/*
	37	+ * Simple board reset.
	38	+ */
	39	+void pixis_reset(void)
	40	+{
	41	+ out8(PIXIS_BASE + PIXIS_RST, 0);
	42	+}
	43	+
	44	+
	45	+/*
	46	+ * Per table 27, page 58 of MPC8641HPCN spec.
	47	+ */
	48	+int set_px_sysclk(ulong sysclk)
	49	+{
	50	+ u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
	51	+
	52	+ switch (sysclk) {
	53	+ case 33:
	54	+ sysclk_s = 0x04;
	55	+ sysclk_r = 0x04;
	56	+ sysclk_v = 0x07;
	57	+ sysclk_aux = 0x00;
	58	+ break;
	59	+ case 40:
	60	+ sysclk_s = 0x01;
	61	+ sysclk_r = 0x1F;
	62	+ sysclk_v = 0x20;
	63	+ sysclk_aux = 0x01;
	64	+ break;
	65	+ case 50:
	66	+ sysclk_s = 0x01;
	67	+ sysclk_r = 0x1F;
	68	+ sysclk_v = 0x2A;
	69	+ sysclk_aux = 0x02;
	70	+ break;
	71	+ case 66:
	72	+ sysclk_s = 0x01;
	73	+ sysclk_r = 0x04;
	74	+ sysclk_v = 0x04;
	75	+ sysclk_aux = 0x03;
	76	+ break;
	77	+ case 83:
	78	+ sysclk_s = 0x01;
	79	+ sysclk_r = 0x1F;
	80	+ sysclk_v = 0x4B;
	81	+ sysclk_aux = 0x04;
	82	+ break;
	83	+ case 100:
	84	+ sysclk_s = 0x01;
	85	+ sysclk_r = 0x1F;
	86	+ sysclk_v = 0x5C;
	87	+ sysclk_aux = 0x05;
	88	+ break;
	89	+ case 134:
	90	+ sysclk_s = 0x06;
	91	+ sysclk_r = 0x1F;
	92	+ sysclk_v = 0x3B;
	93	+ sysclk_aux = 0x06;
	94	+ break;
	95	+ case 166:
	96	+ sysclk_s = 0x06;
	97	+ sysclk_r = 0x1F;
	98	+ sysclk_v = 0x4B;
	99	+ sysclk_aux = 0x07;
	100	+ break;
	101	+ default:
	102	+ printf("Unsupported SYSCLK frequency.\n");
	103	+ return 0;
	104	+ }
	105	+
	106	+ vclkh = (sysclk_s << 5) \| sysclk_r;
	107	+ vclkl = sysclk_v;
	108	+
	109	+ out8(PIXIS_BASE + PIXIS_VCLKH, vclkh);
	110	+ out8(PIXIS_BASE + PIXIS_VCLKL, vclkl);
	111	+
	112	+ out8(PIXIS_BASE + PIXIS_AUX, sysclk_aux);
	113	+
	114	+ return 1;
	115	+}
	116	+
	117	+
	118	+int set_px_mpxpll(ulong mpxpll)
	119	+{
	120	+ u8 tmp;
	121	+ u8 val;
	122	+
	123	+ switch (mpxpll) {
	124	+ case 2:
	125	+ case 4:
	126	+ case 6:
	127	+ case 8:
	128	+ case 10:
	129	+ case 12:
	130	+ case 14:
	131	+ case 16:
	132	+ val = (u8) mpxpll;
	133	+ break;
	134	+ default:
	135	+ printf("Unsupported MPXPLL ratio.\n");
	136	+ return 0;
	137	+ }
	138	+
	139	+ tmp = in8(PIXIS_BASE + PIXIS_VSPEED1);
	140	+ tmp = (tmp & 0xF0) \| (val & 0x0F);
	141	+ out8(PIXIS_BASE + PIXIS_VSPEED1, tmp);
	142	+
	143	+ return 1;
	144	+}
	145	+
	146	+
	147	+int set_px_corepll(ulong corepll)
	148	+{
	149	+ u8 tmp;
	150	+ u8 val;
	151	+
	152	+ switch ((int)corepll) {
	153	+ case 20:
	154	+ val = 0x08;
	155	+ break;
	156	+ case 25:
	157	+ val = 0x0C;
	158	+ break;
	159	+ case 30:
	160	+ val = 0x10;
	161	+ break;
	162	+ case 35:
	163	+ val = 0x1C;
	164	+ break;
	165	+ case 40:
	166	+ val = 0x14;
	167	+ break;
	168	+ case 45:
	169	+ val = 0x0E;
	170	+ break;
	171	+ default:
	172	+ printf("Unsupported COREPLL ratio.\n");
	173	+ return 0;
	174	+ }
	175	+
	176	+ tmp = in8(PIXIS_BASE + PIXIS_VSPEED0);
	177	+ tmp = (tmp & 0xE0) \| (val & 0x1F);
	178	+ out8(PIXIS_BASE + PIXIS_VSPEED0, tmp);
	179	+
	180	+ return 1;
	181	+}
	182	+
	183	+
	184	+void read_from_px_regs(int set)
	185	+{
	186	+ u8 mask = 0x1C;
	187	+ u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN0);
	188	+
	189	+ if (set)
	190	+ tmp = tmp \| mask;
	191	+ else
	192	+ tmp = tmp & ~mask;
	193	+ out8(PIXIS_BASE + PIXIS_VCFGEN0, tmp);
	194	+}
	195	+
	196	+
	197	+void read_from_px_regs_altbank(int set)
	198	+{
	199	+ u8 mask = 0x04;
	200	+ u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN1);
	201	+
	202	+ if (set)
	203	+ tmp = tmp \| mask;
	204	+ else
	205	+ tmp = tmp & ~mask;
	206	+ out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
	207	+}
	208	+
	209	+
	210	+void set_altbank(void)
	211	+{
	212	+ u8 tmp;
	213	+
	214	+ tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
	215	+ tmp ^= 0x40;
	216	+
	217	+ out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
	218	+}
	219	+
	220	+
	221	+void set_px_go(void)
	222	+{
	223	+ u8 tmp;
	224	+
	225	+ tmp = in8(PIXIS_BASE + PIXIS_VCTL);
	226	+ tmp = tmp & 0x1E;
	227	+ out8(PIXIS_BASE + PIXIS_VCTL, tmp);
	228	+
	229	+ tmp = in8(PIXIS_BASE + PIXIS_VCTL);
	230	+ tmp = tmp \| 0x01;
	231	+ out8(PIXIS_BASE + PIXIS_VCTL, tmp);
	232	+}
	233	+
	234	+
	235	+void set_px_go_with_watchdog(void)
	236	+{
	237	+ u8 tmp;
	238	+
	239	+ tmp = in8(PIXIS_BASE + PIXIS_VCTL);
	240	+ tmp = tmp & 0x1E;
	241	+ out8(PIXIS_BASE + PIXIS_VCTL, tmp);
	242	+
	243	+ tmp = in8(PIXIS_BASE + PIXIS_VCTL);
	244	+ tmp = tmp \| 0x09;
	245	+ out8(PIXIS_BASE + PIXIS_VCTL, tmp);
	246	+}
	247	+
	248	+
	249	+int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp,
	250	+ int flag, int argc, char *argv[])
	251	+{
	252	+ u8 tmp;
	253	+
	254	+ tmp = in8(PIXIS_BASE + PIXIS_VCTL);
	255	+ tmp = tmp & 0x1E;
	256	+ out8(PIXIS_BASE + PIXIS_VCTL, tmp);
	257	+
	258	+ /* setting VCTL[WDEN] to 0 to disable watch dog */
	259	+ tmp = in8(PIXIS_BASE + PIXIS_VCTL);
	260	+ tmp &= ~0x08;
	261	+ out8(PIXIS_BASE + PIXIS_VCTL, tmp);
	262	+
	263	+ return 0;
	264	+}
	265	+
	266	+U_BOOT_CMD(
	267	+ diswd, 1, 0, pixis_disable_watchdog_cmd,
	268	+ "diswd - Disable watchdog timer \n",
	269	+ NULL);
	270	+
	271	+/*
	272	+ * This function takes the non-integral cpu:mpx pll ratio
	273	+ * and converts it to an integer that can be used to assign
	274	+ * FPGA register values.
	275	+ * input: strptr i.e. argv[2]
	276	+ */
	277	+
	278	+static ulong strfractoint(uchar *strptr)
	279	+{
	280	+ int i, j, retval;
	281	+ int mulconst;
	282	+ int intarr_len = 0, decarr_len = 0, no_dec = 0;
	283	+ ulong intval = 0, decval = 0;
	284	+ uchar intarr[3], decarr[3];
	285	+
	286	+ /* Assign the integer part to intarr[]
	287	+ * If there is no decimal point i.e.
	288	+ * if the ratio is an integral value
	289	+ * simply create the intarr.
	290	+ */
	291	+ i = 0;
	292	+ while (strptr[i] != 46) {
	293	+ if (strptr[i] == 0) {
	294	+ no_dec = 1;
	295	+ break;
	296	+ }
	297	+ intarr[i] = strptr[i];
	298	+ i++;
	299	+ }
	300	+
	301	+ /* Assign length of integer part to intarr_len. */
	302	+ intarr_len = i;
	303	+ intarr[i] = '\0';
	304	+
	305	+ if (no_dec) {
	306	+ /* Currently needed only for single digit corepll ratios */
	307	+ mulconst = 10;
	308	+ decval = 0;
	309	+ } else {
	310	+ j = 0;
	311	+ i++; /* Skipping the decimal point */
	312	+ while ((strptr[i] > 47) && (strptr[i] < 58)) {
	313	+ decarr[j] = strptr[i];
	314	+ i++;
	315	+ j++;
	316	+ }
	317	+
	318	+ decarr_len = j;
	319	+ decarr[j] = '\0';
	320	+
	321	+ mulconst = 1;
	322	+ for (i = 0; i < decarr_len; i++)
	323	+ mulconst *= 10;
	324	+ decval = simple_strtoul(decarr, NULL, 10);
	325	+ }
	326	+
	327	+ intval = simple_strtoul(intarr, NULL, 10);
	328	+ intval = intval * mulconst;
	329	+
	330	+ retval = intval + decval;
	331	+
	332	+ return retval;
	333	+}
	334	+
	335	+
	336	+int
	337	+pixis_reset_cmd(cmd_tbl_t cmdtp, int flag, int argc, char argv[])
	338	+{
	339	+ ulong val;
	340	+ ulong corepll;
	341	+
	342	+ /*
	343	+ * No args is a simple reset request.
	344	+ */
	345	+ if (argc <= 1) {
	346	+ pixis_reset();
	347	+ /* not reached */
	348	+ }
	349	+
	350	+ if (strcmp(argv[1], "cf") == 0) {
	351	+
	352	+ /*
	353	+ * Reset with frequency changed:
	354	+ * cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
	355	+ */
	356	+ if (argc < 5) {
	357	+ puts(cmdtp->usage);
	358	+ return 1;
	359	+ }
	360	+
	361	+ read_from_px_regs(0);
	362	+
	363	+ val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
	364	+
	365	+ corepll = strfractoint(argv[3]);
	366	+ val = val + set_px_corepll(corepll);
	367	+ val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
	368	+ if (val == 3) {
	369	+ puts("Setting registers VCFGEN0 and VCTL\n");
	370	+ read_from_px_regs(1);
	371	+ puts("Resetting board with values from ");
	372	+ puts("VSPEED0, VSPEED1, VCLKH, and VCLKL \n");
	373	+ set_px_go();
	374	+ } else {
	375	+ puts(cmdtp->usage);
	376	+ return 1;
	377	+ }
	378	+
	379	+ while (1) ; /* Not reached */
	380	+
	381	+ } else if (strcmp(argv[1], "altbank") == 0) {
	382	+
	383	+ /*
	384	+ * Reset using alternate flash bank:
	385	+ */
	386	+ if (argv[2] == 0) {
	387	+ /*
	388	+ * Reset from alternate bank without changing
	389	+ * frequency and without watchdog timer enabled.
	390	+ * altbank
	391	+ */
	392	+ read_from_px_regs(0);
	393	+ read_from_px_regs_altbank(0);
	394	+ if (argc > 2) {
	395	+ puts(cmdtp->usage);
	396	+ return 1;
	397	+ }
	398	+ puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
	399	+ set_altbank();
	400	+ read_from_px_regs_altbank(1);
	401	+ puts("Resetting board to boot from the other bank.\n");
	402	+ set_px_go();
	403	+
	404	+ } else if (strcmp(argv[2], "cf") == 0) {
	405	+ /*
	406	+ * Reset with frequency changed
	407	+ * altbank cf <SYSCLK freq> <COREPLL ratio>
	408	+ * <MPXPLL ratio>
	409	+ */
	410	+ read_from_px_regs(0);
	411	+ read_from_px_regs_altbank(0);
	412	+ val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
	413	+ corepll = strfractoint(argv[4]);
	414	+ val = val + set_px_corepll(corepll);
	415	+ val = val + set_px_mpxpll(simple_strtoul(argv[5],
	416	+ NULL, 10));
	417	+ if (val == 3) {
	418	+ puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
	419	+ set_altbank();
	420	+ read_from_px_regs(1);
	421	+ read_from_px_regs_altbank(1);
	422	+ puts("Enabling watchdog timer on the FPGA\n");
	423	+ puts("Resetting board with values from ");
	424	+ puts("VSPEED0, VSPEED1, VCLKH and VCLKL ");
	425	+ puts("to boot from the other bank.\n");
	426	+ set_px_go_with_watchdog();
	427	+ } else {
	428	+ puts(cmdtp->usage);
	429	+ return 1;
	430	+ }
	431	+
	432	+ while (1) ; /* Not reached */
	433	+
	434	+ } else if (strcmp(argv[2], "wd") == 0) {
	435	+ /*
	436	+ * Reset from alternate bank without changing
	437	+ * frequencies but with watchdog timer enabled:
	438	+ * altbank wd
	439	+ */
	440	+ read_from_px_regs(0);
	441	+ read_from_px_regs_altbank(0);
	442	+ puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
	443	+ set_altbank();
	444	+ read_from_px_regs_altbank(1);
	445	+ puts("Enabling watchdog timer on the FPGA\n");
	446	+ puts("Resetting board to boot from the other bank.\n");
	447	+ set_px_go_with_watchdog();
	448	+ while (1) ; /* Not reached */
	449	+
	450	+ } else {
	451	+ puts(cmdtp->usage);
	452	+ return 1;
	453	+ }
	454	+
	455	+ } else {
	456	+ puts(cmdtp->usage);
	457	+ return 1;
	458	+ }
	459	+
	460	+ return 0;
	461	+}
	462	+
	463	+
	464	+U_BOOT_CMD(
	465	+ pixis_reset, CFG_MAXARGS, 1, pixis_reset_cmd,
	466	+ "pixis_reset - Reset the board using the FPGA sequencer\n",
	467	+ " pixis_reset\n"
	468	+ " pixis_reset [altbank]\n"
	469	+ " pixis_reset altbank wd\n"
	470	+ " pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
	471	+ " pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
	472	+ );
...	...	@@ -25,7 +25,9 @@
25	25
26	26	LIB = $(obj)lib$(BOARD).a
27	27
28		-COBJS := $(BOARD).o pixis.o sys_eeprom.o
	28	+COBJS := $(BOARD).o sys_eeprom.o \
	29	+ ../freescale/common/pixis.o
	30	+
29	31	SOBJS := init.o
30	32
31	33	SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
1	1	/*
2		- * Copyright 2004 Freescale Semiconductor.
3		- * Jeff Brown
4		- * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
	2	+ * Copyright 2006, 2007 Freescale Semiconductor.
5	3	*
6		- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
7		- *
8	4	* See file CREDITS for list of people who contributed to this
9	5	* project.
10	6	*
11	7
12	8
...	...	@@ -25,18 +21,18 @@
25	21	*/
26	22
27	23	#include <common.h>
28		-#include <command.h>
29	24	#include <pci.h>
30	25	#include <asm/processor.h>
31	26	#include <asm/immap_86xx.h>
32	27	#include <spd.h>
	28	+#include <asm/io.h>
33	29
34	30	#if defined(CONFIG_OF_FLAT_TREE)
35	31	#include <ft_build.h>
36	32	extern void ft_cpu_setup(void blob, bd_t bd);
37	33	#endif
38	34
39		-#include "pixis.h"
	35	+#include "../freescale/common/pixis.h"
40	36
41	37	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
42	38	extern void ddr_enable_ecc(unsigned int dram_size);
...	...	@@ -256,109 +252,6 @@
256	252	}
257	253	}
258	254	#endif
259		-
260		-
261		-void
262		-mpc8641_reset_board(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
263		-{
264		- char cmd;
265		- ulong val;
266		- ulong corepll;
267		-
268		- /*
269		- * No args is a simple reset request.
270		- */
271		- if (argc <= 1) {
272		- out8(PIXIS_BASE + PIXIS_RST, 0);
273		- /* not reached */
274		- }
275		-
276		- cmd = argv[1][1];
277		- switch (cmd) {
278		- case 'f': /* reset with frequency changed */
279		- if (argc < 5)
280		- goto my_usage;
281		- read_from_px_regs(0);
282		-
283		- val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
284		-
285		- corepll = strfractoint(argv[3]);
286		- val = val + set_px_corepll(corepll);
287		- val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
288		- if (val == 3) {
289		- puts("Setting registers VCFGEN0 and VCTL\n");
290		- read_from_px_regs(1);
291		- puts("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
292		- set_px_go();
293		- } else
294		- goto my_usage;
295		-
296		- while (1) ; /* Not reached */
297		-
298		- case 'l':
299		- if (argv[2][1] == 'f') {
300		- read_from_px_regs(0);
301		- read_from_px_regs_altbank(0);
302		- /* reset with frequency changed */
303		- val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
304		-
305		- corepll = strfractoint(argv[4]);
306		- val = val + set_px_corepll(corepll);
307		- val = val + set_px_mpxpll(simple_strtoul(argv[5],
308		- NULL, 10));
309		- if (val == 3) {
310		- puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
311		- set_altbank();
312		- read_from_px_regs(1);
313		- read_from_px_regs_altbank(1);
314		- puts("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
315		- set_px_go_with_watchdog();
316		- } else
317		- goto my_usage;
318		-
319		- while (1) ; /* Not reached */
320		-
321		- } else if (argv[2][1] == 'd') {
322		- /*
323		- * Reset from alternate bank without changing
324		- * frequencies but with watchdog timer enabled.
325		- */
326		- read_from_px_regs(0);
327		- read_from_px_regs_altbank(0);
328		- puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
329		- set_altbank();
330		- read_from_px_regs_altbank(1);
331		- puts("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
332		- set_px_go_with_watchdog();
333		- while (1) ; /* Not reached */
334		-
335		- } else {
336		- /*
337		- * Reset from next bank without changing
338		- * frequency and without watchdog timer enabled.
339		- */
340		- read_from_px_regs(0);
341		- read_from_px_regs_altbank(0);
342		- if (argc > 2)
343		- goto my_usage;
344		- puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
345		- set_altbank();
346		- read_from_px_regs_altbank(1);
347		- puts("Resetting board to boot from the other bank....\n");
348		- set_px_go();
349		- }
350		-
351		- default:
352		- goto my_usage;
353		- }
354		-
355		-my_usage:
356		- puts("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
357		- puts(" reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
358		- puts(" reset altbank [wd]\n");
359		- puts("For example: reset cf 40 2.5 10\n");
360		- puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
361		-}
362	255
363	256
364	257	/*
1		-/*
2		- * Copyright 2006 Freescale Semiconductor
3		- * Jeff Brown
4		- * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
5		- *
6		- * See file CREDITS for list of people who contributed to this
7		- * project.
8		- *
9		- * This program is free software; you can redistribute it and/or
10		- * modify it under the terms of the GNU General Public License as
11		- * published by the Free Software Foundation; either version 2 of
12		- * the License, or (at your option) any later version.
13		- *
14		- * This program is distributed in the hope that it will be useful,
15		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
16		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17		- * GNU General Public License for more details.
18		- *
19		- * You should have received a copy of the GNU General Public License
20		- * along with this program; if not, write to the Free Software
21		- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22		- * MA 02111-1307 USA
23		- */
24		-
25		-#include <common.h>
26		-#include <watchdog.h>
27		-#include <command.h>
28		-#include <asm/cache.h>
29		-#include <mpc86xx.h>
30		-
31		-#include "pixis.h"
32		-
33		-
34		-/*
35		- * Per table 27, page 58 of MPC8641HPCN spec.
36		- */
37		-int set_px_sysclk(ulong sysclk)
38		-{
39		- u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
40		-
41		- switch (sysclk) {
42		- case 33:
43		- sysclk_s = 0x04;
44		- sysclk_r = 0x04;
45		- sysclk_v = 0x07;
46		- sysclk_aux = 0x00;
47		- break;
48		- case 40:
49		- sysclk_s = 0x01;
50		- sysclk_r = 0x1F;
51		- sysclk_v = 0x20;
52		- sysclk_aux = 0x01;
53		- break;
54		- case 50:
55		- sysclk_s = 0x01;
56		- sysclk_r = 0x1F;
57		- sysclk_v = 0x2A;
58		- sysclk_aux = 0x02;
59		- break;
60		- case 66:
61		- sysclk_s = 0x01;
62		- sysclk_r = 0x04;
63		- sysclk_v = 0x04;
64		- sysclk_aux = 0x03;
65		- break;
66		- case 83:
67		- sysclk_s = 0x01;
68		- sysclk_r = 0x1F;
69		- sysclk_v = 0x4B;
70		- sysclk_aux = 0x04;
71		- break;
72		- case 100:
73		- sysclk_s = 0x01;
74		- sysclk_r = 0x1F;
75		- sysclk_v = 0x5C;
76		- sysclk_aux = 0x05;
77		- break;
78		- case 134:
79		- sysclk_s = 0x06;
80		- sysclk_r = 0x1F;
81		- sysclk_v = 0x3B;
82		- sysclk_aux = 0x06;
83		- break;
84		- case 166:
85		- sysclk_s = 0x06;
86		- sysclk_r = 0x1F;
87		- sysclk_v = 0x4B;
88		- sysclk_aux = 0x07;
89		- break;
90		- default:
91		- printf("Unsupported SYSCLK frequency.\n");
92		- return 0;
93		- }
94		-
95		- vclkh = (sysclk_s << 5) \| sysclk_r;
96		- vclkl = sysclk_v;
97		-
98		- out8(PIXIS_BASE + PIXIS_VCLKH, vclkh);
99		- out8(PIXIS_BASE + PIXIS_VCLKL, vclkl);
100		-
101		- out8(PIXIS_BASE + PIXIS_AUX, sysclk_aux);
102		-
103		- return 1;
104		-}
105		-
106		-
107		-int set_px_mpxpll(ulong mpxpll)
108		-{
109		- u8 tmp;
110		- u8 val;
111		-
112		- switch (mpxpll) {
113		- case 2:
114		- case 4:
115		- case 6:
116		- case 8:
117		- case 10:
118		- case 12:
119		- case 14:
120		- case 16:
121		- val = (u8) mpxpll;
122		- break;
123		- default:
124		- printf("Unsupported MPXPLL ratio.\n");
125		- return 0;
126		- }
127		-
128		- tmp = in8(PIXIS_BASE + PIXIS_VSPEED1);
129		- tmp = (tmp & 0xF0) \| (val & 0x0F);
130		- out8(PIXIS_BASE + PIXIS_VSPEED1, tmp);
131		-
132		- return 1;
133		-}
134		-
135		-
136		-int set_px_corepll(ulong corepll)
137		-{
138		- u8 tmp;
139		- u8 val;
140		-
141		- switch ((int)corepll) {
142		- case 20:
143		- val = 0x08;
144		- break;
145		- case 25:
146		- val = 0x0C;
147		- break;
148		- case 30:
149		- val = 0x10;
150		- break;
151		- case 35:
152		- val = 0x1C;
153		- break;
154		- case 40:
155		- val = 0x14;
156		- break;
157		- case 45:
158		- val = 0x0E;
159		- break;
160		- default:
161		- printf("Unsupported COREPLL ratio.\n");
162		- return 0;
163		- }
164		-
165		- tmp = in8(PIXIS_BASE + PIXIS_VSPEED0);
166		- tmp = (tmp & 0xE0) \| (val & 0x1F);
167		- out8(PIXIS_BASE + PIXIS_VSPEED0, tmp);
168		-
169		- return 1;
170		-}
171		-
172		-
173		-void read_from_px_regs(int set)
174		-{
175		- u8 mask = 0x1C;
176		- u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN0);
177		-
178		- if (set)
179		- tmp = tmp \| mask;
180		- else
181		- tmp = tmp & ~mask;
182		- out8(PIXIS_BASE + PIXIS_VCFGEN0, tmp);
183		-}
184		-
185		-
186		-void read_from_px_regs_altbank(int set)
187		-{
188		- u8 mask = 0x04;
189		- u8 tmp = in8(PIXIS_BASE + PIXIS_VCFGEN1);
190		-
191		- if (set)
192		- tmp = tmp \| mask;
193		- else
194		- tmp = tmp & ~mask;
195		- out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
196		-}
197		-
198		-
199		-void set_altbank(void)
200		-{
201		- u8 tmp;
202		-
203		- tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
204		- tmp ^= 0x40;
205		-
206		- out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
207		-}
208		-
209		-
210		-void set_px_go(void)
211		-{
212		- u8 tmp;
213		-
214		- tmp = in8(PIXIS_BASE + PIXIS_VCTL);
215		- tmp = tmp & 0x1E;
216		- out8(PIXIS_BASE + PIXIS_VCTL, tmp);
217		-
218		- tmp = in8(PIXIS_BASE + PIXIS_VCTL);
219		- tmp = tmp \| 0x01;
220		- out8(PIXIS_BASE + PIXIS_VCTL, tmp);
221		-}
222		-
223		-
224		-void set_px_go_with_watchdog(void)
225		-{
226		- u8 tmp;
227		-
228		- tmp = in8(PIXIS_BASE + PIXIS_VCTL);
229		- tmp = tmp & 0x1E;
230		- out8(PIXIS_BASE + PIXIS_VCTL, tmp);
231		-
232		- tmp = in8(PIXIS_BASE + PIXIS_VCTL);
233		- tmp = tmp \| 0x09;
234		- out8(PIXIS_BASE + PIXIS_VCTL, tmp);
235		-}
236		-
237		-
238		-int disable_watchdog(cmd_tbl_t cmdtp, int flag, int argc, char argv[])
239		-{
240		- u8 tmp;
241		-
242		- tmp = in8(PIXIS_BASE + PIXIS_VCTL);
243		- tmp = tmp & 0x1E;
244		- out8(PIXIS_BASE + PIXIS_VCTL, tmp);
245		-
246		- /* setting VCTL[WDEN] to 0 to disable watch dog */
247		- tmp = in8(PIXIS_BASE + PIXIS_VCTL);
248		- tmp &= ~0x08;
249		- out8(PIXIS_BASE + PIXIS_VCTL, tmp);
250		-
251		- return 0;
252		-}
253		-
254		-U_BOOT_CMD(
255		- diswd, 1, 0, disable_watchdog,
256		- "diswd - Disable watchdog timer \n",
257		- NULL);
258		-
259		-/*
260		- * This function takes the non-integral cpu:mpx pll ratio
261		- * and converts it to an integer that can be used to assign
262		- * FPGA register values.
263		- * input: strptr i.e. argv[2]
264		- */
265		-
266		-ulong strfractoint(uchar *strptr)
267		-{
268		- int i, j, retval;
269		- int mulconst;
270		- int intarr_len = 0, decarr_len = 0, no_dec = 0;
271		- ulong intval = 0, decval = 0;
272		- uchar intarr[3], decarr[3];
273		-
274		- /* Assign the integer part to intarr[]
275		- * If there is no decimal point i.e.
276		- * if the ratio is an integral value
277		- * simply create the intarr.
278		- */
279		- i = 0;
280		- while (strptr[i] != 46) {
281		- if (strptr[i] == 0) {
282		- no_dec = 1;
283		- break;
284		- }
285		- intarr[i] = strptr[i];
286		- i++;
287		- }
288		-
289		- /* Assign length of integer part to intarr_len. */
290		- intarr_len = i;
291		- intarr[i] = '\0';
292		-
293		- if (no_dec) {
294		- /* Currently needed only for single digit corepll ratios */
295		- mulconst = 10;
296		- decval = 0;
297		- } else {
298		- j = 0;
299		- i++; /* Skipping the decimal point */
300		- while ((strptr[i] > 47) && (strptr[i] < 58)) {
301		- decarr[j] = strptr[i];
302		- i++;
303		- j++;
304		- }
305		-
306		- decarr_len = j;
307		- decarr[j] = '\0';
308		-
309		- mulconst = 1;
310		- for (i = 0; i < decarr_len; i++)
311		- mulconst *= 10;
312		- decval = simple_strtoul(decarr, NULL, 10);
313		- }
314		-
315		- intval = simple_strtoul(intarr, NULL, 10);
316		- intval = intval * mulconst;
317		-
318		- retval = intval + decval;
319		-
320		- return retval;
321		-}
...	...	@@ -32,12 +32,6 @@
32	32	#include <ft_build.h>
33	33	#endif
34	34
35		-#ifdef CONFIG_MPC8641HPCN
36		-extern void mpc8641_reset_board(cmd_tbl_t *cmdtp, int flag,
37		- int argc, char *argv[]);
38		-#endif
39		-
40		-
41	35	int
42	36	checkcpu(void)
43	37	{
...	...	@@ -185,7 +179,7 @@
185	179
186	180	#else /* CONFIG_MPC8641HPCN */
187	181
188		- mpc8641_reset_board(cmdtp, flag, argc, argv);
	182	+ out8(PIXIS_BASE + PIXIS_RST, 0);
189	183
190	184	#endif /* !CONFIG_MPC8641HPCN */
191	185
...	...	@@ -121,4 +121,38 @@
121	121	0xe300_0000 0xe3ff_ffff PCI2/PEX2 IO 16M
122	122	0xfe00_0000 0xfeff_ffff Flash(alternate)16M
123	123	0xff00_0000 0xffff_ffff Flash(boot bank)16M
	124	+
	125	+5. pixis_reset command
	126	+--------------------
	127	+A new command, "pixis_reset", is introduced to reset mpc8641hpcn board
	128	+using the FPGA sequencer. When the board restarts, it has the option
	129	+of using either the current or alternate flash bank as the boot
	130	+image, with or without the watchdog timer enabled, and finally with
	131	+or without frequency changes.
	132	+
	133	+Usage is;
	134	+
	135	+ pixis_reset
	136	+ pixis_reset altbank
	137	+ pixis_reset altbank wd
	138	+ pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
	139	+ pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
	140	+
	141	+Examples;
	142	+
	143	+ /* reset to current bank, like "reset" command */
	144	+ pixis_reset
	145	+
	146	+ /* reset board but use the to alternate flash bank */
	147	+ pixis_reset altbank
	148	+
	149	+ /* reset board, use alternate flash bank with watchdog timer enabled*/
	150	+ pixis_reset altbank wd
	151	+
	152	+ /* reset board to alternate bank with frequency changed.
	153	+ * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
	154	+ */
	155	+ pixis-reset altbank cf 40 2.5 10
	156	+
	157	+Valid clock choices are in the 8641 Reference Manuals.