Eric Lee / smarc-uboot | Embedian Git Server

Commit a832ddba55f79801b6f75b79e96c3f5e1469335a

Authored by Pavel Machek 2014-09-08 20:08:45 +0800

Committed by Marek Vasut 2014-10-06 23:46:49 +0800

Exists in v2017.01-smarct4x and in 37 other branches

arm: socfpga: clock: Add code to read clock configuration

Add the entire bulk of code to read out clock configuration from the SoCFPGA
CPU registers. This is important for MMC, QSPI and UART drivers as otherwise
they cannot determine the frequency of their upstream clock.

Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>

V2: Fixed the L4 MP clock divider and synced the clock code with latest
    rocketboards codebase (thanks Dinh for pointing this out)

Showing 3 changed files with 267 additions and 3 deletions Inline Diff

arch/arm/cpu/armv7/socfpga/clock_manager.c
arch/arm/include/asm/arch-socfpga/clock_manager.h
include/configs/socfpga_cyclone5.h

arch/arm/cpu/armv7/socfpga/clock_manager.c

Diff comments View file @ a832ddb

 /*
  *  Copyright (C) 2013 Altera Corporation <www.altera.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/clock_manager.h>
+DECLARE_GLOBAL_DATA_PTR;
 static const struct socfpga_clock_manager *clock_manager_base =
-		(void *)SOCFPGA_CLKMGR_ADDRESS;
+	(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
 #define CLKMGR_BYPASS_ENABLE	1
 #define CLKMGR_BYPASS_DISABLE	0
 #define CLKMGR_STAT_IDLE	0
 #define CLKMGR_STAT_BUSY	1
 #define CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1		0
 #define CLKMGR_BYPASS_PERPLLSRC_SELECT_INPUT_MUX	1
 #define CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1		0
 #define CLKMGR_BYPASS_SDRPLLSRC_SELECT_INPUT_MUX	1
 #define CLEAR_BGP_EN_PWRDN \
 	(CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
 	CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \
 	CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
 #define VCO_EN_BASE \
 	(CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
 	CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \
 	CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
 static void cm_wait_for_lock(uint32_t mask)
 {
 	register uint32_t inter_val;
 	do {
 		inter_val = readl(&clock_manager_base->inter) & mask;
 	} while (inter_val != mask);
 }
 /* function to poll in the fsm busy bit */
 static void cm_wait_for_fsm(void)
 {
 	while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY)
 		;
 }
 /*
  * function to write the bypass register which requires a poll of the
  * busy bit
  */
 static void cm_write_bypass(uint32_t val)
 {
 	writel(val, &clock_manager_base->bypass);
 	cm_wait_for_fsm();
 }
 /* function to write the ctrl register which requires a poll of the busy bit */
 static void cm_write_ctrl(uint32_t val)
 {
 	writel(val, &clock_manager_base->ctrl);
 	cm_wait_for_fsm();
 }
 /* function to write a clock register that has phase information */
 static void cm_write_with_phase(uint32_t value,
 				uint32_t reg_address, uint32_t mask)
 {
 	/* poll until phase is zero */
 	while (readl(reg_address) & mask)
 		;
 	writel(value, reg_address);
 	while (readl(reg_address) & mask)
 		;
 }
 /*
  * Setup clocks while making no assumptions about previous state of the clocks.
  *
  * Start by being paranoid and gate all sw managed clocks
  * Put all plls in bypass
  * Put all plls VCO registers back to reset value (bandgap power down).
  * Put peripheral and main pll src to reset value to avoid glitch.
  * Delay 5 us.
  * Deassert bandgap power down and set numerator and denominator
  * Start 7 us timer.
  * set internal dividers
  * Wait for 7 us timer.
  * Enable plls
  * Set external dividers while plls are locking
  * Wait for pll lock
  * Assert/deassert outreset all.
  * Take all pll's out of bypass
  * Clear safe mode
  * set source main and peripheral clocks
  * Ungate clocks
  */
 void cm_basic_init(const cm_config_t *cfg)
 {
 	uint32_t start, timeout;
 	/* Start by being paranoid and gate all sw managed clocks */
 	/*
 	 * We need to disable nandclk
 	 * and then do another apb access before disabling
 	 * gatting off the rest of the periperal clocks.
 	 */
 	writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
 		readl(&clock_manager_base->per_pll.en),
 		&clock_manager_base->per_pll.en);
 	/* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
 	writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
 		CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK |
 		CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK |
 		CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
 		CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
 		CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
 		&clock_manager_base->main_pll.en);
 	writel(0, &clock_manager_base->sdr_pll.en);
 	/* now we can gate off the rest of the peripheral clocks */
 	writel(0, &clock_manager_base->per_pll.en);
 	/* Put all plls in bypass */
 	cm_write_bypass(
 		CLKMGR_BYPASS_PERPLLSRC_SET(
 		CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
 		CLKMGR_BYPASS_SDRPLLSRC_SET(
 		CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
 		CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_ENABLE) |
 		CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_ENABLE) |
 		CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_ENABLE));
 	/*
 	 * Put all plls VCO registers back to reset value.
 	 * Some code might have messed with them.
 	 */
 	writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE,
 	       &clock_manager_base->main_pll.vco);
 	writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE,
 	       &clock_manager_base->per_pll.vco);
 	writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE,
 	       &clock_manager_base->sdr_pll.vco);
 	/*
 	 * The clocks to the flash devices and the L4_MAIN clocks can
 	 * glitch when coming out of safe mode if their source values
 	 * are different from their reset value.  So the trick it to
 	 * put them back to their reset state, and change input
 	 * after exiting safe mode but before ungating the clocks.
 	 */
 	writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
 	       &clock_manager_base->per_pll.src);
 	writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
 	       &clock_manager_base->main_pll.l4src);
 	/* read back for the required 5 us delay. */
 	readl(&clock_manager_base->main_pll.vco);
 	readl(&clock_manager_base->per_pll.vco);
 	readl(&clock_manager_base->sdr_pll.vco);
 	/*
 	 * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
 	 * with numerator and denominator.
 	 */
 	writel(cfg->main_vco_base | CLEAR_BGP_EN_PWRDN |
 		CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
 		&clock_manager_base->main_pll.vco);
 	writel(cfg->peri_vco_base | CLEAR_BGP_EN_PWRDN |
 		CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
 		&clock_manager_base->per_pll.vco);
 	writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
 		CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
 		cfg->sdram_vco_base | CLEAR_BGP_EN_PWRDN |
 		CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
 		&clock_manager_base->sdr_pll.vco);
 	/*
 	 * Time starts here
 	 * must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1)
 	 */
 	start = get_timer(0);
 	/* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */
 	timeout = 7;
 	/* main mpu */
 	writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
 	/* main main clock */
 	writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
 	/* main for dbg */
 	writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk);
 	/* main for cfgs2fuser0clk */
 	writel(cfg->cfg2fuser0clk,
 	       &clock_manager_base->main_pll.cfgs2fuser0clk);
 	/* Peri emac0 50 MHz default to RMII */
 	writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk);
 	/* Peri emac1 50 MHz default to RMII */
 	writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk);
 	/* Peri QSPI */
 	writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk);
 	writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
 	/* Peri pernandsdmmcclk */
 	writel(cfg->pernandsdmmcclk,
 	       &clock_manager_base->per_pll.pernandsdmmcclk);
 	/* Peri perbaseclk */
 	writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk);
 	/* Peri s2fuser1clk */
 	writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
 	/* 7 us must have elapsed before we can enable the VCO */
 	while (get_timer(start) < timeout)
 		;
 	/* Enable vco */
 	/* main pll vco */
 	writel(cfg->main_vco_base | VCO_EN_BASE,
 	       &clock_manager_base->main_pll.vco);
 	/* periferal pll */
 	writel(cfg->peri_vco_base | VCO_EN_BASE,
 	       &clock_manager_base->per_pll.vco);
 	/* sdram pll vco */
 	writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
 		CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
 		cfg->sdram_vco_base | VCO_EN_BASE,
 		&clock_manager_base->sdr_pll.vco);
 	/* L3 MP and L3 SP */
 	writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
 	writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv);
 	writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv);
 	/* L4 MP, L4 SP, can0, and can1 */
 	writel(cfg->perdiv, &clock_manager_base->per_pll.div);
 	writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv);
 #define LOCKED_MASK \
 	(CLKMGR_INTER_SDRPLLLOCKED_MASK  | \
 	CLKMGR_INTER_PERPLLLOCKED_MASK  | \
 	CLKMGR_INTER_MAINPLLLOCKED_MASK)
 	cm_wait_for_lock(LOCKED_MASK);
 	/* write the sdram clock counters before toggling outreset all */
 	writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
 	       &clock_manager_base->sdr_pll.ddrdqsclk);
 	writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
 	       &clock_manager_base->sdr_pll.ddr2xdqsclk);
 	writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
 	       &clock_manager_base->sdr_pll.ddrdqclk);
 	writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
 	       &clock_manager_base->sdr_pll.s2fuser2clk);
 	/*
 	 * after locking, but before taking out of bypass
 	 * assert/deassert outresetall
 	 */
 	uint32_t mainvco = readl(&clock_manager_base->main_pll.vco);
 	/* assert main outresetall */
 	writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
 	       &clock_manager_base->main_pll.vco);
 	uint32_t periphvco = readl(&clock_manager_base->per_pll.vco);
 	/* assert pheriph outresetall */
 	writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
 	       &clock_manager_base->per_pll.vco);
 	/* assert sdram outresetall */
 	writel(cfg->sdram_vco_base | VCO_EN_BASE|
 		CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1),
 		&clock_manager_base->sdr_pll.vco);
 	/* deassert main outresetall */
 	writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
 	       &clock_manager_base->main_pll.vco);
 	/* deassert pheriph outresetall */
 	writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
 	       &clock_manager_base->per_pll.vco);
 	/* deassert sdram outresetall */
 	writel(CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
 		cfg->sdram_vco_base | VCO_EN_BASE,
 		&clock_manager_base->sdr_pll.vco);
 	/*
 	 * now that we've toggled outreset all, all the clocks
 	 * are aligned nicely; so we can change any phase.
 	 */
 	cm_write_with_phase(cfg->ddrdqsclk,
 			    (uint32_t)&clock_manager_base->sdr_pll.ddrdqsclk,
 			    CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
 	/* SDRAM DDR2XDQSCLK */
 	cm_write_with_phase(cfg->ddr2xdqsclk,
 			    (uint32_t)&clock_manager_base->sdr_pll.ddr2xdqsclk,
 			    CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
 	cm_write_with_phase(cfg->ddrdqclk,
 			    (uint32_t)&clock_manager_base->sdr_pll.ddrdqclk,
 			    CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
 	cm_write_with_phase(cfg->s2fuser2clk,
 			    (uint32_t)&clock_manager_base->sdr_pll.s2fuser2clk,
 			    CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
 	/* Take all three PLLs out of bypass when safe mode is cleared. */
 	cm_write_bypass(
 		CLKMGR_BYPASS_PERPLLSRC_SET(
 			CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
 		CLKMGR_BYPASS_SDRPLLSRC_SET(
 			CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
 		CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_DISABLE) |
 		CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_DISABLE) |
 		CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_DISABLE));
 	/* clear safe mode */
 	cm_write_ctrl(readl(&clock_manager_base->ctrl) |
 			CLKMGR_CTRL_SAFEMODE_SET(CLKMGR_CTRL_SAFEMODE_MASK));
 	/*
 	 * now that safe mode is clear with clocks gated
 	 * it safe to change the source mux for the flashes the the L4_MAIN
 	 */
 	writel(cfg->persrc, &clock_manager_base->per_pll.src);
 	writel(cfg->l4src, &clock_manager_base->main_pll.l4src);
 	/* Now ungate non-hw-managed clocks */
 	writel(~0, &clock_manager_base->main_pll.en);
 	writel(~0, &clock_manager_base->per_pll.en);
 	writel(~0, &clock_manager_base->sdr_pll.en);
 }
+unsigned long cm_get_mpu_clk_hz(void)
+{
+	uint32_t reg, clock;
+	/* get the main VCO clock */
+	reg = readl(&clock_manager_base->main_pll.vco);
+	clock = CONFIG_HPS_CLK_OSC1_HZ /
+		(CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
+	clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
+	/* get the MPU clock */
+	reg = readl(&clock_manager_base->altera.mpuclk);
+	clock /= (reg + 1);
+	reg = readl(&clock_manager_base->main_pll.mpuclk);
+	clock /= (reg + 1);
+	return clock;
+}
+unsigned long cm_get_sdram_clk_hz(void)
+{
+	uint32_t reg, clock = 0;
+	/* identify SDRAM PLL clock source */
+	reg = readl(&clock_manager_base->sdr_pll.vco);
+	reg = CLKMGR_SDRPLLGRP_VCO_SSRC_GET(reg);
+	if (reg == CLKMGR_VCO_SSRC_EOSC1)
+		clock = CONFIG_HPS_CLK_OSC1_HZ;
+	else if (reg == CLKMGR_VCO_SSRC_EOSC2)
+		clock = CONFIG_HPS_CLK_OSC2_HZ;
+	else if (reg == CLKMGR_VCO_SSRC_F2S)
+		clock = CONFIG_HPS_CLK_F2S_SDR_REF_HZ;
+	/* get the SDRAM VCO clock */
+	reg = readl(&clock_manager_base->sdr_pll.vco);
+	clock /= (CLKMGR_SDRPLLGRP_VCO_DENOM_GET(reg) + 1);
+	clock *= (CLKMGR_SDRPLLGRP_VCO_NUMER_GET(reg) + 1);
+	/* get the SDRAM (DDR_DQS) clock */
+	reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
+	reg = CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_GET(reg);
+	clock /= (reg + 1);
+	return clock;
+}
+unsigned int cm_get_l4_sp_clk_hz(void)
+{
+	uint32_t reg, clock = 0;
+	/* identify the source of L4 SP clock */
+	reg = readl(&clock_manager_base->main_pll.l4src);
+	reg = CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(reg);
+	if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
+		/* get the main VCO clock */
+		reg = readl(&clock_manager_base->main_pll.vco);
+		clock = CONFIG_HPS_CLK_OSC1_HZ /
+			(CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
+		clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
+		/* get the clock prior L4 SP divider (main clk) */
+		reg = readl(&clock_manager_base->altera.mainclk);
+		clock /= (reg + 1);
+		reg = readl(&clock_manager_base->main_pll.mainclk);
+		clock /= (reg + 1);
+	} else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
+		/* identify PER PLL clock source */
+		reg = readl(&clock_manager_base->per_pll.vco);
+		reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg);
+		if (reg == CLKMGR_VCO_SSRC_EOSC1)
+			clock = CONFIG_HPS_CLK_OSC1_HZ;
+		else if (reg == CLKMGR_VCO_SSRC_EOSC2)
+			clock = CONFIG_HPS_CLK_OSC2_HZ;
+		else if (reg == CLKMGR_VCO_SSRC_F2S)
+			clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+		/* get the PER VCO clock */
+		reg = readl(&clock_manager_base->per_pll.vco);
+		clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1);
+		clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1);
+		/* get the clock prior L4 SP divider (periph_base_clk) */
+		reg = readl(&clock_manager_base->per_pll.perbaseclk);
+		clock /= (reg + 1);
+	}
+	/* get the L4 SP clock which supplied to UART */
+	reg = readl(&clock_manager_base->main_pll.maindiv);
+	reg = CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_GET(reg);
+	clock = clock / (1 << reg);
+	return clock;
+}
+unsigned int cm_get_mmc_controller_clk_hz(void)
+{
+	uint32_t reg, clock = 0;
+	/* identify the source of MMC clock */
+	reg = readl(&clock_manager_base->per_pll.src);
+	reg = CLKMGR_PERPLLGRP_SRC_SDMMC_GET(reg);
+	if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
+		clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+	} else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {
+		/* get the main VCO clock */
+		reg = readl(&clock_manager_base->main_pll.vco);
+		clock = CONFIG_HPS_CLK_OSC1_HZ /
+			(CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
+		clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
+		/* get the SDMMC clock */
+		reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);
+		clock /= (reg + 1);
+	} else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
+		/* identify PER PLL clock source */
+		reg = readl(&clock_manager_base->per_pll.vco);
+		reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg);
+		if (reg == CLKMGR_VCO_SSRC_EOSC1)
+			clock = CONFIG_HPS_CLK_OSC1_HZ;
+		else if (reg == CLKMGR_VCO_SSRC_EOSC2)
+			clock = CONFIG_HPS_CLK_OSC2_HZ;
+		else if (reg == CLKMGR_VCO_SSRC_F2S)
+			clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+		/* get the PER VCO clock */
+		reg = readl(&clock_manager_base->per_pll.vco);
+		clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1);
+		clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1);
+		/* get the SDMMC clock */
+		reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);
+		clock /= (reg + 1);
+	}
+	/* further divide by 4 as we have fixed divider at wrapper */
+	clock /= 4;
+	return clock;
+}
+unsigned int cm_get_qspi_controller_clk_hz(void)
+{
+	uint32_t reg, clock = 0;
+	/* identify the source of QSPI clock */
+	reg = readl(&clock_manager_base->per_pll.src);
+	reg = CLKMGR_PERPLLGRP_SRC_QSPI_GET(reg);
+	if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
+		clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+	} else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) {
+		/* get the main VCO clock */
+		reg = readl(&clock_manager_base->main_pll.vco);
+		clock = CONFIG_HPS_CLK_OSC1_HZ /
+			(CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
+		clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
+		/* get the qspi clock */
+		reg = readl(&clock_manager_base->main_pll.mainqspiclk);
+		clock /= (reg + 1);
+	} else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
+		/* identify PER PLL clock source */
+		reg = readl(&clock_manager_base->per_pll.vco);
+		reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg);
+		if (reg == CLKMGR_VCO_SSRC_EOSC1)
+			clock = CONFIG_HPS_CLK_OSC1_HZ;
+		else if (reg == CLKMGR_VCO_SSRC_EOSC2)
+			clock = CONFIG_HPS_CLK_OSC2_HZ;
+		else if (reg == CLKMGR_VCO_SSRC_F2S)
+			clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+		/* get the PER VCO clock */
+		reg = readl(&clock_manager_base->per_pll.vco);
+		clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1);
+		clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1);
+		/* get the qspi clock */
+		reg = readl(&clock_manager_base->per_pll.perqspiclk);
+		clock /= (reg + 1);
+	}
+	return clock;
+}
+static void cm_print_clock_quick_summary(void)
+{
+	printf("MPU       %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
+	printf("DDR       %10ld kHz\n", cm_get_sdram_clk_hz() / 1000);
+	printf("EOSC1       %8d kHz\n", CONFIG_HPS_CLK_OSC1_HZ / 1000);
+	printf("EOSC2       %8d kHz\n", CONFIG_HPS_CLK_OSC2_HZ / 1000);
+	printf("F2S_SDR_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_SDR_REF_HZ / 1000);
+	printf("F2S_PER_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_PER_REF_HZ / 1000);
+	printf("MMC         %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
+	printf("QSPI        %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
+	printf("UART        %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
+}
+int set_cpu_clk_info(void)
+{
+	/* Calculate the clock frequencies required for drivers */
+	cm_get_l4_sp_clk_hz();
+	cm_get_mmc_controller_clk_hz();
+	gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
+	gd->bd->bi_dsp_freq = 0;
+	gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
+	return 0;
+}
+int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	cm_print_clock_quick_summary();
+	return 0;
+}
+U_BOOT_CMD(
+	clocks,	CONFIG_SYS_MAXARGS, 1, do_showclocks,
+	"display clocks",
+	""
+);

arch/arm/include/asm/arch-socfpga/clock_manager.h

Diff comments View file @ a832ddb

 /*
  *  Copyright (C) 2013 Altera Corporation <www.altera.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef	_CLOCK_MANAGER_H_
 #define	_CLOCK_MANAGER_H_
+#ifndef __ASSEMBLER__
+/* Clock speed accessors */
+unsigned long cm_get_mpu_clk_hz(void);
+unsigned long cm_get_sdram_clk_hz(void);
+unsigned int cm_get_l4_sp_clk_hz(void);
+unsigned int cm_get_mmc_controller_clk_hz(void);
+unsigned int cm_get_qspi_controller_clk_hz(void);
+#endif
 typedef struct {
 	/* main group */
 	uint32_t main_vco_base;
 	uint32_t mpuclk;
 	uint32_t mainclk;
 	uint32_t dbgatclk;
 	uint32_t mainqspiclk;
 	uint32_t mainnandsdmmcclk;
 	uint32_t cfg2fuser0clk;
 	uint32_t maindiv;
 	uint32_t dbgdiv;
 	uint32_t tracediv;
 	uint32_t l4src;
 	/* peripheral group */
 	uint32_t peri_vco_base;
 	uint32_t emac0clk;
 	uint32_t emac1clk;
 	uint32_t perqspiclk;
 	uint32_t pernandsdmmcclk;
 	uint32_t perbaseclk;
 	uint32_t s2fuser1clk;
 	uint32_t perdiv;
 	uint32_t gpiodiv;
 	uint32_t persrc;
 	/* sdram pll group */
 	uint32_t sdram_vco_base;
 	uint32_t ddrdqsclk;
 	uint32_t ddr2xdqsclk;
 	uint32_t ddrdqclk;
 	uint32_t s2fuser2clk;
 } cm_config_t;
 extern void cm_basic_init(const cm_config_t *cfg);
 struct socfpga_clock_manager_main_pll {
 	u32	vco;
 	u32	misc;
 	u32	mpuclk;
 	u32	mainclk;
 	u32	dbgatclk;
 	u32	mainqspiclk;
 	u32	mainnandsdmmcclk;
 	u32	cfgs2fuser0clk;
 	u32	en;
 	u32	maindiv;
 	u32	dbgdiv;
 	u32	tracediv;
 	u32	l4src;
 	u32	stat;
 	u32	_pad_0x38_0x40[2];
 };
 struct socfpga_clock_manager_per_pll {
 	u32	vco;
 	u32	misc;
 	u32	emac0clk;
 	u32	emac1clk;
 	u32	perqspiclk;
 	u32	pernandsdmmcclk;
 	u32	perbaseclk;
 	u32	s2fuser1clk;
 	u32	en;
 	u32	div;
 	u32	gpiodiv;
 	u32	src;
 	u32	stat;
 	u32	_pad_0x34_0x40[3];
 };
 struct socfpga_clock_manager_sdr_pll {
 	u32	vco;
 	u32	ctrl;
 	u32	ddrdqsclk;
 	u32	ddr2xdqsclk;
 	u32	ddrdqclk;
 	u32	s2fuser2clk;
 	u32	en;
 	u32	stat;
 };
+struct socfpga_clock_manager_altera {
+	u32	mpuclk;
+	u32	mainclk;
+};
 struct socfpga_clock_manager {
 	u32	ctrl;
 	u32	bypass;
 	u32	inter;
 	u32	intren;
 	u32	dbctrl;
 	u32	stat;
 	u32	_pad_0x18_0x3f[10];
 	struct socfpga_clock_manager_main_pll main_pll;
 	struct socfpga_clock_manager_per_pll per_pll;
 	struct socfpga_clock_manager_sdr_pll sdr_pll;
-	u32	_pad_0xe0_0x200[72];
+	struct socfpga_clock_manager_altera altera;
+	u32	_pad_0xe8_0x200[70];
 };
 #define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001
 #define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) << 0) & 0x00000001)
 #define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) << 0) & 0x00000001)
 #define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) << 4) & 0x00000010)
 #define CLKMGR_BYPASS_PERPLL_SET(x) (((x) << 3) & 0x00000008)
 #define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) << 2) & 0x00000004)
 #define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) << 1) & 0x00000002)
 #define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040
 #define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080
 #define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100
 /* Main PLL */
 #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001)
+#define CLKMGR_MAINPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16)
 #define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
 #define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002)
+#define CLKMGR_MAINPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3)
 #define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
 #define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
 #define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004)
 #define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
 #define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
 #define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
 #define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
 #define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
 #define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
 #define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
 #define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
 #define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010
 #define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020
 #define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080
 #define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040
 #define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004
 #define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200
 #define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003)
 #define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c)
 #define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070)
-#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x)  (((x) << 7) & 0x00000380)
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_GET(x) (((x) & 0x00000380) >> 7)
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x) (((x) << 7) & 0x00000380)
 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003)
 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c)
 #define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007)
 #define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001)
+#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(x) (((x) & 0x00000002) >> 1)
 #define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002)
 #define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
+#define CLKMGR_L4_SP_CLK_SRC_MAINPLL	0x0
+#define CLKMGR_L4_SP_CLK_SRC_PERPLL	0x1
 /* Per PLL */
+#define CLKMGR_PERPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16)
 #define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
+#define CLKMGR_PERPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3)
 #define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
 #define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
 #define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000)
 #define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
 #define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
+#define CLKMGR_PERPLLGRP_VCO_SSRC_GET(x) (((x) & 0x00c00000) >> 22)
+#define CLKMGR_VCO_SSRC_EOSC1		0x0
+#define CLKMGR_VCO_SSRC_EOSC2		0x1
+#define CLKMGR_VCO_SSRC_F2S		0x2
 #define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
 #define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
 #define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
 #define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
 #define CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
 #define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
 #define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400
 #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100
 #define CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(x) (((x) << 6) & 0x000001c0)
 #define CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(x) (((x) << 9) & 0x00000e00)
 #define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
 #define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
 #define CLKMGR_PERPLLGRP_DIV_USBCLK_SET(x) (((x) << 0) & 0x00000007)
 #define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff)
 #define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c)
+#define CLKMGR_PERPLLGRP_SRC_QSPI_GET(x) (((x) & 0x00000030) >> 4)
 #define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030)
 #define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
+#define CLKMGR_PERPLLGRP_SRC_SDMMC_GET(x) (((x) & 0x00000003) >> 0)
 #define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003)
+#define CLKMGR_SDMMC_CLK_SRC_F2S	0x0
+#define CLKMGR_SDMMC_CLK_SRC_MAIN	0x1
+#define CLKMGR_SDMMC_CLK_SRC_PER	0x2
+#define CLKMGR_QSPI_CLK_SRC_F2S		0x0
+#define CLKMGR_QSPI_CLK_SRC_MAIN	0x1
+#define CLKMGR_QSPI_CLK_SRC_PER		0x2
 /* SDR PLL */
+#define CLKMGR_SDRPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16)
 #define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
+#define CLKMGR_SDRPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3)
 #define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
 #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
 #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
 #define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000
 #define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000)
 #define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
 #define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
+#define CLKMGR_SDRPLLGRP_VCO_SSRC_GET(x) (((x) & 0x00c00000) >> 22)
 #define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000)
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_GET(x) (((x) & 0x000001ff) >> 0)
 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00
 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff
 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00
 #define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
 #define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff
 #define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
 #define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00
 #define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff
 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00
 #define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
 #define MAIN_VCO_BASE \
 	(CLKMGR_MAINPLLGRP_VCO_DENOM_SET(CONFIG_HPS_MAINPLLGRP_VCO_DENOM) | \
 	CLKMGR_MAINPLLGRP_VCO_NUMER_SET(CONFIG_HPS_MAINPLLGRP_VCO_NUMER))
 #define PERI_VCO_BASE \
 	(CLKMGR_PERPLLGRP_VCO_PSRC_SET(CONFIG_HPS_PERPLLGRP_VCO_PSRC) | \
 	CLKMGR_PERPLLGRP_VCO_DENOM_SET(CONFIG_HPS_PERPLLGRP_VCO_DENOM) | \
 	CLKMGR_PERPLLGRP_VCO_NUMER_SET(CONFIG_HPS_PERPLLGRP_VCO_NUMER))
 #define SDR_VCO_BASE \
 	(CLKMGR_SDRPLLGRP_VCO_SSRC_SET(CONFIG_HPS_SDRPLLGRP_VCO_SSRC) | \
 	CLKMGR_SDRPLLGRP_VCO_DENOM_SET(CONFIG_HPS_SDRPLLGRP_VCO_DENOM) | \
 	CLKMGR_SDRPLLGRP_VCO_NUMER_SET(CONFIG_HPS_SDRPLLGRP_VCO_NUMER))
 #endif /* _CLOCK_MANAGER_H_ */

include/configs/socfpga_cyclone5.h

Diff comments View file @ a832ddb

 /*
  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 #include <asm/arch/socfpga_base_addrs.h>
 #include "../../board/altera/socfpga/pinmux_config.h"
 #include "../../board/altera/socfpga/iocsr_config.h"
 #include "../../board/altera/socfpga/pll_config.h"
 /*
  * High level configuration
  */
 /* Virtual target or real hardware */
 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
 #define CONFIG_ARMV7
 #define CONFIG_SYS_DCACHE_OFF
 #undef CONFIG_USE_IRQ
 #define CONFIG_MISC_INIT_R
 #define CONFIG_SINGLE_BOOTLOADER
 #define CONFIG_SOCFPGA
+#define CONFIG_CLOCKS
 /* base address for .text section */
 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 #define CONFIG_SYS_TEXT_BASE		0x08000040
 #else
 #define CONFIG_SYS_TEXT_BASE		0x01000040
 #endif
 #define CONFIG_SYS_LOAD_ADDR		0x7fc0
 /* Console I/O Buffer Size */
 #define CONFIG_SYS_CBSIZE		256
 /* Monitor Command Prompt */
 #define CONFIG_SYS_PROMPT		"SOCFPGA_CYCLONE5 # "
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)
 /*
  * Display CPU and Board Info
  */
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 /*
  * Enable early stage initialization at C environment
  */
 #define CONFIG_BOARD_EARLY_INIT_F
 /* flat device tree */
 #define CONFIG_OF_LIBFDT
 /* skip updating the FDT blob */
 #define CONFIG_FDT_BLOB_SKIP_UPDATE
 /* Initial Memory map size for Linux, minus 4k alignment for DFT blob */
 #define CONFIG_SYS_BOOTMAPSZ		((256*1024*1024) - (4*1024))
 #define CONFIG_SPL_RAM_DEVICE
 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
 #define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start))
 #define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
 /*
  * Memory allocation (MALLOC)
  */
 /* Room required on the stack for the environment data */
 #define CONFIG_ENV_SIZE			1024
 /* Size of DRAM reserved for malloc() use */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
 /* SP location before relocation, must use scratch RAM */
 #define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
 /* Reserving 0x100 space at back of scratch RAM for debug info */
 #define CONFIG_SYS_INIT_RAM_SIZE	(0x10000 - 0x100)
 /* Stack pointer prior relocation, must situated at on-chip RAM */
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
 					 CONFIG_SYS_INIT_RAM_SIZE - \
 					 GENERATED_GBL_DATA_SIZE)
 /*
  * Command line configuration.
  */
 #define CONFIG_SYS_NO_FLASH
 #include <config_cmd_default.h>
 /* FAT file system support */
 #define CONFIG_CMD_FAT
 /*
  * Misc
  */
 #define CONFIG_DOS_PARTITION            1
 #ifdef CONFIG_SPL_BUILD
 #undef CONFIG_PARTITIONS
 #endif
 /*
  * Environment setup
  */
 /* Delay before automatically booting the default image */
 #define CONFIG_BOOTDELAY		3
 /* Enable auto completion of commands using TAB */
 #define CONFIG_AUTO_COMPLETE
 /* use "hush" command parser */
 #define CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_CMD_RUN
 #define CONFIG_BOOTCOMMAND "run ramboot"
 /*
  * arguments passed to the bootm command. The value of
  * CONFIG_BOOTARGS goes into the environment value "bootargs".
  * Do note the value will overide also the chosen node in FDT blob.
  */
 #define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0"
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"verify=n\0" \
 	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
 	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
 		"bootm ${loadaddr} - ${fdt_addr}\0" \
 	"bootimage=uImage\0" \
 	"fdt_addr=100\0" \
 	"fsloadcmd=ext2load\0" \
 		"bootm ${loadaddr} - ${fdt_addr}\0" \
 	"qspiroot=/dev/mtdblock0\0" \
 	"qspirootfstype=jffs2\0" \
 	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
 		" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
 		"bootm ${loadaddr} - ${fdt_addr}\0"
 /* using environment setting for stdin, stdout, stderr */
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 /* Enable the call to overwrite_console() */
 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 /* Enable overwrite of previous console environment settings */
 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
 /* max number of command args	 */
 #define CONFIG_SYS_MAXARGS		16
 /*
  * Hardware drivers
  */
 /*
  * SDRAM Memory Map
  */
 /* We have 1 bank of DRAM */
 #define CONFIG_NR_DRAM_BANKS		1
 /* SDRAM Bank #1 */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
 /* SDRAM memory size */
 #define PHYS_SDRAM_1_SIZE		0x40000000
 #define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_MEMTEST_START	0x00000000
 #define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE
 /*
  * NS16550 Configuration
  */
 #define UART0_BASE			SOCFPGA_UART0_ADDRESS
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	-4
 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
 #define CONFIG_CONS_INDEX               1
 #define CONFIG_SYS_NS16550_COM1		UART0_BASE
 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 #define V_NS16550_CLK			1000000
 #else
 #define V_NS16550_CLK			100000000
 #endif
 #define CONFIG_BAUDRATE			115200
 /*
  * FLASH
  */
 #define CONFIG_SYS_NO_FLASH
 /*
  * L4 OSC1 Timer 0
  */
 /* This timer use eosc1 where the clock frequency is fixed
  * throughout any condition */
 #define CONFIG_SYS_TIMERBASE		SOCFPGA_OSC1TIMER0_ADDRESS
 /* reload value when timer count to zero */
 #define TIMER_LOAD_VAL			0xFFFFFFFF
 /* Timer info */
 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 #define CONFIG_SYS_TIMER_RATE		2400000
 #else
 #define CONFIG_SYS_TIMER_RATE		25000000
 #endif
 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 #define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
 #define CONFIG_ENV_IS_NOWHERE
 /*
  * network support
  */
 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
 #define CONFIG_DESIGNWARE_ETH          1
 #endif
 #ifdef CONFIG_DESIGNWARE_ETH
 #define CONFIG_EMAC0_BASE              SOCFPGA_EMAC0_ADDRESS
 #define CONFIG_EMAC1_BASE              SOCFPGA_EMAC1_ADDRESS
 /* console support for network */
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_PING
 /* designware */
 #define CONFIG_NET_MULTI
 #define CONFIG_DW_ALTDESCRIPTOR
 #define CONFIG_MII
 #define CONFIG_PHY_GIGE
 #define CONFIG_DW_AUTONEG
 #define CONFIG_AUTONEG_TIMEOUT         (15 * CONFIG_SYS_HZ)
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_MICREL
 #define CONFIG_PHY_MICREL_KSZ9021
 /* EMAC controller and PHY used */
 #define CONFIG_EMAC_BASE               CONFIG_EMAC1_BASE
 #define CONFIG_EPHY_PHY_ADDR           CONFIG_EPHY1_PHY_ADDR
 #define CONFIG_PHY_INTERFACE_MODE      PHY_INTERFACE_MODE_RGMII
 #endif /* CONFIG_DESIGNWARE_ETH */
 /*
  * L4 Watchdog
  */
 #define CONFIG_HW_WATCHDOG
 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS	2000
 #define CONFIG_DESIGNWARE_WATCHDOG
 #define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
 /* Clocks source frequency to watchdog timer */
 #define CONFIG_DW_WDT_CLOCK_KHZ		25000
 /*
  * SPL "Second Program Loader" aka Initial Software
  */
 /* Enable building of SPL globally */
 #define CONFIG_SPL_FRAMEWORK
 /* TEXT_BASE for linking the SPL binary */
 #define CONFIG_SPL_TEXT_BASE		0xFFFF0000
 /* Stack size for SPL */
 #define CONFIG_SPL_STACK_SIZE		(4 * 1024)
 /* MALLOC size for SPL */
 #define CONFIG_SPL_MALLOC_SIZE		(5 * 1024)
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_BOARD_INIT
 #define CHUNKSZ_CRC32			(1 * 1024)
 #define CONFIG_CRC32_VERIFY
 /* Linker script for SPL */
 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
 /* Support for common/libcommon.o in SPL binary */
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 /* Support for lib/libgeneric.o in SPL binary */
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 /* Support for watchdog */
 #define CONFIG_SPL_WATCHDOG_SUPPORT
 #endif	/* __CONFIG_H */