arm: socfpga: clock: Add code to read clock configuration

Add the entire bulk of code to read out clock configuration from the SoCFPGA CPU registers. This is important for MMC, QSPI and UART drivers as otherwise they cannot determine the frequency of their upstream clock. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> V2: Fixed the L4 MP clock divider and synced the clock code with latest rocketboards codebase (thanks Dinh for pointing this out)

arm: socfpga: clock: Add code to read clock configuration
Add the entire bulk of code to read out clock configuration from the SoCFPGA CPU registers. This is important for MMC, QSPI and UART drivers as otherwise they cannot determine the frequency of their upstream clock. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> V2: Fixed the L4 MP clock divider and synced the clock code with latest rocketboards codebase (thanks Dinh for pointing this out)
Pavel Machek · Marek Vasut
1 parent 0911af00b0
Showing 3 changed files with 267 additions and 3 deletions Side-by-side Diff
arch/arm/cpu/armv7/socfpga/clock_manager.c
arch/arm/include/asm/arch-socfpga/clock_manager.h
include/configs/socfpga_cyclone5.h
@@ -8,8 +8,10 @@
 #include <asm/io.h>
 #include <asm/arch/clock_manager.h>
  
+DECLARE_GLOBAL_DATA_PTR;
+
 static const struct socfpga_clock_manager *clock_manager_base =
-		(void *)SOCFPGA_CLKMGR_ADDRESS;
+	(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
  
 #define CLKMGR_BYPASS_ENABLE	1
 #define CLKMGR_BYPASS_DISABLE	0
@@ -358,4 +360,226 @@
 	writel(~0, &clock_manager_base->per_pll.en);
 	writel(~0, &clock_manager_base->sdr_pll.en);
 }
+
+unsigned long cm_get_mpu_clk_hz(void)
+{
+	uint32_t reg, clock;
+
+	/* get the main VCO clock */
+	reg = readl(&clock_manager_base->main_pll.vco);
+	clock = CONFIG_HPS_CLK_OSC1_HZ /
+		(CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
+	clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
+
+	/* get the MPU clock */
+	reg = readl(&clock_manager_base->altera.mpuclk);
+	clock /= (reg + 1);
+	reg = readl(&clock_manager_base->main_pll.mpuclk);
+	clock /= (reg + 1);
+	return clock;
+}
+
+unsigned long cm_get_sdram_clk_hz(void)
+{
+	uint32_t reg, clock = 0;
+
+	/* identify SDRAM PLL clock source */
+	reg = readl(&clock_manager_base->sdr_pll.vco);
+	reg = CLKMGR_SDRPLLGRP_VCO_SSRC_GET(reg);
+	if (reg == CLKMGR_VCO_SSRC_EOSC1)
+		clock = CONFIG_HPS_CLK_OSC1_HZ;
+	else if (reg == CLKMGR_VCO_SSRC_EOSC2)
+		clock = CONFIG_HPS_CLK_OSC2_HZ;
+	else if (reg == CLKMGR_VCO_SSRC_F2S)
+		clock = CONFIG_HPS_CLK_F2S_SDR_REF_HZ;
+
+	/* get the SDRAM VCO clock */
+	reg = readl(&clock_manager_base->sdr_pll.vco);
+	clock /= (CLKMGR_SDRPLLGRP_VCO_DENOM_GET(reg) + 1);
+	clock *= (CLKMGR_SDRPLLGRP_VCO_NUMER_GET(reg) + 1);
+
+	/* get the SDRAM (DDR_DQS) clock */
+	reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
+	reg = CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_GET(reg);
+	clock /= (reg + 1);
+
+	return clock;
+}
+
+unsigned int cm_get_l4_sp_clk_hz(void)
+{
+	uint32_t reg, clock = 0;
+
+	/* identify the source of L4 SP clock */
+	reg = readl(&clock_manager_base->main_pll.l4src);
+	reg = CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(reg);
+
+	if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
+		/* get the main VCO clock */
+		reg = readl(&clock_manager_base->main_pll.vco);
+		clock = CONFIG_HPS_CLK_OSC1_HZ /
+			(CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
+		clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
+
+		/* get the clock prior L4 SP divider (main clk) */
+		reg = readl(&clock_manager_base->altera.mainclk);
+		clock /= (reg + 1);
+		reg = readl(&clock_manager_base->main_pll.mainclk);
+		clock /= (reg + 1);
+	} else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
+		/* identify PER PLL clock source */
+		reg = readl(&clock_manager_base->per_pll.vco);
+		reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg);
+		if (reg == CLKMGR_VCO_SSRC_EOSC1)
+			clock = CONFIG_HPS_CLK_OSC1_HZ;
+		else if (reg == CLKMGR_VCO_SSRC_EOSC2)
+			clock = CONFIG_HPS_CLK_OSC2_HZ;
+		else if (reg == CLKMGR_VCO_SSRC_F2S)
+			clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+
+		/* get the PER VCO clock */
+		reg = readl(&clock_manager_base->per_pll.vco);
+		clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1);
+		clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1);
+
+		/* get the clock prior L4 SP divider (periph_base_clk) */
+		reg = readl(&clock_manager_base->per_pll.perbaseclk);
+		clock /= (reg + 1);
+	}
+
+	/* get the L4 SP clock which supplied to UART */
+	reg = readl(&clock_manager_base->main_pll.maindiv);
+	reg = CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_GET(reg);
+	clock = clock / (1 << reg);
+
+	return clock;
+}
+
+unsigned int cm_get_mmc_controller_clk_hz(void)
+{
+	uint32_t reg, clock = 0;
+
+	/* identify the source of MMC clock */
+	reg = readl(&clock_manager_base->per_pll.src);
+	reg = CLKMGR_PERPLLGRP_SRC_SDMMC_GET(reg);
+
+	if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
+		clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+	} else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {
+		/* get the main VCO clock */
+		reg = readl(&clock_manager_base->main_pll.vco);
+		clock = CONFIG_HPS_CLK_OSC1_HZ /
+			(CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
+		clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
+
+		/* get the SDMMC clock */
+		reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);
+		clock /= (reg + 1);
+	} else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
+		/* identify PER PLL clock source */
+		reg = readl(&clock_manager_base->per_pll.vco);
+		reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg);
+		if (reg == CLKMGR_VCO_SSRC_EOSC1)
+			clock = CONFIG_HPS_CLK_OSC1_HZ;
+		else if (reg == CLKMGR_VCO_SSRC_EOSC2)
+			clock = CONFIG_HPS_CLK_OSC2_HZ;
+		else if (reg == CLKMGR_VCO_SSRC_F2S)
+			clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+
+		/* get the PER VCO clock */
+		reg = readl(&clock_manager_base->per_pll.vco);
+		clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1);
+		clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1);
+
+		/* get the SDMMC clock */
+		reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);
+		clock /= (reg + 1);
+	}
+
+	/* further divide by 4 as we have fixed divider at wrapper */
+	clock /= 4;
+	return clock;
+}
+
+unsigned int cm_get_qspi_controller_clk_hz(void)
+{
+	uint32_t reg, clock = 0;
+
+	/* identify the source of QSPI clock */
+	reg = readl(&clock_manager_base->per_pll.src);
+	reg = CLKMGR_PERPLLGRP_SRC_QSPI_GET(reg);
+
+	if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
+		clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+	} else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) {
+		/* get the main VCO clock */
+		reg = readl(&clock_manager_base->main_pll.vco);
+		clock = CONFIG_HPS_CLK_OSC1_HZ /
+			(CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
+		clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
+
+		/* get the qspi clock */
+		reg = readl(&clock_manager_base->main_pll.mainqspiclk);
+		clock /= (reg + 1);
+	} else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
+		/* identify PER PLL clock source */
+		reg = readl(&clock_manager_base->per_pll.vco);
+		reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg);
+		if (reg == CLKMGR_VCO_SSRC_EOSC1)
+			clock = CONFIG_HPS_CLK_OSC1_HZ;
+		else if (reg == CLKMGR_VCO_SSRC_EOSC2)
+			clock = CONFIG_HPS_CLK_OSC2_HZ;
+		else if (reg == CLKMGR_VCO_SSRC_F2S)
+			clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+
+		/* get the PER VCO clock */
+		reg = readl(&clock_manager_base->per_pll.vco);
+		clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1);
+		clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1);
+
+		/* get the qspi clock */
+		reg = readl(&clock_manager_base->per_pll.perqspiclk);
+		clock /= (reg + 1);
+	}
+
+	return clock;
+}
+
+static void cm_print_clock_quick_summary(void)
+{
+	printf("MPU       %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
+	printf("DDR       %10ld kHz\n", cm_get_sdram_clk_hz() / 1000);
+	printf("EOSC1       %8d kHz\n", CONFIG_HPS_CLK_OSC1_HZ / 1000);
+	printf("EOSC2       %8d kHz\n", CONFIG_HPS_CLK_OSC2_HZ / 1000);
+	printf("F2S_SDR_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_SDR_REF_HZ / 1000);
+	printf("F2S_PER_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_PER_REF_HZ / 1000);
+	printf("MMC         %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
+	printf("QSPI        %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
+	printf("UART        %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
+}
+
+int set_cpu_clk_info(void)
+{
+	/* Calculate the clock frequencies required for drivers */
+	cm_get_l4_sp_clk_hz();
+	cm_get_mmc_controller_clk_hz();
+
+	gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
+	gd->bd->bi_dsp_freq = 0;
+	gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
+
+	return 0;
+}
+
+int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	cm_print_clock_quick_summary();
+	return 0;
+}
+
+U_BOOT_CMD(
+	clocks,	CONFIG_SYS_MAXARGS, 1, do_showclocks,
+	"display clocks",
+	""
+);
@@ -7,6 +7,15 @@
 #ifndef	_CLOCK_MANAGER_H_
 #define	_CLOCK_MANAGER_H_
  
+#ifndef __ASSEMBLER__
+/* Clock speed accessors */
+unsigned long cm_get_mpu_clk_hz(void);
+unsigned long cm_get_sdram_clk_hz(void);
+unsigned int cm_get_l4_sp_clk_hz(void);
+unsigned int cm_get_mmc_controller_clk_hz(void);
+unsigned int cm_get_qspi_controller_clk_hz(void);
+#endif
+
 typedef struct {
 	/* main group */
 	uint32_t main_vco_base;
@@ -89,6 +98,11 @@
 	u32	stat;
 };
  
+struct socfpga_clock_manager_altera {
+	u32	mpuclk;
+	u32	mainclk;
+};
+
 struct socfpga_clock_manager {
 	u32	ctrl;
 	u32	bypass;
@@ -100,7 +114,8 @@
 	struct socfpga_clock_manager_main_pll main_pll;
 	struct socfpga_clock_manager_per_pll per_pll;
 	struct socfpga_clock_manager_sdr_pll sdr_pll;
-	u32	_pad_0xe0_0x200[72];
+	struct socfpga_clock_manager_altera altera;
+	u32	_pad_0xe8_0x200[70];
 };
  
 #define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001
  
@@ -118,8 +133,10 @@
  
 /* Main PLL */
 #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001)
+#define CLKMGR_MAINPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16)
 #define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
 #define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002)
+#define CLKMGR_MAINPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3)
 #define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
 #define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
 #define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004)
@@ -148,7 +165,8 @@
 #define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003)
 #define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c)
 #define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070)
-#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x)  (((x) << 7) & 0x00000380)
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_GET(x) (((x) & 0x00000380) >> 7)
+#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x) (((x) << 7) & 0x00000380)
  
 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003)
 #define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c)
  
  
  
  
@@ -156,16 +174,25 @@
 #define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007)
  
 #define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001)
+#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(x) (((x) & 0x00000002) >> 1)
 #define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002)
 #define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
+#define CLKMGR_L4_SP_CLK_SRC_MAINPLL	0x0
+#define CLKMGR_L4_SP_CLK_SRC_PERPLL	0x1
  
 /* Per PLL */
+#define CLKMGR_PERPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16)
 #define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
+#define CLKMGR_PERPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3)
 #define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
 #define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
 #define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000)
 #define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
 #define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
+#define CLKMGR_PERPLLGRP_VCO_SSRC_GET(x) (((x) & 0x00c00000) >> 22)
+#define CLKMGR_VCO_SSRC_EOSC1		0x0
+#define CLKMGR_VCO_SSRC_EOSC2		0x1
+#define CLKMGR_VCO_SSRC_F2S		0x2
  
 #define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
  
  
  
  
  
@@ -191,12 +218,22 @@
 #define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff)
  
 #define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c)
+#define CLKMGR_PERPLLGRP_SRC_QSPI_GET(x) (((x) & 0x00000030) >> 4)
 #define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030)
 #define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
+#define CLKMGR_PERPLLGRP_SRC_SDMMC_GET(x) (((x) & 0x00000003) >> 0)
 #define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003)
+#define CLKMGR_SDMMC_CLK_SRC_F2S	0x0
+#define CLKMGR_SDMMC_CLK_SRC_MAIN	0x1
+#define CLKMGR_SDMMC_CLK_SRC_PER	0x2
+#define CLKMGR_QSPI_CLK_SRC_F2S		0x0
+#define CLKMGR_QSPI_CLK_SRC_MAIN	0x1
+#define CLKMGR_QSPI_CLK_SRC_PER		0x2
  
 /* SDR PLL */
+#define CLKMGR_SDRPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16)
 #define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
+#define CLKMGR_SDRPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3)
 #define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
 #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
 #define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
  
@@ -204,8 +241,10 @@
 #define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000)
 #define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
 #define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
+#define CLKMGR_SDRPLLGRP_VCO_SSRC_GET(x) (((x) & 0x00c00000) >> 22)
 #define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000)
  
+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_GET(x) (((x) & 0x000001ff) >> 0)
 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
 #define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00
@@ -24,6 +24,7 @@
 #define CONFIG_MISC_INIT_R
 #define CONFIG_SINGLE_BOOTLOADER
 #define CONFIG_SOCFPGA
+#define CONFIG_CLOCKS
  
 /* base address for .text section */
 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
...	...	@@ -8,8 +8,10 @@
8	8	#include <asm/io.h>
9	9	#include <asm/arch/clock_manager.h>
10	10
	11	+DECLARE_GLOBAL_DATA_PTR;
	12	+
11	13	static const struct socfpga_clock_manager *clock_manager_base =
12		- (void *)SOCFPGA_CLKMGR_ADDRESS;
	14	+ (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
13	15
14	16	#define CLKMGR_BYPASS_ENABLE 1
15	17	#define CLKMGR_BYPASS_DISABLE 0
...	...	@@ -358,4 +360,226 @@
358	360	writel(~0, &clock_manager_base->per_pll.en);
359	361	writel(~0, &clock_manager_base->sdr_pll.en);
360	362	}
	363	+
	364	+unsigned long cm_get_mpu_clk_hz(void)
	365	+{
	366	+ uint32_t reg, clock;
	367	+
	368	+ /* get the main VCO clock */
	369	+ reg = readl(&clock_manager_base->main_pll.vco);
	370	+ clock = CONFIG_HPS_CLK_OSC1_HZ /
	371	+ (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
	372	+ clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
	373	+
	374	+ /* get the MPU clock */
	375	+ reg = readl(&clock_manager_base->altera.mpuclk);
	376	+ clock /= (reg + 1);
	377	+ reg = readl(&clock_manager_base->main_pll.mpuclk);
	378	+ clock /= (reg + 1);
	379	+ return clock;
	380	+}
	381	+
	382	+unsigned long cm_get_sdram_clk_hz(void)
	383	+{
	384	+ uint32_t reg, clock = 0;
	385	+
	386	+ /* identify SDRAM PLL clock source */
	387	+ reg = readl(&clock_manager_base->sdr_pll.vco);
	388	+ reg = CLKMGR_SDRPLLGRP_VCO_SSRC_GET(reg);
	389	+ if (reg == CLKMGR_VCO_SSRC_EOSC1)
	390	+ clock = CONFIG_HPS_CLK_OSC1_HZ;
	391	+ else if (reg == CLKMGR_VCO_SSRC_EOSC2)
	392	+ clock = CONFIG_HPS_CLK_OSC2_HZ;
	393	+ else if (reg == CLKMGR_VCO_SSRC_F2S)
	394	+ clock = CONFIG_HPS_CLK_F2S_SDR_REF_HZ;
	395	+
	396	+ /* get the SDRAM VCO clock */
	397	+ reg = readl(&clock_manager_base->sdr_pll.vco);
	398	+ clock /= (CLKMGR_SDRPLLGRP_VCO_DENOM_GET(reg) + 1);
	399	+ clock *= (CLKMGR_SDRPLLGRP_VCO_NUMER_GET(reg) + 1);
	400	+
	401	+ /* get the SDRAM (DDR_DQS) clock */
	402	+ reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
	403	+ reg = CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_GET(reg);
	404	+ clock /= (reg + 1);
	405	+
	406	+ return clock;
	407	+}
	408	+
	409	+unsigned int cm_get_l4_sp_clk_hz(void)
	410	+{
	411	+ uint32_t reg, clock = 0;
	412	+
	413	+ /* identify the source of L4 SP clock */
	414	+ reg = readl(&clock_manager_base->main_pll.l4src);
	415	+ reg = CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(reg);
	416	+
	417	+ if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
	418	+ /* get the main VCO clock */
	419	+ reg = readl(&clock_manager_base->main_pll.vco);
	420	+ clock = CONFIG_HPS_CLK_OSC1_HZ /
	421	+ (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
	422	+ clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
	423	+
	424	+ /* get the clock prior L4 SP divider (main clk) */
	425	+ reg = readl(&clock_manager_base->altera.mainclk);
	426	+ clock /= (reg + 1);
	427	+ reg = readl(&clock_manager_base->main_pll.mainclk);
	428	+ clock /= (reg + 1);
	429	+ } else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
	430	+ /* identify PER PLL clock source */
	431	+ reg = readl(&clock_manager_base->per_pll.vco);
	432	+ reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg);
	433	+ if (reg == CLKMGR_VCO_SSRC_EOSC1)
	434	+ clock = CONFIG_HPS_CLK_OSC1_HZ;
	435	+ else if (reg == CLKMGR_VCO_SSRC_EOSC2)
	436	+ clock = CONFIG_HPS_CLK_OSC2_HZ;
	437	+ else if (reg == CLKMGR_VCO_SSRC_F2S)
	438	+ clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
	439	+
	440	+ /* get the PER VCO clock */
	441	+ reg = readl(&clock_manager_base->per_pll.vco);
	442	+ clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1);
	443	+ clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1);
	444	+
	445	+ /* get the clock prior L4 SP divider (periph_base_clk) */
	446	+ reg = readl(&clock_manager_base->per_pll.perbaseclk);
	447	+ clock /= (reg + 1);
	448	+ }
	449	+
	450	+ /* get the L4 SP clock which supplied to UART */
	451	+ reg = readl(&clock_manager_base->main_pll.maindiv);
	452	+ reg = CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_GET(reg);
	453	+ clock = clock / (1 << reg);
	454	+
	455	+ return clock;
	456	+}
	457	+
	458	+unsigned int cm_get_mmc_controller_clk_hz(void)
	459	+{
	460	+ uint32_t reg, clock = 0;
	461	+
	462	+ /* identify the source of MMC clock */
	463	+ reg = readl(&clock_manager_base->per_pll.src);
	464	+ reg = CLKMGR_PERPLLGRP_SRC_SDMMC_GET(reg);
	465	+
	466	+ if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
	467	+ clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
	468	+ } else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {
	469	+ /* get the main VCO clock */
	470	+ reg = readl(&clock_manager_base->main_pll.vco);
	471	+ clock = CONFIG_HPS_CLK_OSC1_HZ /
	472	+ (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
	473	+ clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
	474	+
	475	+ /* get the SDMMC clock */
	476	+ reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);
	477	+ clock /= (reg + 1);
	478	+ } else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
	479	+ /* identify PER PLL clock source */
	480	+ reg = readl(&clock_manager_base->per_pll.vco);
	481	+ reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg);
	482	+ if (reg == CLKMGR_VCO_SSRC_EOSC1)
	483	+ clock = CONFIG_HPS_CLK_OSC1_HZ;
	484	+ else if (reg == CLKMGR_VCO_SSRC_EOSC2)
	485	+ clock = CONFIG_HPS_CLK_OSC2_HZ;
	486	+ else if (reg == CLKMGR_VCO_SSRC_F2S)
	487	+ clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
	488	+
	489	+ /* get the PER VCO clock */
	490	+ reg = readl(&clock_manager_base->per_pll.vco);
	491	+ clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1);
	492	+ clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1);
	493	+
	494	+ /* get the SDMMC clock */
	495	+ reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);
	496	+ clock /= (reg + 1);
	497	+ }
	498	+
	499	+ /* further divide by 4 as we have fixed divider at wrapper */
	500	+ clock /= 4;
	501	+ return clock;
	502	+}
	503	+
	504	+unsigned int cm_get_qspi_controller_clk_hz(void)
	505	+{
	506	+ uint32_t reg, clock = 0;
	507	+
	508	+ /* identify the source of QSPI clock */
	509	+ reg = readl(&clock_manager_base->per_pll.src);
	510	+ reg = CLKMGR_PERPLLGRP_SRC_QSPI_GET(reg);
	511	+
	512	+ if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
	513	+ clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
	514	+ } else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) {
	515	+ /* get the main VCO clock */
	516	+ reg = readl(&clock_manager_base->main_pll.vco);
	517	+ clock = CONFIG_HPS_CLK_OSC1_HZ /
	518	+ (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
	519	+ clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
	520	+
	521	+ /* get the qspi clock */
	522	+ reg = readl(&clock_manager_base->main_pll.mainqspiclk);
	523	+ clock /= (reg + 1);
	524	+ } else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
	525	+ /* identify PER PLL clock source */
	526	+ reg = readl(&clock_manager_base->per_pll.vco);
	527	+ reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg);
	528	+ if (reg == CLKMGR_VCO_SSRC_EOSC1)
	529	+ clock = CONFIG_HPS_CLK_OSC1_HZ;
	530	+ else if (reg == CLKMGR_VCO_SSRC_EOSC2)
	531	+ clock = CONFIG_HPS_CLK_OSC2_HZ;
	532	+ else if (reg == CLKMGR_VCO_SSRC_F2S)
	533	+ clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
	534	+
	535	+ /* get the PER VCO clock */
	536	+ reg = readl(&clock_manager_base->per_pll.vco);
	537	+ clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1);
	538	+ clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1);
	539	+
	540	+ /* get the qspi clock */
	541	+ reg = readl(&clock_manager_base->per_pll.perqspiclk);
	542	+ clock /= (reg + 1);
	543	+ }
	544	+
	545	+ return clock;
	546	+}
	547	+
	548	+static void cm_print_clock_quick_summary(void)
	549	+{
	550	+ printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
	551	+ printf("DDR %10ld kHz\n", cm_get_sdram_clk_hz() / 1000);
	552	+ printf("EOSC1 %8d kHz\n", CONFIG_HPS_CLK_OSC1_HZ / 1000);
	553	+ printf("EOSC2 %8d kHz\n", CONFIG_HPS_CLK_OSC2_HZ / 1000);
	554	+ printf("F2S_SDR_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_SDR_REF_HZ / 1000);
	555	+ printf("F2S_PER_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_PER_REF_HZ / 1000);
	556	+ printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
	557	+ printf("QSPI %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
	558	+ printf("UART %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
	559	+}
	560	+
	561	+int set_cpu_clk_info(void)
	562	+{
	563	+ /* Calculate the clock frequencies required for drivers */
	564	+ cm_get_l4_sp_clk_hz();
	565	+ cm_get_mmc_controller_clk_hz();
	566	+
	567	+ gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
	568	+ gd->bd->bi_dsp_freq = 0;
	569	+ gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
	570	+
	571	+ return 0;
	572	+}
	573	+
	574	+int do_showclocks(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
	575	+{
	576	+ cm_print_clock_quick_summary();
	577	+ return 0;
	578	+}
	579	+
	580	+U_BOOT_CMD(
	581	+ clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks,
	582	+ "display clocks",
	583	+ ""
	584	+);
...	...	@@ -7,6 +7,15 @@
7	7	#ifndef _CLOCK_MANAGER_H_
8	8	#define _CLOCK_MANAGER_H_
9	9
	10	+#ifndef __ASSEMBLER__
	11	+/* Clock speed accessors */
	12	+unsigned long cm_get_mpu_clk_hz(void);
	13	+unsigned long cm_get_sdram_clk_hz(void);
	14	+unsigned int cm_get_l4_sp_clk_hz(void);
	15	+unsigned int cm_get_mmc_controller_clk_hz(void);
	16	+unsigned int cm_get_qspi_controller_clk_hz(void);
	17	+#endif
	18	+
10	19	typedef struct {
11	20	/* main group */
12	21	uint32_t main_vco_base;
...	...	@@ -89,6 +98,11 @@
89	98	u32 stat;
90	99	};
91	100
	101	+struct socfpga_clock_manager_altera {
	102	+ u32 mpuclk;
	103	+ u32 mainclk;
	104	+};
	105	+
92	106	struct socfpga_clock_manager {
93	107	u32 ctrl;
94	108	u32 bypass;
...	...	@@ -100,7 +114,8 @@
100	114	struct socfpga_clock_manager_main_pll main_pll;
101	115	struct socfpga_clock_manager_per_pll per_pll;
102	116	struct socfpga_clock_manager_sdr_pll sdr_pll;
103		- u32 _pad_0xe0_0x200[72];
	117	+ struct socfpga_clock_manager_altera altera;
	118	+ u32 _pad_0xe8_0x200[70];
104	119	};
105	120
106	121	#define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001
107	122
...	...	@@ -118,8 +133,10 @@
118	133
119	134	/* Main PLL */
120	135	#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001)
	136	+#define CLKMGR_MAINPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16)
121	137	#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
122	138	#define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002)
	139	+#define CLKMGR_MAINPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3)
123	140	#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
124	141	#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
125	142	#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004)
...	...	@@ -148,7 +165,8 @@
148	165	#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003)
149	166	#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c)
150	167	#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070)
151		-#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x) (((x) << 7) & 0x00000380)
	168	+#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_GET(x) (((x) & 0x00000380) >> 7)
	169	+#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x) (((x) << 7) & 0x00000380)
152	170
153	171	#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003)
154	172	#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c)
155	173
156	174
157	175
158	176
...	...	@@ -156,16 +174,25 @@
156	174	#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007)
157	175
158	176	#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001)
	177	+#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(x) (((x) & 0x00000002) >> 1)
159	178	#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002)
160	179	#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
	180	+#define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0
	181	+#define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1
161	182
162	183	/* Per PLL */
	184	+#define CLKMGR_PERPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16)
163	185	#define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
	186	+#define CLKMGR_PERPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3)
164	187	#define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
165	188	#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
166	189	#define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000)
167	190	#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
168	191	#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
	192	+#define CLKMGR_PERPLLGRP_VCO_SSRC_GET(x) (((x) & 0x00c00000) >> 22)
	193	+#define CLKMGR_VCO_SSRC_EOSC1 0x0
	194	+#define CLKMGR_VCO_SSRC_EOSC2 0x1
	195	+#define CLKMGR_VCO_SSRC_F2S 0x2
169	196
170	197	#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
171	198
172	199
173	200
174	201
175	202
...	...	@@ -191,12 +218,22 @@
191	218	#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff)
192	219
193	220	#define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c)
	221	+#define CLKMGR_PERPLLGRP_SRC_QSPI_GET(x) (((x) & 0x00000030) >> 4)
194	222	#define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030)
195	223	#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
	224	+#define CLKMGR_PERPLLGRP_SRC_SDMMC_GET(x) (((x) & 0x00000003) >> 0)
196	225	#define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003)
	226	+#define CLKMGR_SDMMC_CLK_SRC_F2S 0x0
	227	+#define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1
	228	+#define CLKMGR_SDMMC_CLK_SRC_PER 0x2
	229	+#define CLKMGR_QSPI_CLK_SRC_F2S 0x0
	230	+#define CLKMGR_QSPI_CLK_SRC_MAIN 0x1
	231	+#define CLKMGR_QSPI_CLK_SRC_PER 0x2
197	232
198	233	/* SDR PLL */
	234	+#define CLKMGR_SDRPLLGRP_VCO_DENOM_GET(x) (((x) & 0x003f0000) >> 16)
199	235	#define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
	236	+#define CLKMGR_SDRPLLGRP_VCO_NUMER_GET(x) (((x) & 0x0000fff8) >> 3)
200	237	#define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
201	238	#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
202	239	#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
203	240
...	...	@@ -204,8 +241,10 @@
204	241	#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000)
205	242	#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
206	243	#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
	244	+#define CLKMGR_SDRPLLGRP_VCO_SSRC_GET(x) (((x) & 0x00c00000) >> 22)
207	245	#define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000)
208	246
	247	+#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_GET(x) (((x) & 0x000001ff) >> 0)
209	248	#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
210	249	#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
211	250	#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00
...	...	@@ -24,6 +24,7 @@
24	24	#define CONFIG_MISC_INIT_R
25	25	#define CONFIG_SINGLE_BOOTLOADER
26	26	#define CONFIG_SOCFPGA
	27	+#define CONFIG_CLOCKS
27	28
28	29	/* base address for .text section */
29	30	#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET