Merge branch 'master' of http://git.denx.de/u-boot-sunxi

Tom Rini
2 parents 0ce3f1f90a 840fe95c3b
Showing 24 changed files Side-by-side Diff
arch/arm/cpu/armv7/exynos/spl_boot.c
arch/arm/cpu/armv7/omap-common/lowlevel_init.S
arch/arm/cpu/armv7/omap3/lowlevel_init.S
arch/arm/cpu/armv7/start.S
arch/arm/cpu/armv7/sunxi/Makefile
arch/arm/cpu/armv7/sunxi/board.c
arch/arm/cpu/armv7/sunxi/config.mk
arch/arm/cpu/armv7/sunxi/dram_helpers.c
arch/arm/cpu/armv7/sunxi/fel_utils.S
arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
arch/arm/include/asm/arch-sunxi/dram.h
arch/arm/include/asm/arch-sunxi/sys_proto.h
arch/arm/include/asm/spl.h
arch/arm/include/asm/system.h
board/nokia/rx51/lowlevel_init.S
board/sunxi/Kconfig
board/sunxi/MAINTAINERS
common/spl/spl.c
configs/Ampe_A76_defconfig
drivers/usb/musb-new/sunxi.c
@@ -309,5 +309,4 @@
 	while (1)
 		;
 }
-void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {}
@@ -19,7 +19,7 @@
 ENTRY(save_boot_params)
 	ldr	r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS
 	str	r0, [r1]
-	bx	lr
+	b	save_boot_params_ret
 ENDPROC(save_boot_params)
  
 ENTRY(set_pl310_ctrl_reg)
@@ -23,7 +23,7 @@
 	ldr	r5, [r0, #0x4]
 	and	r5, r5, #0xff
 	str	r5, [r4]
-	bx	lr
+	b	save_boot_params_ret
 ENDPROC(save_boot_params)
 #endif
  
@@ -31,9 +31,12 @@
  *************************************************************************/
  
 	.globl	reset
+	.globl	save_boot_params_ret
  
 reset:
-	bl	save_boot_params
+	/* Allow the board to save important registers */
+	b	save_boot_params
+save_boot_params_ret:
 	/*
 	 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
 	 * except if in HYP mode already
@@ -96,7 +99,7 @@
  *
  *************************************************************************/
 ENTRY(save_boot_params)
-	bx	lr			@ back to my caller
+	b	save_boot_params_ret		@ back to my caller
 ENDPROC(save_boot_params)
 	.weak	save_boot_params
  
@@ -11,6 +11,7 @@
 obj-y	+= board.o
 obj-y	+= clock.o
 obj-y	+= cpu_info.o
+obj-y	+= dram_helpers.o
 obj-y	+= pinmux.o
 obj-y	+= usbc.o
 obj-$(CONFIG_MACH_SUN6I)	+= prcm.o
@@ -38,8 +39,6 @@
 obj-$(CONFIG_MACH_SUN6I)	+= dram_sun6i.o
 obj-$(CONFIG_MACH_SUN7I)	+= dram_sun4i.o
 obj-$(CONFIG_MACH_SUN8I)	+= dram_sun8i.o
-ifdef CONFIG_SPL_FEL
-obj-y	+= start.o
-endif
+obj-y	+= fel_utils.o
 endif
@@ -27,6 +27,17 @@
  
 #include <linux/compiler.h>
  
+struct fel_stash {
+	uint32_t sp;
+	uint32_t lr;
+	uint32_t cpsr;
+	uint32_t sctlr;
+	uint32_t vbar;
+	uint32_t cr;
+};
+
+struct fel_stash fel_stash __attribute__((section(".data")));
+
 static int gpio_init(void)
 {
 #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
@@ -65,6 +76,12 @@
 	return 0;
 }
  
+void spl_board_load_image(void)
+{
+	debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
+	return_to_fel(fel_stash.sp, fel_stash.lr);
+}
+
 void s_init(void)
 {
 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
@@ -95,7 +112,34 @@
  */
 u32 spl_boot_device(void)
 {
-	return BOOT_DEVICE_MMC1;
+#ifdef CONFIG_SPL_FEL
+	/*
+	 * This is the legacy compile time configuration for a special FEL
+	 * enabled build. It has many restrictions and can only boot over USB.
+	 */
+	return BOOT_DEVICE_BOARD;
+#else
+	/*
+	 * When booting from the SD card, the "eGON.BT0" signature is expected
+	 * to be found in memory at the address 0x0004 (see the "mksunxiboot"
+	 * tool, which generates this header).
+	 *
+	 * When booting in the FEL mode over USB, this signature is patched in
+	 * memory and replaced with something else by the 'fel' tool. This other
+	 * signature is selected in such a way, that it can't be present in a
+	 * valid bootable SD card image (because the BROM would refuse to
+	 * execute the SPL in this case).
+	 *
+	 * This branch is just making a decision at runtime whether to load
+	 * the main u-boot binary from the SD card (if the "eGON.BT0" signature
+	 * is found) or return to the FEL code in the BROM to wait and receive
+	 * the main u-boot binary over USB.
+	 */
+	if (readl(4) == 0x4E4F4765 && readl(8) == 0x3054422E) /* eGON.BT0 */
+		return BOOT_DEVICE_MMC1;
+	else
+		return BOOT_DEVICE_BOARD;
+#endif
 }
  
 /* No confirmation data available in SPL yet. Hardcode bootmode */
 # Build a combined spl + u-boot image
 ifdef CONFIG_SPL
 ifndef CONFIG_SPL_BUILD
-ifndef CONFIG_SPL_FEL
 ALL-y += u-boot-sunxi-with-spl.bin
-endif
 endif
 endif
+/*
+ * DRAM init helper functions
+ *
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/dram.h>
+
+/*
+ * Wait up to 1s for value to be set in given part of reg.
+ */
+void mctl_await_completion(u32 *reg, u32 mask, u32 val)
+{
+	unsigned long tmo = timer_get_us() + 1000000;
+
+	while ((readl(reg) & mask) != val) {
+		if (timer_get_us() > tmo)
+			panic("Timeout initialising DRAM\n");
+	}
+}
+
+/*
+ * Test if memory at offset offset matches memory at begin of DRAM
+ */
+bool mctl_mem_matches(u32 offset)
+{
+	/* Try to write different values to RAM at two addresses */
+	writel(0, CONFIG_SYS_SDRAM_BASE);
+	writel(0xaa55aa55, CONFIG_SYS_SDRAM_BASE + offset);
+	/* Check if the same value is actually observed when reading back */
+	return readl(CONFIG_SYS_SDRAM_BASE) ==
+	       readl(CONFIG_SYS_SDRAM_BASE + offset);
+}
+/*
+ * Utility functions for FEL mode.
+ *
+ * Copyright (c) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/system.h>
+#include <linux/linkage.h>
+
+ENTRY(save_boot_params)
+	ldr	r0, =fel_stash
+	str	sp, [r0, #0]
+	str	lr, [r0, #4]
+	mrs	lr, cpsr		@ Read CPSR
+	str	lr, [r0, #8]
+	mrc	p15, 0, lr, c1, c0, 0	@ Read CP15 SCTLR Register
+	str	lr, [r0, #12]
+	mrc	p15, 0, lr, c12, c0, 0	@ Read VBAR
+	str	lr, [r0, #16]
+	mrc	p15, 0, lr, c1, c0, 0	@ Read CP15 Control Register
+	str	lr, [r0, #20]
+	b	save_boot_params_ret
+ENDPROC(save_boot_params)
+
+ENTRY(return_to_fel)
+	mov	sp, r0
+	mov	lr, r1
+	ldr	r0, =fel_stash
+	ldr	r1, [r0, #20]
+	mcr	p15, 0, r1, c1, c0, 0	@ Write CP15 Control Register
+	ldr	r1, [r0, #16]
+	mcr	p15, 0, r1, c12, c0, 0	@ Write VBAR
+	ldr	r1, [r0, #12]
+	mcr	p15, 0, r1, c1, c0, 0	@ Write CP15 SCTLR Register
+	ldr	r1, [r0, #8]
+	msr	cpsr, r1		@ Write CPSR
+	bx	lr
+ENDPROC(return_to_fel)
-/*
- * (C) Copyright 2013
- * Henrik Nordstrom <henrik@henriknordstrom.net>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(s_init)
-SECTIONS
-{
-	. = 0x00002000;
-
-	. = ALIGN(4);
-	.text :
-	{
-		*(.text.s_init)
-		*(.text*)
-	}
-
-	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-	. = ALIGN(4);
-	.data : {
-		*(.data*)
-	}
-
-	. = ALIGN(4);
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	}
-
-	. = ALIGN(4);
-	. = .;
-
-	. = ALIGN(4);
-	.rel.dyn : {
-		__rel_dyn_start = .;
-		*(.rel*)
-		__rel_dyn_end = .;
-	}
-
-	.dynsym : {
-		__dynsym_start = .;
-		*(.dynsym)
-	}
-
-	. = ALIGN(4);
-	.note.gnu.build-id :
-	{
-		*(.note.gnu.build-id)
-	}
-	_end = .;
-
-	. = ALIGN(4096);
-	.mmutable : {
-		*(.mmutable)
-	}
-
-	.bss_start __rel_dyn_start (OVERLAY) : {
-		KEEP(*(.__bss_start));
-		__bss_base = .;
-	}
-
-	.bss __bss_base (OVERLAY) : {
-		*(.bss*)
-		. = ALIGN(4);
-		__bss_limit = .;
-	}
-
-	.bss_end __bss_limit (OVERLAY) : {
-		KEEP(*(.__bss_end));
-	}
-
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-	/DISCARD/ : { *(.note*) }
-}
@@ -25,32 +25,8 @@
 #endif
  
 unsigned long sunxi_dram_init(void);
-
-/*
- * Wait up to 1s for value to be set in given part of reg.
- */
-static inline void mctl_await_completion(u32 *reg, u32 mask, u32 val)
-{
-	unsigned long tmo = timer_get_us() + 1000000;
-
-	while ((readl(reg) & mask) != val) {
-		if (timer_get_us() > tmo)
-			panic("Timeout initialising DRAM\n");
-	}
-}
-
-/*
- * Test if memory at offset offset matches memory at begin of DRAM
- */
-static inline bool mctl_mem_matches(u32 offset)
-{
-	/* Try to write different values to RAM at two addresses */
-	writel(0, CONFIG_SYS_SDRAM_BASE);
-	writel(0xaa55aa55, CONFIG_SYS_SDRAM_BASE + offset);
-	/* Check if the same value is actually observed when reading back */
-	return readl(CONFIG_SYS_SDRAM_BASE) ==
-	       readl(CONFIG_SYS_SDRAM_BASE + offset);
-}
+void mctl_await_completion(u32 *reg, u32 mask, u32 val);
+bool mctl_mem_matches(u32 offset);
  
 #endif /* _SUNXI_DRAM_H */
@@ -13,5 +13,15 @@
  
 void sdelay(unsigned long);
  
+/* return_to_fel() - Return to BROM from SPL
+ *
+ * This returns back into the BROM after U-Boot SPL has performed its initial
+ * init. It uses the provided lr and sp to do so.
+ *
+ * @lr:		BROM link register value (return address)
+ * @sp:		BROM stack pointer
+ */
+void return_to_fel(uint32_t lr, uint32_t sp);
+
 #endif
@@ -26,9 +26,13 @@
 	BOOT_DEVICE_SPI,
 	BOOT_DEVICE_SATA,
 	BOOT_DEVICE_I2C,
+	BOOT_DEVICE_BOARD,
 	BOOT_DEVICE_NONE
 };
 #endif
+
+/* Board-specific load method */
+void spl_board_load_image(void);
  
 /* Linker symbols. */
 extern char __bss_start[], __bss_end[];
@@ -142,6 +142,21 @@
  
 #ifndef __ASSEMBLY__
  
+/**
+ * save_boot_params() - Save boot parameters before starting reset sequence
+ *
+ * If you provide this function it will be called immediately U-Boot starts,
+ * both for SPL and U-Boot proper.
+ *
+ * All registers are unchanged from U-Boot entry. No registers need be
+ * preserved.
+ *
+ * This is not a normal C function. There is no stack. Return by branching to
+ * save_boot_params_ret.
+ *
+ * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3);
+ */
+
 #define isb() __asm__ __volatile__ ("" : : : "memory")
  
 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
@@ -37,7 +37,8 @@
  
 .global save_boot_params
 save_boot_params:
-
+	/* Get return address */
+	ldr	lr, =save_boot_params_ret
  
 /* Copy valid attached kernel to address KERNEL_ADDRESS */
  
@@ -149,6 +149,16 @@
 	bool "SPL/FEL mode support"
 	depends on SPL
 	default n
+	help
+	  This enables support for Fast Early Loader (FEL) mode. This
+	  allows U-Boot to be loaded to the board over USB by the on-chip
+	  boot rom. U-Boot should be sent in two parts: SPL first, with
+	  'fel write 0x2000 u-boot-spl.bin; fel exe 0x2000' then U-Boot with
+	  'fel write 0x4a000000 u-boot.bin; fel exe 0x4a000000'. This option
+	  shrinks the amount of SRAM available to SPL, so only enable it if
+	  you need FEL. Note that enabling this option only allows FEL to be
+	  used; it is still possible to boot U-Boot from boot media. U-Boot
+	  SPL detects when it is being loaded using FEL.
  
 config UART0_PORT_F
 	bool "UART0 on MicroSD breakout board"
@@ -46,6 +46,11 @@
 F:	board/sunxi/dram_a20_olinuxino_l2.c
 F:	configs/A20-OLinuXino-Lime2_defconfig
  
+AMPE A76 BOARD
+M:	Paul Kocialkowski <contact@paulk.fr>
+S:	Maintained
+F:	configs/Ampe_A76_defconfig
+
 COLOMBUS BOARD
 M:	Maxime Ripard <maxime.ripard@free-electrons.com>
 S:	Maintained
  
@@ -57,9 +62,7 @@
 S:	Maintained
 F:	include/configs/sun7i.h
 F:	configs/Cubieboard2_defconfig
-F:	configs/Cubieboard2_FEL_defconfig
 F:	configs/Cubietruck_defconfig
-F:	configs/Cubietruck_FEL_defconfig
  
 GEMEI-G9 TABLET
 M:	Priit Laes <plaes@plaes.org>
@@ -229,6 +229,11 @@
 		spl_sata_load_image();
 		break;
 #endif
+#ifdef CONFIG_SPL_BOARD_LOAD_IMAGE
+	case BOOT_DEVICE_BOARD:
+		spl_board_load_image();
+		break;
+#endif
 	default:
 #if defined(CONFIG_SPL_SERIAL_SUPPORT) && defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
 		puts("SPL: Unsupported Boot Device!\n");
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER"
+CONFIG_FDTFILE="sun5i-a13-ampe-a76.dtb"
+CONFIG_USB_MUSB_SUNXI=y
+CONFIG_USB0_VBUS_PIN="PG12"
+CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:82,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_POWER="AXP0-0"
+CONFIG_VIDEO_LCD_BL_EN="AXP0-1"
+CONFIG_VIDEO_LCD_BL_PWM="PB2"
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN5I=y
++S:CONFIG_DRAM_CLK=432
++S:CONFIG_DRAM_ZQ=123
++S:CONFIG_DRAM_EMR1=4
@@ -145,16 +145,6 @@
 	musb_writel(base, USBC_REG_o_ISCR, reg_val);
 }
  
-static void USBC_ForceVbusValidDisable(__iomem void *base)
-{
-	u32 reg_val;
-
-	reg_val = musb_readl(base, USBC_REG_o_ISCR);
-	reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
-	reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
-	musb_writel(base, USBC_REG_o_ISCR, reg_val);
-}
-
 static void USBC_ForceVbusValidToHigh(__iomem void *base)
 {
 	u32 reg_val;
  
  
@@ -248,12 +238,11 @@
 	if (is_host_enabled(musb)) {
 		/* Host mode */
 		USBC_ForceIdToLow(musb->mregs);
-		USBC_ForceVbusValidToHigh(musb->mregs);
 	} else {
 		/* Peripheral mode */
 		USBC_ForceIdToHigh(musb->mregs);
-		USBC_ForceVbusValidDisable(musb->mregs);
 	}
+	USBC_ForceVbusValidToHigh(musb->mregs);
  
 	return 0;
 }
@@ -46,6 +46,7 @@
 	GraphicDevice graphic_device;
 	enum sunxi_monitor monitor;
 	unsigned int depth;
+	unsigned int fb_size;
 } sunxi_display;
  
 #ifdef CONFIG_VIDEO_HDMI
@@ -1060,6 +1061,11 @@
 	return NULL; /* never reached */
 }
  
+ulong board_get_usable_ram_top(ulong total_size)
+{
+	return gd->ram_top - CONFIG_SUNXI_MAX_FB_SIZE;
+}
+
 void *video_hw_init(void)
 {
 	static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
@@ -1075,10 +1081,6 @@
  
 	memset(&sunxi_display, 0, sizeof(struct sunxi_display));
  
-	printf("Reserved %dkB of RAM for Framebuffer.\n",
-	       CONFIG_SUNXI_FB_SIZE >> 10);
-	gd->fb_base = gd->ram_top;
-
 	video_get_ctfb_res_modes(RES_MODE_1024x768, 24, &mode,
 				 &sunxi_display.depth, &options);
 #ifdef CONFIG_VIDEO_HDMI
@@ -1169,6 +1171,17 @@
 		       mode->yres, sunxi_get_mon_desc(sunxi_display.monitor));
 	}
  
+	sunxi_display.fb_size =
+		(mode->xres * mode->yres * 4 + 0xfff) & ~0xfff;
+	if (sunxi_display.fb_size > CONFIG_SUNXI_MAX_FB_SIZE) {
+		printf("Error need %dkB for fb, but only %dkB is reserved\n",
+		       sunxi_display.fb_size >> 10,
+		       CONFIG_SUNXI_MAX_FB_SIZE >> 10);
+		return NULL;
+	}
+
+	gd->fb_base = gd->bd->bi_dram[0].start +
+		      gd->bd->bi_dram[0].size - sunxi_display.fb_size;
 	sunxi_engines_init();
 	sunxi_mode_set(mode, gd->fb_base - CONFIG_SYS_SDRAM_BASE);
  
@@ -1194,6 +1207,7 @@
 {
 	static GraphicDevice *graphic_device = &sunxi_display.graphic_device;
 	int offset, ret;
+	u64 start, size;
 	const char *pipeline = NULL;
  
 #ifdef CONFIG_MACH_SUN4I
@@ -1235,6 +1249,20 @@
 	if (offset < 0) {
 		eprintf("Cannot setup simplefb: node not found\n");
 		return 0; /* Keep older kernels working */
+	}
+
+	/*
+	 * Do not report the framebuffer as free RAM to the OS, note we cannot
+	 * use fdt_add_mem_rsv() here, because then it is still seen as RAM,
+	 * and e.g. Linux refuses to iomap RAM on ARM, see:
+	 * linux/arch/arm/mm/ioremap.c around line 301.
+	 */
+	start = gd->bd->bi_dram[0].start;
+	size = gd->bd->bi_dram[0].size - sunxi_display.fb_size;
+	ret = fdt_fixup_memory_banks(blob, &start, &size, 1);
+	if (ret) {
+		eprintf("Cannot setup simplefb: Error reserving memory\n");
+		return ret;
 	}
  
 	ret = fdt_setup_simplefb_node(blob, offset, gd->fb_base,
@@ -18,10 +18,8 @@
  */
 #define CONFIG_SUNXI		/* sunxi family */
 #ifdef CONFIG_SPL_BUILD
-#ifndef CONFIG_SPL_FEL
 #define CONFIG_SYS_THUMB_BUILD	/* Thumbs mode to save space in SPL */
 #endif
-#endif
  
 #include <asm/arch/cpu.h>	/* get chip and board defs */
  
  
@@ -145,10 +143,10 @@
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  
+#define CONFIG_SPL_BOARD_LOAD_IMAGE
+
 #ifdef CONFIG_SPL_FEL
  
-#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds"
-#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7/sunxi"
 #define CONFIG_SPL_TEXT_BASE		0x2000
 #define CONFIG_SPL_MAX_SIZE		0x4000		/* 16 KiB */
  
  
@@ -206,10 +204,10 @@
  
 #ifdef CONFIG_VIDEO
 /*
- * The amount of RAM that is reserved for the FB. This will not show up as
- * RAM to the kernel, but will be reclaimed by a KMS driver in future.
+ * The amount of RAM to keep free at the top of RAM when relocating u-boot,
+ * to use as framebuffer. This must be a multiple of 4096.
  */
-#define CONFIG_SUNXI_FB_SIZE (9 << 20)
+#define CONFIG_SUNXI_MAX_FB_SIZE (9 << 20)
  
 /* Do we want to initialize a simple FB? */
 #define CONFIG_VIDEO_DT_SIMPLEFB
@@ -226,8 +224,6 @@
 #define CONFIG_CONSOLE_MUX
 /* stop x86 thinking in cfbconsole from trying to init a pc keyboard */
 #define CONFIG_VGA_AS_SINGLE_DEVICE
-
-#define CONFIG_SYS_MEM_TOP_HIDE ((CONFIG_SUNXI_FB_SIZE + 0xFFF) & ~0xFFF)
  
 /* To be able to hook simplefb into dt */
 #ifdef CONFIG_VIDEO_DT_SIMPLEFB
@@ -154,9 +154,7 @@
 endif
  
 ifdef CONFIG_SUNXI
-ifndef CONFIG_SPL_FEL
 ALL-y	+= $(obj)/sunxi-spl.bin
-endif
 endif
  
 ifeq ($(CONFIG_SYS_SOC),"at91")
@@ -43,19 +43,19 @@
 	uint32_t i;
 	uint32_t sum;
  
-	length = head_p->length;
+	length = le32_to_cpu(head_p->length);
 	if ((length & 0x3) != 0)	/* must 4-byte-aligned */
 		return -1;
 	buf = (uint32_t *)head_p;
-	head_p->check_sum = STAMP_VALUE;	/* fill stamp */
+	head_p->check_sum = cpu_to_le32(STAMP_VALUE);	/* fill stamp */
 	loop = length >> 2;
  
 	/* calculate the sum */
 	for (i = 0, sum = 0; i < loop; i++)
-		sum += buf[i];
+		sum += le32_to_cpu(buf[i]);
  
 	/* write back check sum */
-	head_p->check_sum = sum;
+	head_p->check_sum = cpu_to_le32(sum);
  
 	return 0;
 }
  
@@ -125,10 +125,12 @@
 	memcpy(img.header.magic, BOOT0_MAGIC, 8);	/* no '0' termination */
 	img.header.length =
 		ALIGN(file_size + sizeof(struct boot_file_head), BLOCK_SIZE);
+	img.header.b_instruction = cpu_to_le32(img.header.b_instruction);
+	img.header.length = cpu_to_le32(img.header.length);
 	gen_check_sum(&img.header);
  
-	count = write(fd_out, &img, img.header.length);
-	if (count != img.header.length) {
+	count = write(fd_out, &img, le32_to_cpu(img.header.length));
+	if (count != le32_to_cpu(img.header.length)) {
 		perror("Writing output");
 		return EXIT_FAILURE;
 	}
...	...	@@ -309,5 +309,4 @@
309	309	while (1)
310	310	;
311	311	}
312		-void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {}
...	...	@@ -19,7 +19,7 @@
19	19	ENTRY(save_boot_params)
20	20	ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS
21	21	str r0, [r1]
22		- bx lr
	22	+ b save_boot_params_ret
23	23	ENDPROC(save_boot_params)
24	24
25	25	ENTRY(set_pl310_ctrl_reg)
...	...	@@ -23,7 +23,7 @@
23	23	ldr r5, [r0, #0x4]
24	24	and r5, r5, #0xff
25	25	str r5, [r4]
26		- bx lr
	26	+ b save_boot_params_ret
27	27	ENDPROC(save_boot_params)
28	28	#endif
29	29
...	...	@@ -31,9 +31,12 @@
31	31	*************************************************************************/
32	32
33	33	.globl reset
	34	+ .globl save_boot_params_ret
34	35
35	36	reset:
36		- bl save_boot_params
	37	+ /* Allow the board to save important registers */
	38	+ b save_boot_params
	39	+save_boot_params_ret:
37	40	/*
38	41	* disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
39	42	* except if in HYP mode already
...	...	@@ -96,7 +99,7 @@
96	99	*
97	100	*************************************************************************/
98	101	ENTRY(save_boot_params)
99		- bx lr @ back to my caller
	102	+ b save_boot_params_ret @ back to my caller
100	103	ENDPROC(save_boot_params)
101	104	.weak save_boot_params
102	105
...	...	@@ -11,6 +11,7 @@
11	11	obj-y += board.o
12	12	obj-y += clock.o
13	13	obj-y += cpu_info.o
	14	+obj-y += dram_helpers.o
14	15	obj-y += pinmux.o
15	16	obj-y += usbc.o
16	17	obj-$(CONFIG_MACH_SUN6I) += prcm.o
...	...	@@ -38,8 +39,6 @@
38	39	obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o
39	40	obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o
40	41	obj-$(CONFIG_MACH_SUN8I) += dram_sun8i.o
41		-ifdef CONFIG_SPL_FEL
42		-obj-y += start.o
43		-endif
	42	+obj-y += fel_utils.o
44	43	endif
...	...	@@ -27,6 +27,17 @@
27	27
28	28	#include <linux/compiler.h>
29	29
	30	+struct fel_stash {
	31	+ uint32_t sp;
	32	+ uint32_t lr;
	33	+ uint32_t cpsr;
	34	+ uint32_t sctlr;
	35	+ uint32_t vbar;
	36	+ uint32_t cr;
	37	+};
	38	+
	39	+struct fel_stash fel_stash __attribute__((section(".data")));
	40	+
30	41	static int gpio_init(void)
31	42	{
32	43	#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
...	...	@@ -65,6 +76,12 @@
65	76	return 0;
66	77	}
67	78
	79	+void spl_board_load_image(void)
	80	+{
	81	+ debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
	82	+ return_to_fel(fel_stash.sp, fel_stash.lr);
	83	+}
	84	+
68	85	void s_init(void)
69	86	{
70	87	#if defined CONFIG_MACH_SUN6I \|\| defined CONFIG_MACH_SUN8I
...	...	@@ -95,7 +112,34 @@
95	112	*/
96	113	u32 spl_boot_device(void)
97	114	{
98		- return BOOT_DEVICE_MMC1;
	115	+#ifdef CONFIG_SPL_FEL
	116	+ /*
	117	+ * This is the legacy compile time configuration for a special FEL
	118	+ * enabled build. It has many restrictions and can only boot over USB.
	119	+ */
	120	+ return BOOT_DEVICE_BOARD;
	121	+#else
	122	+ /*
	123	+ * When booting from the SD card, the "eGON.BT0" signature is expected
	124	+ * to be found in memory at the address 0x0004 (see the "mksunxiboot"
	125	+ * tool, which generates this header).
	126	+ *
	127	+ * When booting in the FEL mode over USB, this signature is patched in
	128	+ * memory and replaced with something else by the 'fel' tool. This other
	129	+ * signature is selected in such a way, that it can't be present in a
	130	+ * valid bootable SD card image (because the BROM would refuse to
	131	+ * execute the SPL in this case).
	132	+ *
	133	+ * This branch is just making a decision at runtime whether to load
	134	+ * the main u-boot binary from the SD card (if the "eGON.BT0" signature
	135	+ * is found) or return to the FEL code in the BROM to wait and receive
	136	+ * the main u-boot binary over USB.
	137	+ */
	138	+ if (readl(4) == 0x4E4F4765 && readl(8) == 0x3054422E) /* eGON.BT0 */
	139	+ return BOOT_DEVICE_MMC1;
	140	+ else
	141	+ return BOOT_DEVICE_BOARD;
	142	+#endif
99	143	}
100	144
101	145	/* No confirmation data available in SPL yet. Hardcode bootmode */
1	1	# Build a combined spl + u-boot image
2	2	ifdef CONFIG_SPL
3	3	ifndef CONFIG_SPL_BUILD
4		-ifndef CONFIG_SPL_FEL
5	4	ALL-y += u-boot-sunxi-with-spl.bin
6		-endif
7	5	endif
8	6	endif
	1	+/*
	2	+ * DRAM init helper functions
	3	+ *
	4	+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
	5	+ *
	6	+ * SPDX-License-Identifier: GPL-2.0+
	7	+ */
	8	+
	9	+#include <common.h>
	10	+#include <asm/io.h>
	11	+#include <asm/arch/dram.h>
	12	+
	13	+/*
	14	+ * Wait up to 1s for value to be set in given part of reg.
	15	+ */
	16	+void mctl_await_completion(u32 *reg, u32 mask, u32 val)
	17	+{
	18	+ unsigned long tmo = timer_get_us() + 1000000;
	19	+
	20	+ while ((readl(reg) & mask) != val) {
	21	+ if (timer_get_us() > tmo)
	22	+ panic("Timeout initialising DRAM\n");
	23	+ }
	24	+}
	25	+
	26	+/*
	27	+ * Test if memory at offset offset matches memory at begin of DRAM
	28	+ */
	29	+bool mctl_mem_matches(u32 offset)
	30	+{
	31	+ /* Try to write different values to RAM at two addresses */
	32	+ writel(0, CONFIG_SYS_SDRAM_BASE);
	33	+ writel(0xaa55aa55, CONFIG_SYS_SDRAM_BASE + offset);
	34	+ /* Check if the same value is actually observed when reading back */
	35	+ return readl(CONFIG_SYS_SDRAM_BASE) ==
	36	+ readl(CONFIG_SYS_SDRAM_BASE + offset);
	37	+}
	1	+/*
	2	+ * Utility functions for FEL mode.
	3	+ *
	4	+ * Copyright (c) 2015 Google, Inc
	5	+ *
	6	+ * SPDX-License-Identifier: GPL-2.0+
	7	+ */
	8	+
	9	+#include <asm-offsets.h>
	10	+#include <config.h>
	11	+#include <asm/system.h>
	12	+#include <linux/linkage.h>
	13	+
	14	+ENTRY(save_boot_params)
	15	+ ldr r0, =fel_stash
	16	+ str sp, [r0, #0]
	17	+ str lr, [r0, #4]
	18	+ mrs lr, cpsr @ Read CPSR
	19	+ str lr, [r0, #8]
	20	+ mrc p15, 0, lr, c1, c0, 0 @ Read CP15 SCTLR Register
	21	+ str lr, [r0, #12]
	22	+ mrc p15, 0, lr, c12, c0, 0 @ Read VBAR
	23	+ str lr, [r0, #16]
	24	+ mrc p15, 0, lr, c1, c0, 0 @ Read CP15 Control Register
	25	+ str lr, [r0, #20]
	26	+ b save_boot_params_ret
	27	+ENDPROC(save_boot_params)
	28	+
	29	+ENTRY(return_to_fel)
	30	+ mov sp, r0
	31	+ mov lr, r1
	32	+ ldr r0, =fel_stash
	33	+ ldr r1, [r0, #20]
	34	+ mcr p15, 0, r1, c1, c0, 0 @ Write CP15 Control Register
	35	+ ldr r1, [r0, #16]
	36	+ mcr p15, 0, r1, c12, c0, 0 @ Write VBAR
	37	+ ldr r1, [r0, #12]
	38	+ mcr p15, 0, r1, c1, c0, 0 @ Write CP15 SCTLR Register
	39	+ ldr r1, [r0, #8]
	40	+ msr cpsr, r1 @ Write CPSR
	41	+ bx lr
	42	+ENDPROC(return_to_fel)
1		-/*
2		- * (C) Copyright 2013
3		- * Henrik Nordstrom <henrik@henriknordstrom.net>
4		- *
5		- * SPDX-License-Identifier: GPL-2.0+
6		- */
7		-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
8		-OUTPUT_ARCH(arm)
9		-ENTRY(s_init)
10		-SECTIONS
11		-{
12		- . = 0x00002000;
13		-
14		- . = ALIGN(4);
15		- .text :
16		- {
17		- *(.text.s_init)
18		- (.text)
19		- }
20		-
21		- . = ALIGN(4);
22		- .rodata : { (SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata))) }
23		-
24		- . = ALIGN(4);
25		- .data : {
26		- (.data)
27		- }
28		-
29		- . = ALIGN(4);
30		- .u_boot_list : {
31		- KEEP((SORT(.u_boot_list)));
32		- }
33		-
34		- . = ALIGN(4);
35		- . = .;
36		-
37		- . = ALIGN(4);
38		- .rel.dyn : {
39		- __rel_dyn_start = .;
40		- (.rel)
41		- __rel_dyn_end = .;
42		- }
43		-
44		- .dynsym : {
45		- __dynsym_start = .;
46		- *(.dynsym)
47		- }
48		-
49		- . = ALIGN(4);
50		- .note.gnu.build-id :
51		- {
52		- *(.note.gnu.build-id)
53		- }
54		- _end = .;
55		-
56		- . = ALIGN(4096);
57		- .mmutable : {
58		- *(.mmutable)
59		- }
60		-
61		- .bss_start __rel_dyn_start (OVERLAY) : {
62		- KEEP(*(.__bss_start));
63		- __bss_base = .;
64		- }
65		-
66		- .bss __bss_base (OVERLAY) : {
67		- (.bss)
68		- . = ALIGN(4);
69		- __bss_limit = .;
70		- }
71		-
72		- .bss_end __bss_limit (OVERLAY) : {
73		- KEEP(*(.__bss_end));
74		- }
75		-
76		- /DISCARD/ : { (.dynstr) }
77		- /DISCARD/ : { (.dynamic) }
78		- /DISCARD/ : { (.plt) }
79		- /DISCARD/ : { (.interp) }
80		- /DISCARD/ : { (.gnu) }
81		- /DISCARD/ : { (.note) }
82		-}