arm/ls1021a: Remove ccsr_ddr from immap_ls102xa.h

ccsr_ddr structure is already defined in fsl_immap.h. Remove this duplicated define. Move fixed timing into ls1021atwr.h. Signed-off-by: York Sun <yorksun@freescale.com> CC: Alison Wang <alison.wang@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com>

arm/ls1021a: Remove ccsr_ddr from immap_ls102xa.h
ccsr_ddr structure is already defined in fsl_immap.h. Remove this duplicated define. Move fixed timing into ls1021atwr.h. Signed-off-by: York Sun <yorksun@freescale.com> CC: Alison Wang <alison.wang@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com>
York Sun
1 parent d9be24c92d
Showing 3 changed files with 24 additions and 146 deletions Side-by-side Diff
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
board/freescale/ls1021atwr/ls1021atwr.c
include/configs/ls1021atwr.h
@@ -348,152 +348,6 @@
 	u8	res_a00[0x1000-0xa00];	/* from 0xa00 to 0xfff */
 };
  
-#define DDR_SDRAM_CFG			0x470c0008
-#define DDR_CS0_BNDS			0x008000bf
-#define DDR_CS0_CONFIG			0x80014302
-#define DDR_TIMING_CFG_0		0x50550004
-#define DDR_TIMING_CFG_1		0xbcb38c56
-#define DDR_TIMING_CFG_2		0x0040d120
-#define DDR_TIMING_CFG_3		0x010e1000
-#define DDR_TIMING_CFG_4		0x00000001
-#define DDR_TIMING_CFG_5		0x03401400
-#define DDR_SDRAM_CFG_2			0x00401010
-#define DDR_SDRAM_MODE			0x00061c60
-#define DDR_SDRAM_MODE_2		0x00180000
-#define DDR_SDRAM_INTERVAL		0x18600618
-#define DDR_DDR_WRLVL_CNTL		0x8655f605
-#define DDR_DDR_WRLVL_CNTL_2		0x05060607
-#define DDR_DDR_WRLVL_CNTL_3		0x05050505
-#define DDR_DDR_CDR1			0x80040000
-#define DDR_DDR_CDR2			0x00000001
-#define DDR_SDRAM_CLK_CNTL		0x02000000
-#define DDR_DDR_ZQ_CNTL			0x89080600
-#define DDR_CS0_CONFIG_2		0
-#define DDR_SDRAM_CFG_MEM_EN		0x80000000
-
-/* DDR memory controller registers */
-struct ccsr_ddr {
-	u32 cs0_bnds;			/* Chip Select 0 Memory Bounds */
-	u32 resv1[1];
-	u32 cs1_bnds;			/* Chip Select 1 Memory Bounds */
-	u32 resv2[1];
-	u32 cs2_bnds;			/* Chip Select 2 Memory Bounds */
-	u32 resv3[1];
-	u32 cs3_bnds;			/* Chip Select 3 Memory Bounds */
-	u32 resv4[25];
-	u32 cs0_config;			/* Chip Select Configuration */
-	u32 cs1_config;			/* Chip Select Configuration */
-	u32 cs2_config;			/* Chip Select Configuration */
-	u32 cs3_config;			/* Chip Select Configuration */
-	u32 resv5[12];
-	u32 cs0_config_2;		/* Chip Select Configuration 2 */
-	u32 cs1_config_2;		/* Chip Select Configuration 2 */
-	u32 cs2_config_2;		/* Chip Select Configuration 2 */
-	u32 cs3_config_2;		/* Chip Select Configuration 2 */
-	u32 resv6[12];
-	u32 timing_cfg_3;		/* SDRAM Timing Configuration 3 */
-	u32 timing_cfg_0;		/* SDRAM Timing Configuration 0 */
-	u32 timing_cfg_1;		/* SDRAM Timing Configuration 1 */
-	u32 timing_cfg_2;		/* SDRAM Timing Configuration 2 */
-	u32 sdram_cfg;			/* SDRAM Control Configuration */
-	u32 sdram_cfg_2;		/* SDRAM Control Configuration 2 */
-	u32 sdram_mode;			/* SDRAM Mode Configuration */
-	u32 sdram_mode_2;		/* SDRAM Mode Configuration 2 */
-	u32 sdram_md_cntl;		/* SDRAM Mode Control */
-	u32 sdram_interval;		/* SDRAM Interval Configuration */
-	u32 sdram_data_init;		/* SDRAM Data initialization */
-	u32 resv7[1];
-	u32 sdram_clk_cntl;		/* SDRAM Clock Control */
-	u32 resv8[5];
-	u32 init_addr;			/* training init addr */
-	u32 init_ext_addr;		/* training init extended addr */
-	u32 resv9[4];
-	u32 timing_cfg_4;		/* SDRAM Timing Configuration 4 */
-	u32 timing_cfg_5;		/* SDRAM Timing Configuration 5 */
-	u32 timing_cfg_6;		/* SDRAM Timing Configuration 6 */
-	u32 timing_cfg_7;		/* SDRAM Timing Configuration 7 */
-	u32 ddr_zq_cntl;		/* ZQ calibration control*/
-	u32 ddr_wrlvl_cntl;		/* write leveling control*/
-	u32 resv10[1];
-	u32 ddr_sr_cntr;		/* self refresvh counter */
-	u32 ddr_sdram_rcw_1;		/* Control Words 1 */
-	u32 ddr_sdram_rcw_2;		/* Control Words 2 */
-	u32 resv11[2];
-	u32 ddr_wrlvl_cntl_2;		/* write leveling control 2 */
-	u32 ddr_wrlvl_cntl_3;		/* write leveling control 3 */
-	u32 resv12[2];
-	u32 ddr_sdram_rcw_3;		/* Control Words 3 */
-	u32 ddr_sdram_rcw_4;		/* Control Words 4 */
-	u32 ddr_sdram_rcw_5;		/* Control Words 5 */
-	u32 ddr_sdram_rcw_6;		/* Control Words 6 */
-	u32 resv13[20];
-	u32 sdram_mode_3;		/* SDRAM Mode Configuration 3 */
-	u32 sdram_mode_4;		/* SDRAM Mode Configuration 4 */
-	u32 sdram_mode_5;		/* SDRAM Mode Configuration 5 */
-	u32 sdram_mode_6;		/* SDRAM Mode Configuration 6 */
-	u32 sdram_mode_7;		/* SDRAM Mode Configuration 7 */
-	u32 sdram_mode_8;		/* SDRAM Mode Configuration 8 */
-	u32 sdram_mode_9;		/* SDRAM Mode Configuration 9 */
-	u32 sdram_mode_10;		/* SDRAM Mode Configuration 10 */
-	u32 sdram_mode_11;		/* SDRAM Mode Configuration 11 */
-	u32 sdram_mode_12;		/* SDRAM Mode Configuration 12 */
-	u32 sdram_mode_13;		/* SDRAM Mode Configuration 13 */
-	u32 sdram_mode_14;		/* SDRAM Mode Configuration 14 */
-	u32 sdram_mode_15;		/* SDRAM Mode Configuration 15 */
-	u32 sdram_mode_16;		/* SDRAM Mode Configuration 16 */
-	u32 resv14[4];
-	u32 timing_cfg_8;		/* SDRAM Timing Configuration 8 */
-	u32 timing_cfg_9;		/* SDRAM Timing Configuration 9 */
-	u32 resv15[2];
-	u32 sdram_cfg_3;		/* SDRAM Control Configuration 3 */
-	u32 resv16[15];
-	u32 deskew_cntl;		/* SDRAM Deskew Control */
-	u32 resv17[545];
-	u32 ddr_dsr1;			/* Debug Status 1 */
-	u32 ddr_dsr2;			/* Debug Status 2 */
-	u32 ddr_cdr1;			/* Control Driver 1 */
-	u32 ddr_cdr2;			/* Control Driver 2 */
-	u32 resv18[50];
-	u32 ip_rev1;			/* IP Block Revision 1 */
-	u32 ip_rev2;			/* IP Block Revision 2 */
-	u32 eor;			/* Enhanced Optimization Register */
-	u32 resv19[63];
-	u32 mtcr;			/* Memory Test Control Register */
-	u32 resv20[7];
-	u32 mtp1;			/* Memory Test Pattern 1 */
-	u32 mtp2;			/* Memory Test Pattern 2 */
-	u32 mtp3;			/* Memory Test Pattern 3 */
-	u32 mtp4;			/* Memory Test Pattern 4 */
-	u32 mtp5;			/* Memory Test Pattern 5 */
-	u32 mtp6;			/* Memory Test Pattern 6 */
-	u32 mtp7;			/* Memory Test Pattern 7 */
-	u32 mtp8;			/* Memory Test Pattern 8 */
-	u32 mtp9;			/* Memory Test Pattern 9 */
-	u32 mtp10;			/* Memory Test Pattern 10 */
-	u32 resv21[6];
-	u32 ddr_mt_st_ext_addr;		/* Memory Test Start Extended Address */
-	u32 ddr_mt_st_addr;		/* Memory Test Start Address */
-	u32 ddr_mt_end_ext_addr;	/* Memory Test End Extended Address */
-	u32 ddr_mt_end_addr;		/* Memory Test End Address */
-	u32 resv22[36];
-	u32 data_err_inject_hi;		/* Data Path Err Injection Mask High */
-	u32 data_err_inject_lo;		/* Data Path Err Injection Mask Low */
-	u32 ecc_err_inject;		/* Data Path Err Injection Mask ECC */
-	u32 resv23[5];
-	u32 capture_data_hi;		/* Data Path Read Capture High */
-	u32 capture_data_lo;		/* Data Path Read Capture Low */
-	u32 capture_ecc;		/* Data Path Read Capture ECC */
-	u32 resv24[5];
-	u32 err_detect;			/* Error Detect */
-	u32 err_disable;		/* Error Disable */
-	u32 err_int_en;
-	u32 capture_attributes;		/* Error Attrs Capture */
-	u32 capture_address;		/* Error Addr Capture */
-	u32 capture_ext_address;	/* Error Extended Addr Capture */
-	u32 err_sbe;			/* Single-Bit ECC Error Management */
-	u32 resv25[105];
-};
-
 #define CCI400_CTRLORD_TERM_BARRIER	0x00000008
 #define CCI400_CTRLORD_EN_BARRIER	0
 #define CCI400_SHAORD_NON_SHAREABLE	0x00000002
@@ -16,6 +16,7 @@
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <fsl_ifc.h>
+#include <fsl_immap.h>
 #include <netdev.h>
 #include <fsl_mdio.h>
 #include <tsec.h>
@@ -35,6 +35,29 @@
 #define CONFIG_SYS_CLK_FREQ		100000000
 #define CONFIG_DDR_CLK_FREQ		100000000
  
+#define DDR_SDRAM_CFG			0x470c0008
+#define DDR_CS0_BNDS			0x008000bf
+#define DDR_CS0_CONFIG			0x80014302
+#define DDR_TIMING_CFG_0		0x50550004
+#define DDR_TIMING_CFG_1		0xbcb38c56
+#define DDR_TIMING_CFG_2		0x0040d120
+#define DDR_TIMING_CFG_3		0x010e1000
+#define DDR_TIMING_CFG_4		0x00000001
+#define DDR_TIMING_CFG_5		0x03401400
+#define DDR_SDRAM_CFG_2			0x00401010
+#define DDR_SDRAM_MODE			0x00061c60
+#define DDR_SDRAM_MODE_2		0x00180000
+#define DDR_SDRAM_INTERVAL		0x18600618
+#define DDR_DDR_WRLVL_CNTL		0x8655f605
+#define DDR_DDR_WRLVL_CNTL_2		0x05060607
+#define DDR_DDR_WRLVL_CNTL_3		0x05050505
+#define DDR_DDR_CDR1			0x80040000
+#define DDR_DDR_CDR2			0x00000001
+#define DDR_SDRAM_CLK_CNTL		0x02000000
+#define DDR_DDR_ZQ_CNTL			0x89080600
+#define DDR_CS0_CONFIG_2		0
+#define DDR_SDRAM_CFG_MEM_EN		0x80000000
+
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_SYS_FSL_PBL_PBI	board/freescale/ls1021atwr/ls102xa_pbi.cfg
 #endif
...	...	@@ -348,152 +348,6 @@
348	348	u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
349	349	};
350	350
351		-#define DDR_SDRAM_CFG 0x470c0008
352		-#define DDR_CS0_BNDS 0x008000bf
353		-#define DDR_CS0_CONFIG 0x80014302
354		-#define DDR_TIMING_CFG_0 0x50550004
355		-#define DDR_TIMING_CFG_1 0xbcb38c56
356		-#define DDR_TIMING_CFG_2 0x0040d120
357		-#define DDR_TIMING_CFG_3 0x010e1000
358		-#define DDR_TIMING_CFG_4 0x00000001
359		-#define DDR_TIMING_CFG_5 0x03401400
360		-#define DDR_SDRAM_CFG_2 0x00401010
361		-#define DDR_SDRAM_MODE 0x00061c60
362		-#define DDR_SDRAM_MODE_2 0x00180000
363		-#define DDR_SDRAM_INTERVAL 0x18600618
364		-#define DDR_DDR_WRLVL_CNTL 0x8655f605
365		-#define DDR_DDR_WRLVL_CNTL_2 0x05060607
366		-#define DDR_DDR_WRLVL_CNTL_3 0x05050505
367		-#define DDR_DDR_CDR1 0x80040000
368		-#define DDR_DDR_CDR2 0x00000001
369		-#define DDR_SDRAM_CLK_CNTL 0x02000000
370		-#define DDR_DDR_ZQ_CNTL 0x89080600
371		-#define DDR_CS0_CONFIG_2 0
372		-#define DDR_SDRAM_CFG_MEM_EN 0x80000000
373		-
374		-/* DDR memory controller registers */
375		-struct ccsr_ddr {
376		- u32 cs0_bnds; /* Chip Select 0 Memory Bounds */
377		- u32 resv1[1];
378		- u32 cs1_bnds; /* Chip Select 1 Memory Bounds */
379		- u32 resv2[1];
380		- u32 cs2_bnds; /* Chip Select 2 Memory Bounds */
381		- u32 resv3[1];
382		- u32 cs3_bnds; /* Chip Select 3 Memory Bounds */
383		- u32 resv4[25];
384		- u32 cs0_config; /* Chip Select Configuration */
385		- u32 cs1_config; /* Chip Select Configuration */
386		- u32 cs2_config; /* Chip Select Configuration */
387		- u32 cs3_config; /* Chip Select Configuration */
388		- u32 resv5[12];
389		- u32 cs0_config_2; /* Chip Select Configuration 2 */
390		- u32 cs1_config_2; /* Chip Select Configuration 2 */
391		- u32 cs2_config_2; /* Chip Select Configuration 2 */
392		- u32 cs3_config_2; /* Chip Select Configuration 2 */
393		- u32 resv6[12];
394		- u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
395		- u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
396		- u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
397		- u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
398		- u32 sdram_cfg; /* SDRAM Control Configuration */
399		- u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */
400		- u32 sdram_mode; /* SDRAM Mode Configuration */
401		- u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */
402		- u32 sdram_md_cntl; /* SDRAM Mode Control */
403		- u32 sdram_interval; /* SDRAM Interval Configuration */
404		- u32 sdram_data_init; /* SDRAM Data initialization */
405		- u32 resv7[1];
406		- u32 sdram_clk_cntl; /* SDRAM Clock Control */
407		- u32 resv8[5];
408		- u32 init_addr; /* training init addr */
409		- u32 init_ext_addr; /* training init extended addr */
410		- u32 resv9[4];
411		- u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */
412		- u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */
413		- u32 timing_cfg_6; /* SDRAM Timing Configuration 6 */
414		- u32 timing_cfg_7; /* SDRAM Timing Configuration 7 */
415		- u32 ddr_zq_cntl; /* ZQ calibration control*/
416		- u32 ddr_wrlvl_cntl; /* write leveling control*/
417		- u32 resv10[1];
418		- u32 ddr_sr_cntr; /* self refresvh counter */
419		- u32 ddr_sdram_rcw_1; /* Control Words 1 */
420		- u32 ddr_sdram_rcw_2; /* Control Words 2 */
421		- u32 resv11[2];
422		- u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */
423		- u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */
424		- u32 resv12[2];
425		- u32 ddr_sdram_rcw_3; /* Control Words 3 */
426		- u32 ddr_sdram_rcw_4; /* Control Words 4 */
427		- u32 ddr_sdram_rcw_5; /* Control Words 5 */
428		- u32 ddr_sdram_rcw_6; /* Control Words 6 */
429		- u32 resv13[20];
430		- u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */
431		- u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */
432		- u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */
433		- u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */
434		- u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */
435		- u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */
436		- u32 sdram_mode_9; /* SDRAM Mode Configuration 9 */
437		- u32 sdram_mode_10; /* SDRAM Mode Configuration 10 */
438		- u32 sdram_mode_11; /* SDRAM Mode Configuration 11 */
439		- u32 sdram_mode_12; /* SDRAM Mode Configuration 12 */
440		- u32 sdram_mode_13; /* SDRAM Mode Configuration 13 */
441		- u32 sdram_mode_14; /* SDRAM Mode Configuration 14 */
442		- u32 sdram_mode_15; /* SDRAM Mode Configuration 15 */
443		- u32 sdram_mode_16; /* SDRAM Mode Configuration 16 */
444		- u32 resv14[4];
445		- u32 timing_cfg_8; /* SDRAM Timing Configuration 8 */
446		- u32 timing_cfg_9; /* SDRAM Timing Configuration 9 */
447		- u32 resv15[2];
448		- u32 sdram_cfg_3; /* SDRAM Control Configuration 3 */
449		- u32 resv16[15];
450		- u32 deskew_cntl; /* SDRAM Deskew Control */
451		- u32 resv17[545];
452		- u32 ddr_dsr1; /* Debug Status 1 */
453		- u32 ddr_dsr2; /* Debug Status 2 */
454		- u32 ddr_cdr1; /* Control Driver 1 */
455		- u32 ddr_cdr2; /* Control Driver 2 */
456		- u32 resv18[50];
457		- u32 ip_rev1; /* IP Block Revision 1 */
458		- u32 ip_rev2; /* IP Block Revision 2 */
459		- u32 eor; /* Enhanced Optimization Register */
460		- u32 resv19[63];
461		- u32 mtcr; /* Memory Test Control Register */
462		- u32 resv20[7];
463		- u32 mtp1; /* Memory Test Pattern 1 */
464		- u32 mtp2; /* Memory Test Pattern 2 */
465		- u32 mtp3; /* Memory Test Pattern 3 */
466		- u32 mtp4; /* Memory Test Pattern 4 */
467		- u32 mtp5; /* Memory Test Pattern 5 */
468		- u32 mtp6; /* Memory Test Pattern 6 */
469		- u32 mtp7; /* Memory Test Pattern 7 */
470		- u32 mtp8; /* Memory Test Pattern 8 */
471		- u32 mtp9; /* Memory Test Pattern 9 */
472		- u32 mtp10; /* Memory Test Pattern 10 */
473		- u32 resv21[6];
474		- u32 ddr_mt_st_ext_addr; /* Memory Test Start Extended Address */
475		- u32 ddr_mt_st_addr; /* Memory Test Start Address */
476		- u32 ddr_mt_end_ext_addr; /* Memory Test End Extended Address */
477		- u32 ddr_mt_end_addr; /* Memory Test End Address */
478		- u32 resv22[36];
479		- u32 data_err_inject_hi; /* Data Path Err Injection Mask High */
480		- u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */
481		- u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */
482		- u32 resv23[5];
483		- u32 capture_data_hi; /* Data Path Read Capture High */
484		- u32 capture_data_lo; /* Data Path Read Capture Low */
485		- u32 capture_ecc; /* Data Path Read Capture ECC */
486		- u32 resv24[5];
487		- u32 err_detect; /* Error Detect */
488		- u32 err_disable; /* Error Disable */
489		- u32 err_int_en;
490		- u32 capture_attributes; /* Error Attrs Capture */
491		- u32 capture_address; /* Error Addr Capture */
492		- u32 capture_ext_address; /* Error Extended Addr Capture */
493		- u32 err_sbe; /* Single-Bit ECC Error Management */
494		- u32 resv25[105];
495		-};
496		-
497	351	#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
498	352	#define CCI400_CTRLORD_EN_BARRIER 0
499	353	#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
...	...	@@ -16,6 +16,7 @@
16	16	#include <mmc.h>
17	17	#include <fsl_esdhc.h>
18	18	#include <fsl_ifc.h>
	19	+#include <fsl_immap.h>
19	20	#include <netdev.h>
20	21	#include <fsl_mdio.h>
21	22	#include <tsec.h>
...	...	@@ -35,6 +35,29 @@
35	35	#define CONFIG_SYS_CLK_FREQ 100000000
36	36	#define CONFIG_DDR_CLK_FREQ 100000000
37	37
	38	+#define DDR_SDRAM_CFG 0x470c0008
	39	+#define DDR_CS0_BNDS 0x008000bf
	40	+#define DDR_CS0_CONFIG 0x80014302
	41	+#define DDR_TIMING_CFG_0 0x50550004
	42	+#define DDR_TIMING_CFG_1 0xbcb38c56
	43	+#define DDR_TIMING_CFG_2 0x0040d120
	44	+#define DDR_TIMING_CFG_3 0x010e1000
	45	+#define DDR_TIMING_CFG_4 0x00000001
	46	+#define DDR_TIMING_CFG_5 0x03401400
	47	+#define DDR_SDRAM_CFG_2 0x00401010
	48	+#define DDR_SDRAM_MODE 0x00061c60
	49	+#define DDR_SDRAM_MODE_2 0x00180000
	50	+#define DDR_SDRAM_INTERVAL 0x18600618
	51	+#define DDR_DDR_WRLVL_CNTL 0x8655f605
	52	+#define DDR_DDR_WRLVL_CNTL_2 0x05060607
	53	+#define DDR_DDR_WRLVL_CNTL_3 0x05050505
	54	+#define DDR_DDR_CDR1 0x80040000
	55	+#define DDR_DDR_CDR2 0x00000001
	56	+#define DDR_SDRAM_CLK_CNTL 0x02000000
	57	+#define DDR_DDR_ZQ_CNTL 0x89080600
	58	+#define DDR_CS0_CONFIG_2 0
	59	+#define DDR_SDRAM_CFG_MEM_EN 0x80000000
	60	+
38	61	#ifdef CONFIG_RAMBOOT_PBL
39	62	#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
40	63	#endif