Commit a89a8423938d46798a54bf838a3aafa90009b3c6
1 parent
70b1c1bb1c
Exists in
smarc-rel_imx_4.1.15_2.0.0_ga
MLK-12687 mx6ullarm2: Clean up macro usage for pins conflict devices
1. Bind the macro CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK to eMMC 8 bits rework, which conflicts with QSPIA and NAND, that we have to disable them at same time. 2. Bind the macro CONFIG_MX6ULL_DDR3_ARM2_QSPIB_REWORK to QSPI B port rework, which conflicts with SD2 and NAND, that we have to disable them at same time. 3. Fix a typo issue of CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK 4. Enable QSPI support for default SD boot case. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 00f36b3e9445ff47ed68262ef2d656e410cd8fcd)
Showing 2 changed files with 11 additions and 8 deletions Side-by-side Diff
board/freescale/mx6ull_ddr3_arm2/mx6ull_ddr3_arm2.c
| ... | ... | @@ -119,7 +119,6 @@ |
| 119 | 119 | MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 120 | 120 | MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 121 | 121 | MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 122 | -#if !defined(CONFIG_SYS_USE_NAND) && !defined(CONFIG_SYS_USE_QSPI1A) | |
| 123 | 122 | /* |
| 124 | 123 | * The following 4 pins conflicts with qspi and nand flash. |
| 125 | 124 | * You can comment out the following 4 pins and change |
| ... | ... | @@ -130,7 +129,6 @@ |
| 130 | 129 | MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 131 | 130 | MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 132 | 131 | MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 133 | -#endif | |
| 134 | 132 | |
| 135 | 133 | /* Default NO WP for emmc, since we use pull down */ |
| 136 | 134 | MX6_PAD_UART1_CTS_B__USDHC1_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL_WP), |
| ... | ... | @@ -156,7 +154,7 @@ |
| 156 | 154 | }; |
| 157 | 155 | #endif |
| 158 | 156 | |
| 159 | -#if !defined(CONFIG_SYS_USE_NAND) && !defined(CONFIG_SYS_USE_QSPI1B) | |
| 157 | +#if !defined(CONFIG_SYS_USE_NAND) && !defined(CONFIG_MX6ULL_DDR3_ARM2_QSPIB_REWORK) | |
| 160 | 158 | static iomux_v3_cfg_t const usdhc2_pads[] = { |
| 161 | 159 | /* usdhc2_clk, nand_re_b, qspi1b_clk */ |
| 162 | 160 | MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| ... | ... | @@ -344,6 +342,7 @@ |
| 344 | 342 | MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| 345 | 343 | MX6_PAD_NAND_DATA07__QSPI_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| 346 | 344 | |
| 345 | +#ifdef CONFIG_MX6ULL_DDR3_ARM2_QSPIB_REWORK | |
| 347 | 346 | MX6_PAD_NAND_RE_B__QSPI_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| 348 | 347 | MX6_PAD_NAND_WE_B__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| 349 | 348 | MX6_PAD_NAND_DATA00__QSPI_B_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| ... | ... | @@ -351,6 +350,7 @@ |
| 351 | 350 | MX6_PAD_NAND_DATA03__QSPI_B_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| 352 | 351 | MX6_PAD_NAND_DATA04__QSPI_B_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| 353 | 352 | MX6_PAD_NAND_DATA05__QSPI_B_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), |
| 353 | +#endif | |
| 354 | 354 | }; |
| 355 | 355 | |
| 356 | 356 | int board_qspi_init(void) |
| 357 | 357 | |
| ... | ... | @@ -368,13 +368,13 @@ |
| 368 | 368 | |
| 369 | 369 | #ifdef CONFIG_FSL_ESDHC |
| 370 | 370 | static struct fsl_esdhc_cfg usdhc_cfg[2] = { |
| 371 | -#if !defined(CONFIG_SYS_USE_NAND) && !defined(CONFIG_SYS_USE_QSPI1A) | |
| 371 | +#ifdef CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK | |
| 372 | 372 | /* If want to use qspi, should change to 4 bit width */ |
| 373 | 373 | {USDHC1_BASE_ADDR, 0, 8}, |
| 374 | 374 | #else |
| 375 | 375 | {USDHC1_BASE_ADDR, 0, 4}, |
| 376 | 376 | #endif |
| 377 | -#if !defined(CONFIG_SYS_USE_NAND) && !defined(CONFIG_SYS_USE_QSPI1B) | |
| 377 | +#if !defined(CONFIG_SYS_USE_NAND) && !defined(CONFIG_MX6ULL_DDR3_ARM2_QSPIB_REWORK) | |
| 378 | 378 | {USDHC2_BASE_ADDR, 0, 4}, |
| 379 | 379 | #endif |
| 380 | 380 | }; |
| ... | ... | @@ -408,7 +408,7 @@ |
| 408 | 408 | ret = !gpio_get_value(USDHC1_CD_GPIO); |
| 409 | 409 | #endif |
| 410 | 410 | break; |
| 411 | -#if !defined(CONFIG_SYS_USE_NAND) && !defined(CONFIG_SYS_USE_QSPI1A) | |
| 411 | +#if !defined(CONFIG_SYS_USE_NAND) && !defined(CONFIG_MX6ULL_DDR3_ARM2_QSPIB_REWORK) | |
| 412 | 412 | case USDHC2_BASE_ADDR: |
| 413 | 413 | ret = !gpio_get_value(USDHC2_CD_GPIO); |
| 414 | 414 | break; |
| ... | ... | @@ -431,7 +431,7 @@ |
| 431 | 431 | for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { |
| 432 | 432 | switch (i) { |
| 433 | 433 | case 0: |
| 434 | -#ifdef CONFIG_MX6UL_DDR3_ARM2_EMMC_REWORK | |
| 434 | +#ifdef CONFIG_MX6ULL_DDR3_ARM2_EMMC_REWORK | |
| 435 | 435 | imx_iomux_v3_setup_multiple_pads( |
| 436 | 436 | usdhc1_emmc_pads, ARRAY_SIZE(usdhc1_emmc_pads)); |
| 437 | 437 | #else |
| ... | ... | @@ -444,7 +444,7 @@ |
| 444 | 444 | gpio_direction_output(USDHC1_VSELECT, 0); |
| 445 | 445 | gpio_direction_output(USDHC1_PWR_GPIO, 1); |
| 446 | 446 | break; |
| 447 | -#if !defined(CONFIG_SYS_USE_NAND) && !defined(CONFIG_SYS_USE_QSPI1A) | |
| 447 | +#if !defined(CONFIG_SYS_USE_NAND) && !defined(CONFIG_MX6ULL_DDR3_ARM2_QSPIB_REWORK) | |
| 448 | 448 | case 1: |
| 449 | 449 | imx_iomux_v3_setup_multiple_pads( |
| 450 | 450 | usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); |
include/configs/mx6ull_ddr3_arm2.h