Eric Lee / smarc-uboot

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Commit a8d0526133e542ea93a741fd18833e571e817775

Authored by Stephen Warren
Committed by Tom Warren
1 parent 1ab557a074
Exists in v2017.01-smarct4x and in 25 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ARM: tegra186: call secure monitor for all cache-wide ops 

An SMC call is required for all cache-wide operations on Tegra186. This
patch implements the two missing hooks now that U-Boot supports them, and
fixes the mapping of "hook name" to SMC call code.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

Showing 1 changed file with 21 additions and 3 deletions Inline Diff

arch/arm/mach-tegra/tegra186/cache.S
Diff comments   View file @ a8d0526
1 /* 1 /*
2 * Copyright (c) 2016, NVIDIA CORPORATION. 2 * Copyright (c) 2016, NVIDIA CORPORATION.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0 4 * SPDX-License-Identifier: GPL-2.0
5 */ 5 */
6 6
7 #include <config.h> 7 #include <config.h>
8 #include <linux/linkage.h> 8 #include <linux/linkage.h>
9 9
10 #define SMC_SIP_INVOKE_MCE 0x82FFFF00 10 #define SMC_SIP_INVOKE_MCE 0x82FFFF00
11 #define MCE_SMC_ROC_FLUSH_CACHE (SMC_SIP_INVOKE_MCE | 11) 11 #define MCE_SMC_ROC_FLUSH_CACHE (SMC_SIP_INVOKE_MCE | 11)
12 #define MCE_SMC_ROC_FLUSH_CACHE_ONLY (SMC_SIP_INVOKE_MCE | 14)
13 #define MCE_SMC_ROC_CLEAN_CACHE_ONLY (SMC_SIP_INVOKE_MCE | 15)
12 14
13 ENTRY(__asm_flush_l3_dcache) 15 ENTRY(__asm_tegra_cache_smc)
14 mov x0, #(MCE_SMC_ROC_FLUSH_CACHE & 0xffff)
15 movk x0, #(MCE_SMC_ROC_FLUSH_CACHE >> 16), lsl #16
16 mov x1, #0 16 mov x1, #0
17 mov x2, #0 17 mov x2, #0
18 mov x3, #0 18 mov x3, #0
19 mov x4, #0 19 mov x4, #0
20 mov x5, #0 20 mov x5, #0
21 mov x6, #0 21 mov x6, #0
22 smc #0 22 smc #0
23 mov x0, #0 23 mov x0, #0
24 ret 24 ret
25 ENDPROC(__asm_invalidate_l3_dcache)
26
27 ENTRY(__asm_invalidate_l3_dcache)
28 mov x0, #(MCE_SMC_ROC_FLUSH_CACHE_ONLY & 0xffff)
29 movk x0, #(MCE_SMC_ROC_FLUSH_CACHE_ONLY >> 16), lsl #16
30 b __asm_tegra_cache_smc
31 ENDPROC(__asm_invalidate_l3_dcache)
32
33 ENTRY(__asm_flush_l3_dcache)
34 mov x0, #(MCE_SMC_ROC_CLEAN_CACHE_ONLY & 0xffff)
35 movk x0, #(MCE_SMC_ROC_CLEAN_CACHE_ONLY >> 16), lsl #16
36 b __asm_tegra_cache_smc
25 ENDPROC(__asm_flush_l3_dcache) 37 ENDPROC(__asm_flush_l3_dcache)
38
39 ENTRY(__asm_invalidate_l3_icache)
40 mov x0, #(MCE_SMC_ROC_FLUSH_CACHE & 0xffff)
41 movk x0, #(MCE_SMC_ROC_FLUSH_CACHE >> 16), lsl #16
42 b __asm_tegra_cache_smc