Commit a8d0526133e542ea93a741fd18833e571e817775

Authored by Stephen Warren
Committed by Tom Warren
1 parent 1ab557a074

ARM: tegra186: call secure monitor for all cache-wide ops

An SMC call is required for all cache-wide operations on Tegra186. This
patch implements the two missing hooks now that U-Boot supports them, and
fixes the mapping of "hook name" to SMC call code.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

Showing 1 changed file with 21 additions and 3 deletions Side-by-side Diff

arch/arm/mach-tegra/tegra186/cache.S
... ... @@ -9,10 +9,10 @@
9 9  
10 10 #define SMC_SIP_INVOKE_MCE 0x82FFFF00
11 11 #define MCE_SMC_ROC_FLUSH_CACHE (SMC_SIP_INVOKE_MCE | 11)
  12 +#define MCE_SMC_ROC_FLUSH_CACHE_ONLY (SMC_SIP_INVOKE_MCE | 14)
  13 +#define MCE_SMC_ROC_CLEAN_CACHE_ONLY (SMC_SIP_INVOKE_MCE | 15)
12 14  
13   -ENTRY(__asm_flush_l3_dcache)
14   - mov x0, #(MCE_SMC_ROC_FLUSH_CACHE & 0xffff)
15   - movk x0, #(MCE_SMC_ROC_FLUSH_CACHE >> 16), lsl #16
  15 +ENTRY(__asm_tegra_cache_smc)
16 16 mov x1, #0
17 17 mov x2, #0
18 18 mov x3, #0
19 19  
... ... @@ -22,5 +22,23 @@
22 22 smc #0
23 23 mov x0, #0
24 24 ret
  25 +ENDPROC(__asm_invalidate_l3_dcache)
  26 +
  27 +ENTRY(__asm_invalidate_l3_dcache)
  28 + mov x0, #(MCE_SMC_ROC_FLUSH_CACHE_ONLY & 0xffff)
  29 + movk x0, #(MCE_SMC_ROC_FLUSH_CACHE_ONLY >> 16), lsl #16
  30 + b __asm_tegra_cache_smc
  31 +ENDPROC(__asm_invalidate_l3_dcache)
  32 +
  33 +ENTRY(__asm_flush_l3_dcache)
  34 + mov x0, #(MCE_SMC_ROC_CLEAN_CACHE_ONLY & 0xffff)
  35 + movk x0, #(MCE_SMC_ROC_CLEAN_CACHE_ONLY >> 16), lsl #16
  36 + b __asm_tegra_cache_smc
25 37 ENDPROC(__asm_flush_l3_dcache)
  38 +
  39 +ENTRY(__asm_invalidate_l3_icache)
  40 + mov x0, #(MCE_SMC_ROC_FLUSH_CACHE & 0xffff)
  41 + movk x0, #(MCE_SMC_ROC_FLUSH_CACHE >> 16), lsl #16
  42 + b __asm_tegra_cache_smc
  43 +ENDPROC(__asm_invalidate_l3_icache)