Eric Lee / smarc-uboot

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Commit a91ef4adfb5a4b21ebf37dffcb6c6e485c75685b

Authored by Anthoine Bourgeois
Committed by Tom Rini
1 parent 875e415492
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm: omap3: devkit8000: inherit from ti_omap3_common.h 

Signed-off-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>

Showing 2 changed files with 16 additions and 42 deletions Inline Diff

board/timll/devkit8000/devkit8000.c
Diff comments   View file @ a91ef4a
1 /* 1 /*
2 * (C) Copyright 2004-2008 2 * (C) Copyright 2004-2008
3 * Texas Instruments, <www.ti.com> 3 * Texas Instruments, <www.ti.com>
4 * 4 *
5 * Author : 5 * Author :
6 * Sunil Kumar <sunilsaini05@gmail.com> 6 * Sunil Kumar <sunilsaini05@gmail.com>
7 * Shashi Ranjan <shashiranjanmca05@gmail.com> 7 * Shashi Ranjan <shashiranjanmca05@gmail.com>
8 * 8 *
9 * (C) Copyright 2009 9 * (C) Copyright 2009
10 * Frederik Kriewitz <frederik@kriewitz.eu> 10 * Frederik Kriewitz <frederik@kriewitz.eu>
11 * 11 *
12 * Derived from Beagle Board and 3430 SDP code by 12 * Derived from Beagle Board and 3430 SDP code by
13 * Richard Woodruff <r-woodruff2@ti.com> 13 * Richard Woodruff <r-woodruff2@ti.com>
14 * Syed Mohammed Khasim <khasim@ti.com> 14 * Syed Mohammed Khasim <khasim@ti.com>
15 * 15 *
16 * 16 *
17 * SPDX-License-Identifier: GPL-2.0+ 17 * SPDX-License-Identifier: GPL-2.0+
18 */ 18 */
19 #include <common.h> 19 #include <common.h>
20 #include <dm.h>
21 #include <ns16550.h>
20 #include <twl4030.h> 22 #include <twl4030.h>
21 #include <asm/io.h> 23 #include <asm/io.h>
22 #include <asm/arch/mmc_host_def.h> 24 #include <asm/arch/mmc_host_def.h>
23 #include <asm/arch/mux.h> 25 #include <asm/arch/mux.h>
24 #include <asm/arch/sys_proto.h> 26 #include <asm/arch/sys_proto.h>
25 #include <asm/arch/mem.h> 27 #include <asm/arch/mem.h>
26 #include <asm/mach-types.h> 28 #include <asm/mach-types.h>
27 #include "devkit8000.h" 29 #include "devkit8000.h"
28 #include <asm/gpio.h> 30 #include <asm/gpio.h>
29 #ifdef CONFIG_DRIVER_DM9000 31 #ifdef CONFIG_DRIVER_DM9000
30 #include <net.h> 32 #include <net.h>
31 #include <netdev.h> 33 #include <netdev.h>
32 #endif 34 #endif
33 35
34 DECLARE_GLOBAL_DATA_PTR; 36 DECLARE_GLOBAL_DATA_PTR;
35 37
36 static u32 gpmc_net_config[GPMC_MAX_REG] = { 38 static u32 gpmc_net_config[GPMC_MAX_REG] = {
37 NET_GPMC_CONFIG1, 39 NET_GPMC_CONFIG1,
38 NET_GPMC_CONFIG2, 40 NET_GPMC_CONFIG2,
39 NET_GPMC_CONFIG3, 41 NET_GPMC_CONFIG3,
40 NET_GPMC_CONFIG4, 42 NET_GPMC_CONFIG4,
41 NET_GPMC_CONFIG5, 43 NET_GPMC_CONFIG5,
42 NET_GPMC_CONFIG6, 44 NET_GPMC_CONFIG6,
43 0 45 0
46 };
47
48 static const struct ns16550_platdata devkit8000_serial = {
49 OMAP34XX_UART3,
50 2,
51 V_NS16550_CLK
52 };
53
54 U_BOOT_DEVICE(devkit8000_uart) = {
55 "serial_omap",
56 &devkit8000_serial
44 }; 57 };
45 58
46 /* 59 /*
47 * Routine: board_init 60 * Routine: board_init
48 * Description: Early hardware init. 61 * Description: Early hardware init.
49 */ 62 */
50 int board_init(void) 63 int board_init(void)
51 { 64 {
52 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ 65 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
53 /* board id for Linux */ 66 /* board id for Linux */
54 gd->bd->bi_arch_number = MACH_TYPE_DEVKIT8000; 67 gd->bd->bi_arch_number = MACH_TYPE_DEVKIT8000;
55 /* boot param addr */ 68 /* boot param addr */
56 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); 69 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
57 70
58 return 0; 71 return 0;
59 } 72 }
60 73
61 /* Configure GPMC registers for DM9000 */ 74 /* Configure GPMC registers for DM9000 */
62 static void gpmc_dm9000_config(void) 75 static void gpmc_dm9000_config(void)
63 { 76 {
64 enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6], 77 enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6],
65 CONFIG_DM9000_BASE, GPMC_SIZE_16M); 78 CONFIG_DM9000_BASE, GPMC_SIZE_16M);
66 } 79 }
67 80
68 /* 81 /*
69 * Routine: misc_init_r 82 * Routine: misc_init_r
70 * Description: Configure board specific parts 83 * Description: Configure board specific parts
71 */ 84 */
72 int misc_init_r(void) 85 int misc_init_r(void)
73 { 86 {
74 struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE; 87 struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
75 #ifdef CONFIG_DRIVER_DM9000 88 #ifdef CONFIG_DRIVER_DM9000
76 uchar enetaddr[6]; 89 uchar enetaddr[6];
77 u32 die_id_0; 90 u32 die_id_0;
78 #endif 91 #endif
79 92
80 twl4030_power_init(); 93 twl4030_power_init();
81 #ifdef CONFIG_TWL4030_LED 94 #ifdef CONFIG_TWL4030_LED
82 twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); 95 twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
83 #endif 96 #endif
84 97
85 #ifdef CONFIG_DRIVER_DM9000 98 #ifdef CONFIG_DRIVER_DM9000
86 /* Configure GPMC registers for DM9000 */ 99 /* Configure GPMC registers for DM9000 */
87 enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6], 100 enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[6],
88 CONFIG_DM9000_BASE, GPMC_SIZE_16M); 101 CONFIG_DM9000_BASE, GPMC_SIZE_16M);
89 102
90 /* Use OMAP DIE_ID as MAC address */ 103 /* Use OMAP DIE_ID as MAC address */
91 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { 104 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
92 printf("ethaddr not set, using Die ID\n"); 105 printf("ethaddr not set, using Die ID\n");
93 die_id_0 = readl(&id_base->die_id_0); 106 die_id_0 = readl(&id_base->die_id_0);
94 enetaddr[0] = 0x02; /* locally administered */ 107 enetaddr[0] = 0x02; /* locally administered */
95 enetaddr[1] = readl(&id_base->die_id_1) & 0xff; 108 enetaddr[1] = readl(&id_base->die_id_1) & 0xff;
96 enetaddr[2] = (die_id_0 & 0xff000000) >> 24; 109 enetaddr[2] = (die_id_0 & 0xff000000) >> 24;
97 enetaddr[3] = (die_id_0 & 0x00ff0000) >> 16; 110 enetaddr[3] = (die_id_0 & 0x00ff0000) >> 16;
98 enetaddr[4] = (die_id_0 & 0x0000ff00) >> 8; 111 enetaddr[4] = (die_id_0 & 0x0000ff00) >> 8;
99 enetaddr[5] = (die_id_0 & 0x000000ff); 112 enetaddr[5] = (die_id_0 & 0x000000ff);
100 eth_setenv_enetaddr("ethaddr", enetaddr); 113 eth_setenv_enetaddr("ethaddr", enetaddr);
101 } 114 }
102 #endif 115 #endif
103 116
104 dieid_num_r(); 117 dieid_num_r();
105 118
106 return 0; 119 return 0;
107 } 120 }
108 121
109 /* 122 /*
110 * Routine: set_muxconf_regs 123 * Routine: set_muxconf_regs
111 * Description: Setting up the configuration Mux registers specific to the 124 * Description: Setting up the configuration Mux registers specific to the
112 * hardware. Many pins need to be moved from protect to primary 125 * hardware. Many pins need to be moved from protect to primary
113 * mode. 126 * mode.
114 */ 127 */
115 void set_muxconf_regs(void) 128 void set_muxconf_regs(void)
116 { 129 {
117 MUX_DEVKIT8000(); 130 MUX_DEVKIT8000();
118 } 131 }
119 132
120 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) 133 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
121 int board_mmc_init(bd_t *bis) 134 int board_mmc_init(bd_t *bis)
122 { 135 {
123 return omap_mmc_init(0, 0, 0, -1, -1); 136 return omap_mmc_init(0, 0, 0, -1, -1);
124 } 137 }
125 #endif 138 #endif
126 139
127 #if defined(CONFIG_GENERIC_MMC) 140 #if defined(CONFIG_GENERIC_MMC)
128 void board_mmc_power_init(void) 141 void board_mmc_power_init(void)
129 { 142 {
130 twl4030_power_mmc_init(0); 143 twl4030_power_mmc_init(0);
131 } 144 }
132 #endif 145 #endif
133 146
134 #if defined(CONFIG_DRIVER_DM9000) & !defined(CONFIG_SPL_BUILD) 147 #if defined(CONFIG_DRIVER_DM9000) & !defined(CONFIG_SPL_BUILD)
135 /* 148 /*
136 * Routine: board_eth_init 149 * Routine: board_eth_init
137 * Description: Setting up the Ethernet hardware. 150 * Description: Setting up the Ethernet hardware.
138 */ 151 */
139 int board_eth_init(bd_t *bis) 152 int board_eth_init(bd_t *bis)
140 { 153 {
141 return dm9000_initialize(bis); 154 return dm9000_initialize(bis);
142 } 155 }
143 #endif 156 #endif
144 157
145 #ifdef CONFIG_SPL_OS_BOOT 158 #ifdef CONFIG_SPL_OS_BOOT
146 /* 159 /*
147 * Do board specific preperation before SPL 160 * Do board specific preperation before SPL
148 * Linux boot 161 * Linux boot
149 */ 162 */
150 void spl_board_prepare_for_linux(void) 163 void spl_board_prepare_for_linux(void)
151 { 164 {
152 gpmc_dm9000_config(); 165 gpmc_dm9000_config();
153 } 166 }
154 167
155 /* 168 /*
156 * devkit8000 specific implementation of spl_start_uboot() 169 * devkit8000 specific implementation of spl_start_uboot()
157 * 170 *
158 * RETURN 171 * RETURN
159 * 0 if the button is not pressed 172 * 0 if the button is not pressed
160 * 1 if the button is pressed 173 * 1 if the button is pressed
161 */ 174 */
162 int spl_start_uboot(void) 175 int spl_start_uboot(void)
163 { 176 {
164 int val = 0; 177 int val = 0;
165 if (!gpio_request(SPL_OS_BOOT_KEY, "U-Boot key")) { 178 if (!gpio_request(SPL_OS_BOOT_KEY, "U-Boot key")) {
166 gpio_direction_input(SPL_OS_BOOT_KEY); 179 gpio_direction_input(SPL_OS_BOOT_KEY);
167 val = gpio_get_value(SPL_OS_BOOT_KEY); 180 val = gpio_get_value(SPL_OS_BOOT_KEY);
168 gpio_free(SPL_OS_BOOT_KEY); 181 gpio_free(SPL_OS_BOOT_KEY);
169 } 182 }
170 return !val; 183 return !val;
171 } 184 }
172 #endif 185 #endif
173 186
174 /* 187 /*
175 * Routine: get_board_mem_timings 188 * Routine: get_board_mem_timings
176 * Description: If we use SPL then there is no x-loader nor config header 189 * Description: If we use SPL then there is no x-loader nor config header
177 * so we have to setup the DDR timings ourself on the first bank. This 190 * so we have to setup the DDR timings ourself on the first bank. This
178 * provides the timing values back to the function that configures 191 * provides the timing values back to the function that configures
179 * the memory. We have either one or two banks of 128MB DDR. 192 * the memory. We have either one or two banks of 128MB DDR.
180 */ 193 */
181 void get_board_mem_timings(struct board_sdrc_timings *timings) 194 void get_board_mem_timings(struct board_sdrc_timings *timings)
182 { 195 {
183 /* General SDRC config */ 196 /* General SDRC config */
184 timings->mcfg = MICRON_V_MCFG_165(128 << 20); 197 timings->mcfg = MICRON_V_MCFG_165(128 << 20);
185 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 198 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
186 199
187 /* AC timings */ 200 /* AC timings */
188 timings->ctrla = MICRON_V_ACTIMA_165; 201 timings->ctrla = MICRON_V_ACTIMA_165;
189 timings->ctrlb = MICRON_V_ACTIMB_165; 202 timings->ctrlb = MICRON_V_ACTIMB_165;
190 203
191 timings->mr = MICRON_V_MR_165; 204 timings->mr = MICRON_V_MR_165;
192 } 205 }
193 206
include/configs/devkit8000.h
Diff comments   View file @ a91ef4a
1 /* 1 /*
2 * (C) Copyright 2006-2008 2 * (C) Copyright 2006-2008
3 * Texas Instruments. 3 * Texas Instruments.
4 * Richard Woodruff <r-woodruff2@ti.com> 4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com> 5 * Syed Mohammed Khasim <x0khasim@ti.com>
6 * 6 *
7 * (C) Copyright 2009 7 * (C) Copyright 2009
8 * Frederik Kriewitz <frederik@kriewitz.eu> 8 * Frederik Kriewitz <frederik@kriewitz.eu>
9 * 9 *
10 * Configuration settings for the DevKit8000 board. 10 * Configuration settings for the DevKit8000 board.
11 * 11 *
12 * SPDX-License-Identifier: GPL-2.0+ 12 * SPDX-License-Identifier: GPL-2.0+
13 */ 13 */
14 14
15 #ifndef __CONFIG_H 15 #ifndef __CONFIG_H
16 #define __CONFIG_H 16 #define __CONFIG_H
17 17
18 /* High Level Configuration Options */ 18 /* High Level Configuration Options */
19 #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */ 19 #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */
20 #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000 20 #define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000
21 21
22 /* 22 /*
23 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 23 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
24 * 64 bytes before this address should be set aside for u-boot.img's 24 * 64 bytes before this address should be set aside for u-boot.img's
25 * header. That is 0x800FFFC0--0x80100000 should not be used for any 25 * header. That is 0x800FFFC0--0x80100000 should not be used for any
26 * other needs. 26 * other needs.
27 */ 27 */
28 #define CONFIG_SYS_TEXT_BASE 0x80100000 28 #define CONFIG_SYS_TEXT_BASE 0x80100000
29 29
30 #define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/ 30 #define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/
31 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 31 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
32 32
33 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 33 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
34 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ 34 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
35 35
36 #include <asm/arch/cpu.h> /* get chip and board defs */
37 #include <asm/arch/omap3.h>
38
39 #define CONFIG_SDRC /* The chip has SDRC controller */
40 #define CONFIG_NAND 36 #define CONFIG_NAND
41 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
42 /* to access nand at */
43 /* CS0 */
44 37
45 /* Physical Memory Map */ 38 /* Physical Memory Map */
46 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 39 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
47 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
48 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
49 40
50 #include <configs/ti_armv7_common.h> 41 #include <configs/ti_omap3_common.h>
51 42
52 /* Display CPU and Board information */ 43 /* Display CPU and Board information */
53 #define CONFIG_DISPLAY_CPUINFO 1 44 #define CONFIG_DISPLAY_CPUINFO 1
54 #define CONFIG_DISPLAY_BOARDINFO 1 45 #define CONFIG_DISPLAY_BOARDINFO 1
55 46
56 /* Clock Defines */
57 #define V_OSCK 26000000 /* Clock output from T2 */
58 #define V_SCLK (V_OSCK >> 1)
59
60 #define CONFIG_MISC_INIT_R 47 #define CONFIG_MISC_INIT_R
61 48
62 #define CONFIG_REVISION_TAG 1 49 #define CONFIG_REVISION_TAG 1
63 50
64 /* Size of malloc() pool */ 51 /* Size of malloc() pool */
65 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 52 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
66 /* Sector */ 53 /* Sector */
67 #undef CONFIG_SYS_MALLOC_LEN 54 #undef CONFIG_SYS_MALLOC_LEN
68 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 55 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
69 56
70 /* Hardware drivers */ 57 /* Hardware drivers */
71 /* DM9000 */ 58 /* DM9000 */
72 #define CONFIG_NET_RETRY_COUNT 20 59 #define CONFIG_NET_RETRY_COUNT 20
73 #define CONFIG_DRIVER_DM9000 1 60 #define CONFIG_DRIVER_DM9000 1
74 #define CONFIG_DM9000_BASE 0x2c000000 61 #define CONFIG_DM9000_BASE 0x2c000000
75 #define DM9000_IO CONFIG_DM9000_BASE 62 #define DM9000_IO CONFIG_DM9000_BASE
76 #define DM9000_DATA (CONFIG_DM9000_BASE + 0x400) 63 #define DM9000_DATA (CONFIG_DM9000_BASE + 0x400)
77 #define CONFIG_DM9000_USE_16BIT 1 64 #define CONFIG_DM9000_USE_16BIT 1
78 #define CONFIG_DM9000_NO_SROM 1 65 #define CONFIG_DM9000_NO_SROM 1
79 #undef CONFIG_DM9000_DEBUG 66 #undef CONFIG_DM9000_DEBUG
80 67
81 /* NS16550 Configuration */
82 #define CONFIG_SYS_NS16550
83 #define CONFIG_SYS_NS16550_SERIAL
84 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
85 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
86
87 /* select serial console configuration */
88 #define CONFIG_CONS_INDEX 3
89 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
90 #define CONFIG_SERIAL3 3
91 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
92 115200}
93
94 /* SPI */ 68 /* SPI */
95 #undef CONFIG_SPI 69 #undef CONFIG_SPI
96 #undef CONFIG_OMAP3_SPI 70 #undef CONFIG_OMAP3_SPI
97 71
98 /* I2C */ 72 /* I2C */
99 #undef CONFIG_SYS_I2C_OMAP24XX 73 #undef CONFIG_SYS_I2C_OMAP24XX
100 #define CONFIG_SYS_I2C_OMAP34XX 74 #define CONFIG_SYS_I2C_OMAP34XX
101 75
102 /* TWL4030 */ 76 /* TWL4030 */
103 #define CONFIG_TWL4030_POWER 1
104 #define CONFIG_TWL4030_LED 1 77 #define CONFIG_TWL4030_LED 1
105 78
106 /* Board NAND Info */ 79 /* Board NAND Info */
107 #define MTDIDS_DEFAULT "nand0=nand" 80 #define MTDIDS_DEFAULT "nand0=nand"
108 #define MTDPARTS_DEFAULT "mtdparts=nand:" \ 81 #define MTDPARTS_DEFAULT "mtdparts=nand:" \
109 "512k(x-loader)," \ 82 "512k(x-loader)," \
110 "1920k(u-boot)," \ 83 "1920k(u-boot)," \
111 "128k(u-boot-env)," \ 84 "128k(u-boot-env)," \
112 "4m(kernel)," \ 85 "4m(kernel)," \
113 "-(fs)" 86 "-(fs)"
114 87
115 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 88 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
116 /* to access nand */ 89 /* to access nand */
117 #define CONFIG_JFFS2_NAND 90 #define CONFIG_JFFS2_NAND
118 /* nand device jffs2 lives on */ 91 /* nand device jffs2 lives on */
119 #define CONFIG_JFFS2_DEV "nand0" 92 #define CONFIG_JFFS2_DEV "nand0"
120 /* start of jffs2 partition */ 93 /* start of jffs2 partition */
121 #define CONFIG_JFFS2_PART_OFFSET 0x680000 94 #define CONFIG_JFFS2_PART_OFFSET 0x680000
122 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ 95 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
123 /* partition */ 96 /* partition */
124 97
125 /* commands to include */ 98 /* commands to include */
126 #define CONFIG_CMD_DHCP /* DHCP support */ 99 #define CONFIG_CMD_DHCP /* DHCP support */
127 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 100 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
128 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ 101 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
129 102
130 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 103 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
131 #undef CONFIG_CMD_IMI /* iminfo */ 104 #undef CONFIG_CMD_IMI /* iminfo */
132 #undef CONFIG_CMD_SPI 105 #undef CONFIG_CMD_SPI
133 #undef CONFIG_CMD_GPIO 106 #undef CONFIG_CMD_GPIO
134 #undef CONFIG_CMD_ASKENV 107 #undef CONFIG_CMD_ASKENV
135 #undef CONFIG_CMD_BOOTZ 108 #undef CONFIG_CMD_BOOTZ
136 #undef CONFIG_SUPPORT_RAW_INITRD 109 #undef CONFIG_SUPPORT_RAW_INITRD
137 #undef CONFIG_FAT_WRITE 110 #undef CONFIG_FAT_WRITE
138 #undef CONFIG_CMD_EXT4 111 #undef CONFIG_CMD_EXT4
139 #undef CONFIG_CMD_FS_GENERIC 112 #undef CONFIG_CMD_FS_GENERIC
140 113
141 /* BOOTP/DHCP options */ 114 /* BOOTP/DHCP options */
142 #define CONFIG_BOOTP_SUBNETMASK 115 #define CONFIG_BOOTP_SUBNETMASK
143 #define CONFIG_BOOTP_GATEWAY 116 #define CONFIG_BOOTP_GATEWAY
144 #define CONFIG_BOOTP_HOSTNAME 117 #define CONFIG_BOOTP_HOSTNAME
145 #define CONFIG_BOOTP_NISDOMAIN 118 #define CONFIG_BOOTP_NISDOMAIN
146 #define CONFIG_BOOTP_BOOTPATH 119 #define CONFIG_BOOTP_BOOTPATH
147 #define CONFIG_BOOTP_BOOTFILESIZE 120 #define CONFIG_BOOTP_BOOTFILESIZE
148 #define CONFIG_BOOTP_DNS 121 #define CONFIG_BOOTP_DNS
149 #define CONFIG_BOOTP_DNS2 122 #define CONFIG_BOOTP_DNS2
150 #define CONFIG_BOOTP_SEND_HOSTNAME 123 #define CONFIG_BOOTP_SEND_HOSTNAME
151 #define CONFIG_BOOTP_NTPSERVER 124 #define CONFIG_BOOTP_NTPSERVER
152 #define CONFIG_BOOTP_TIMEOFFSET 125 #define CONFIG_BOOTP_TIMEOFFSET
153 #undef CONFIG_BOOTP_VENDOREX 126 #undef CONFIG_BOOTP_VENDOREX
154 127
155 /* Environment information */ 128 /* Environment information */
156 #define CONFIG_EXTRA_ENV_SETTINGS \ 129 #define CONFIG_EXTRA_ENV_SETTINGS \
157 "loadaddr=0x82000000\0" \ 130 "loadaddr=0x82000000\0" \
158 "console=ttyO2,115200n8\0" \ 131 "console=ttyO2,115200n8\0" \
159 "mmcdev=0\0" \ 132 "mmcdev=0\0" \
160 "vram=12M\0" \ 133 "vram=12M\0" \
161 "dvimode=1024x768MR-16@60\0" \ 134 "dvimode=1024x768MR-16@60\0" \
162 "defaultdisplay=dvi\0" \ 135 "defaultdisplay=dvi\0" \
163 "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \ 136 "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
164 "kernelopts=rw\0" \ 137 "kernelopts=rw\0" \
165 "commonargs=" \ 138 "commonargs=" \
166 "setenv bootargs console=${console} " \ 139 "setenv bootargs console=${console} " \
167 "vram=${vram} " \ 140 "vram=${vram} " \
168 "omapfb.mode=dvi:${dvimode} " \ 141 "omapfb.mode=dvi:${dvimode} " \
169 "omapdss.def_disp=${defaultdisplay}\0" \ 142 "omapdss.def_disp=${defaultdisplay}\0" \
170 "mmcargs=" \ 143 "mmcargs=" \
171 "run commonargs; " \ 144 "run commonargs; " \
172 "setenv bootargs ${bootargs} " \ 145 "setenv bootargs ${bootargs} " \
173 "root=/dev/mmcblk0p2 " \ 146 "root=/dev/mmcblk0p2 " \
174 "rootwait " \ 147 "rootwait " \
175 "${kernelopts}\0" \ 148 "${kernelopts}\0" \
176 "nandargs=" \ 149 "nandargs=" \
177 "run commonargs; " \ 150 "run commonargs; " \
178 "setenv bootargs ${bootargs} " \ 151 "setenv bootargs ${bootargs} " \
179 "omapfb.mode=dvi:${dvimode} " \ 152 "omapfb.mode=dvi:${dvimode} " \
180 "omapdss.def_disp=${defaultdisplay} " \ 153 "omapdss.def_disp=${defaultdisplay} " \
181 "root=/dev/mtdblock4 " \ 154 "root=/dev/mtdblock4 " \
182 "rootfstype=jffs2 " \ 155 "rootfstype=jffs2 " \
183 "${kernelopts}\0" \ 156 "${kernelopts}\0" \
184 "netargs=" \ 157 "netargs=" \
185 "run commonargs; " \ 158 "run commonargs; " \
186 "setenv bootargs ${bootargs} " \ 159 "setenv bootargs ${bootargs} " \
187 "root=/dev/nfs " \ 160 "root=/dev/nfs " \
188 "nfsroot=${serverip}:${rootpath},${nfsopts} " \ 161 "nfsroot=${serverip}:${rootpath},${nfsopts} " \
189 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \ 162 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
190 "${kernelopts} " \ 163 "${kernelopts} " \
191 "dnsip1=${dnsip} " \ 164 "dnsip1=${dnsip} " \
192 "dnsip2=${dnsip2}\0" \ 165 "dnsip2=${dnsip2}\0" \
193 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 166 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
194 "bootscript=echo Running bootscript from mmc ...; " \ 167 "bootscript=echo Running bootscript from mmc ...; " \
195 "source ${loadaddr}\0" \ 168 "source ${loadaddr}\0" \
196 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 169 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
197 "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \ 170 "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
198 "mmcboot=echo Booting from mmc ...; " \ 171 "mmcboot=echo Booting from mmc ...; " \
199 "run mmcargs; " \ 172 "run mmcargs; " \
200 "bootm ${loadaddr}\0" \ 173 "bootm ${loadaddr}\0" \
201 "nandboot=echo Booting from nand ...; " \ 174 "nandboot=echo Booting from nand ...; " \
202 "run nandargs; " \ 175 "run nandargs; " \
203 "nand read ${loadaddr} 280000 400000; " \ 176 "nand read ${loadaddr} 280000 400000; " \
204 "bootm ${loadaddr}\0" \ 177 "bootm ${loadaddr}\0" \
205 "netboot=echo Booting from network ...; " \ 178 "netboot=echo Booting from network ...; " \
206 "dhcp ${loadaddr}; " \ 179 "dhcp ${loadaddr}; " \
207 "run netargs; " \ 180 "run netargs; " \
208 "bootm ${loadaddr}\0" \ 181 "bootm ${loadaddr}\0" \
209 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ 182 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
210 "if run loadbootscript; then " \ 183 "if run loadbootscript; then " \
211 "run bootscript; " \ 184 "run bootscript; " \
212 "else " \ 185 "else " \
213 "if run loaduimage; then " \ 186 "if run loaduimage; then " \
214 "run mmcboot; " \ 187 "run mmcboot; " \
215 "else run nandboot; " \ 188 "else run nandboot; " \
216 "fi; " \ 189 "fi; " \
217 "fi; " \ 190 "fi; " \
218 "else run nandboot; fi\0" 191 "else run nandboot; fi\0"
219 192
220 193
221 #define CONFIG_BOOTCOMMAND "run autoboot" 194 #define CONFIG_BOOTCOMMAND "run autoboot"
222 195
223 /* Boot Argument Buffer Size */ 196 /* Boot Argument Buffer Size */
224 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000) 197 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000)
225 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 198 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
226 0x01000000) /* 16MB */ 199 0x01000000) /* 16MB */
227 200
228 /*
229 * OMAP3 has 12 GP timers, they can be driven by the system clock
230 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
231 * This rate is divided by a local divisor.
232 */
233 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
234
235 /* NAND and environment organization */ 201 /* NAND and environment organization */
236 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
237
238 #define CONFIG_ENV_IS_IN_NAND 1 202 #define CONFIG_ENV_IS_IN_NAND 1
239 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 203 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
240 204
241 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 205 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
242 206
243 /* SRAM config */ 207 /* SRAM config */
244 #define CONFIG_SYS_SRAM_START 0x40200000 208 #define CONFIG_SYS_SRAM_START 0x40200000
245 #define CONFIG_SYS_SRAM_SIZE 0x10000 209 #define CONFIG_SYS_SRAM_SIZE 0x10000
246 210
247 /* Defines for SPL */ 211 /* Defines for SPL */
248 #define CONFIG_SPL_NAND_SIMPLE
249
250 #define CONFIG_SPL_POWER_SUPPORT
251 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
252 #undef CONFIG_SPL_MTD_SUPPORT 212 #undef CONFIG_SPL_MTD_SUPPORT
253 213
214 #undef CONFIG_SPL_TEXT_BASE
254 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ 215 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
255 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
256 #undef CONFIG_SPL_STACK 216 #undef CONFIG_SPL_STACK
257 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK 217 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
258 218
259 /* NAND boot config */ 219 /* NAND boot config */
260 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 220 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
261 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 221 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
262 #define CONFIG_SYS_NAND_PAGE_COUNT 64 222 #define CONFIG_SYS_NAND_PAGE_COUNT 64
263 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 223 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
264 #define CONFIG_SYS_NAND_OOBSIZE 64 224 #define CONFIG_SYS_NAND_OOBSIZE 64
265 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 225 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
266 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 226 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
267 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 227 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
268 10, 11, 12, 13} 228 10, 11, 12, 13}
269 229
270 #define CONFIG_SYS_NAND_ECCSIZE 512 230 #define CONFIG_SYS_NAND_ECCSIZE 512
271 #define CONFIG_SYS_NAND_ECCBYTES 3 231 #define CONFIG_SYS_NAND_ECCBYTES 3
272 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 232 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
273 233
274 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 234 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
275 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000 235 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000
276 236
277 /* SPL OS boot options */ 237 /* SPL OS boot options */
278 #define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */ 238 #define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */
279 #define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\ 239 #define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\
280 0x400000) 240 0x400000)
281 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 241 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
282 242
283 #undef CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 243 #undef CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
284 #undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 244 #undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR
285 #undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 245 #undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
286 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */ 246 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */
287 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */ 247 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */
288 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */ 248 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */
289 249
250 #undef CONFIG_SYS_SPL_ARGS_ADDR
290 #define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100) 251 #define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100)
291 252