arm: omap3: devkit8000: inherit from ti_omap3_common.h

Signed-off-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>

arm: omap3: devkit8000: inherit from ti_omap3_common.h
Signed-off-by: Anthoine Bourgeois <anthoine.bourgeois@gmail.com>
Anthoine Bourgeois · Tom Rini
1 parent 875e415492
Showing 2 changed files with 16 additions and 42 deletions Side-by-side Diff
board/timll/devkit8000/devkit8000.c
include/configs/devkit8000.h
@@ -17,6 +17,8 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
+#include <dm.h>
+#include <ns16550.h>
 #include <twl4030.h>
 #include <asm/io.h>
 #include <asm/arch/mmc_host_def.h>
@@ -41,6 +43,17 @@
 	NET_GPMC_CONFIG5,
 	NET_GPMC_CONFIG6,
 	0
+};
+
+static const struct ns16550_platdata devkit8000_serial = {
+	OMAP34XX_UART3,
+	2,
+	V_NS16550_CLK
+};
+
+U_BOOT_DEVICE(devkit8000_uart) = {
+	"serial_omap",
+	&devkit8000_serial
 };
  
 /*
@@ -33,30 +33,17 @@
 #define CONFIG_SYS_SPL_MALLOC_START	0x80208000
 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000	/* 1 MB */
  
-#include <asm/arch/cpu.h>		/* get chip and board defs */
-#include <asm/arch/omap3.h>
-
-#define CONFIG_SDRC	/* The chip has SDRC controller */
 #define CONFIG_NAND
-#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
-							/* to access nand at */
-							/* CS0 */
  
 /*  Physical Memory Map  */
 #define CONFIG_NR_DRAM_BANKS		2 /* CS1 may or may not be populated */
-#define PHYS_SDRAM_1			OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_2			OMAP34XX_SDRC_CS1
  
-#include <configs/ti_armv7_common.h>
+#include <configs/ti_omap3_common.h>
  
 /* Display CPU and Board information */
 #define CONFIG_DISPLAY_CPUINFO		1
 #define CONFIG_DISPLAY_BOARDINFO	1
  
-/* Clock Defines */
-#define V_OSCK				26000000	/* Clock output from T2 */
-#define V_SCLK				(V_OSCK >> 1)
-
 #define CONFIG_MISC_INIT_R
  
 #define CONFIG_REVISION_TAG		1
@@ -78,19 +65,6 @@
 #define CONFIG_DM9000_NO_SROM		1
 #undef	CONFIG_DM9000_DEBUG
  
-/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		48000000 /* 48MHz (APLL96/2) */
-
-/* select serial console configuration */
-#define CONFIG_CONS_INDEX		3
-#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
-#define CONFIG_SERIAL3			3
-#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
-					115200}
-
 /* SPI */
 #undef CONFIG_SPI
 #undef CONFIG_OMAP3_SPI
@@ -100,7 +74,6 @@
 #define CONFIG_SYS_I2C_OMAP34XX
  
 /* TWL4030 */
-#define CONFIG_TWL4030_POWER		1
 #define CONFIG_TWL4030_LED		1
  
 /* Board NAND Info */
  
@@ -225,16 +198,7 @@
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
 					0x01000000) /* 16MB */
  
-/*
- * OMAP3 has 12 GP timers, they can be driven by the system clock
- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- * This rate is divided by a local divisor.
- */
-#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
-
 /* NAND and environment organization  */
-#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
-
 #define CONFIG_ENV_IS_IN_NAND		1
 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
  
  
  
@@ -245,14 +209,10 @@
 #define CONFIG_SYS_SRAM_SIZE               0x10000
  
 /* Defines for SPL */
-#define CONFIG_SPL_NAND_SIMPLE
-
-#define CONFIG_SPL_POWER_SUPPORT
-#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
 #undef CONFIG_SPL_MTD_SUPPORT
  
+#undef CONFIG_SPL_TEXT_BASE
 #define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
-#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
 #undef CONFIG_SPL_STACK
 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
  
@@ -287,6 +247,7 @@
 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR	0x8   /* address 0x1000 */
 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS	8     /* 4KB */
  
+#undef CONFIG_SYS_SPL_ARGS_ADDR
 #define CONFIG_SYS_SPL_ARGS_ADDR        (PHYS_SDRAM_1 + 0x100)
  
 #endif /* __CONFIG_H */
...	...	@@ -17,6 +17,8 @@
17	17	* SPDX-License-Identifier: GPL-2.0+
18	18	*/
19	19	#include <common.h>
	20	+#include <dm.h>
	21	+#include <ns16550.h>
20	22	#include <twl4030.h>
21	23	#include <asm/io.h>
22	24	#include <asm/arch/mmc_host_def.h>
...	...	@@ -41,6 +43,17 @@
41	43	NET_GPMC_CONFIG5,
42	44	NET_GPMC_CONFIG6,
43	45	0
	46	+};
	47	+
	48	+static const struct ns16550_platdata devkit8000_serial = {
	49	+ OMAP34XX_UART3,
	50	+ 2,
	51	+ V_NS16550_CLK
	52	+};
	53	+
	54	+U_BOOT_DEVICE(devkit8000_uart) = {
	55	+ "serial_omap",
	56	+ &devkit8000_serial
44	57	};
45	58
46	59	/*
...	...	@@ -33,30 +33,17 @@
33	33	#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
34	34	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
35	35
36		-#include <asm/arch/cpu.h> /* get chip and board defs */
37		-#include <asm/arch/omap3.h>
38		-
39		-#define CONFIG_SDRC /* The chip has SDRC controller */
40	36	#define CONFIG_NAND
41		-#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
42		- /* to access nand at */
43		- /* CS0 */
44	37
45	38	/* Physical Memory Map */
46	39	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
47		-#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
48		-#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
49	40
50		-#include <configs/ti_armv7_common.h>
	41	+#include <configs/ti_omap3_common.h>
51	42
52	43	/* Display CPU and Board information */
53	44	#define CONFIG_DISPLAY_CPUINFO 1
54	45	#define CONFIG_DISPLAY_BOARDINFO 1
55	46
56		-/* Clock Defines */
57		-#define V_OSCK 26000000 /* Clock output from T2 */
58		-#define V_SCLK (V_OSCK >> 1)
59		-
60	47	#define CONFIG_MISC_INIT_R
61	48
62	49	#define CONFIG_REVISION_TAG 1
...	...	@@ -78,19 +65,6 @@
78	65	#define CONFIG_DM9000_NO_SROM 1
79	66	#undef CONFIG_DM9000_DEBUG
80	67
81		-/* NS16550 Configuration */
82		-#define CONFIG_SYS_NS16550
83		-#define CONFIG_SYS_NS16550_SERIAL
84		-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
85		-#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
86		-
87		-/* select serial console configuration */
88		-#define CONFIG_CONS_INDEX 3
89		-#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
90		-#define CONFIG_SERIAL3 3
91		-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
92		- 115200}
93		-
94	68	/* SPI */
95	69	#undef CONFIG_SPI
96	70	#undef CONFIG_OMAP3_SPI
...	...	@@ -100,7 +74,6 @@
100	74	#define CONFIG_SYS_I2C_OMAP34XX
101	75
102	76	/* TWL4030 */
103		-#define CONFIG_TWL4030_POWER 1
104	77	#define CONFIG_TWL4030_LED 1
105	78
106	79	/* Board NAND Info */
107	80
...	...	@@ -225,16 +198,7 @@
225	198	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
226	199	0x01000000) /* 16MB */
227	200
228		-/*
229		- * OMAP3 has 12 GP timers, they can be driven by the system clock
230		- * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
231		- * This rate is divided by a local divisor.
232		- */
233		-#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
234		-
235	201	/* NAND and environment organization */
236		-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
237		-
238	202	#define CONFIG_ENV_IS_IN_NAND 1
239	203	#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
240	204
241	205
242	206
...	...	@@ -245,14 +209,10 @@
245	209	#define CONFIG_SYS_SRAM_SIZE 0x10000
246	210
247	211	/* Defines for SPL */
248		-#define CONFIG_SPL_NAND_SIMPLE
249		-
250		-#define CONFIG_SPL_POWER_SUPPORT
251		-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
252	212	#undef CONFIG_SPL_MTD_SUPPORT
253	213
	214	+#undef CONFIG_SPL_TEXT_BASE
254	215	#define CONFIG_SPL_TEXT_BASE 0x40200000 /CONFIG_SYS_SRAM_START/
255		-#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
256	216	#undef CONFIG_SPL_STACK
257	217	#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
258	218
...	...	@@ -287,6 +247,7 @@
287	247	#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */
288	248	#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */
289	249
	250	+#undef CONFIG_SYS_SPL_ARGS_ADDR
290	251	#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100)
291	252
292	253	#endif /* __CONFIG_H */