Commit a994b3deb00bf3177cdf9f92060baec4f640f466
Committed by
York Sun
York Sun
1 parent
6f14e257c4
Exists in
v2017.01-smarct4x
and in
30 other branches
driver/ddr/fsl: Add workaround for A009663
Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0 before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE] to the desired value after DDR initialization has completed. When DDR controller is configured to operate in auto-precharge mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
Showing 6 changed files with 20 additions and 0 deletions Side-by-side Diff
arch/arm/include/asm/arch-fsl-layerscape/config.h
| ... | ... | @@ -118,7 +118,9 @@ |
| 118 | 118 | #define CONFIG_SYS_FSL_ERRATUM_A008585 |
| 119 | 119 | #define CONFIG_SYS_FSL_ERRATUM_A008751 |
| 120 | 120 | #define CONFIG_SYS_FSL_ERRATUM_A009635 |
| 121 | +#define CONFIG_SYS_FSL_ERRATUM_A009663 | |
| 121 | 122 | #define CONFIG_SYS_FSL_ERRATUM_A009942 |
| 123 | + | |
| 122 | 124 | #elif defined(CONFIG_LS1043A) |
| 123 | 125 | #define CONFIG_MAX_CPUS 4 |
| 124 | 126 | #define CONFIG_SYS_CACHELINE_SIZE 64 |
| ... | ... | @@ -167,6 +169,7 @@ |
| 167 | 169 | #define GICD_BASE 0x01401000 |
| 168 | 170 | #define GICC_BASE 0x01402000 |
| 169 | 171 | |
| 172 | +#define CONFIG_SYS_FSL_ERRATUM_A009663 | |
| 170 | 173 | #define CONFIG_SYS_FSL_ERRATUM_A009929 |
| 171 | 174 | #else |
| 172 | 175 | #error SoC not defined |
arch/arm/include/asm/arch-ls102xa/config.h
arch/powerpc/cpu/mpc85xx/cmd_errata.c
| ... | ... | @@ -326,6 +326,9 @@ |
| 326 | 326 | #if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR) && defined(CONFIG_B4860QDS) |
| 327 | 327 | puts("Work-around for Erratum XFI on B4860QDS enabled\n"); |
| 328 | 328 | #endif |
| 329 | +#ifdef CONFIG_SYS_FSL_ERRATUM_A009663 | |
| 330 | + puts("Work-around for Erratum A009663 enabled\n"); | |
| 331 | +#endif | |
| 329 | 332 | |
| 330 | 333 | return 0; |
| 331 | 334 | } |
arch/powerpc/include/asm/config_mpc85xx.h
| ... | ... | @@ -808,6 +808,7 @@ |
| 808 | 808 | #define QE_NUM_OF_SNUM 28 |
| 809 | 809 | #define CONFIG_SYS_FSL_SFP_VER_3_0 |
| 810 | 810 | #define CONFIG_SYS_FSL_ERRATUM_A008378 |
| 811 | +#define CONFIG_SYS_FSL_ERRATUM_A009663 | |
| 811 | 812 | |
| 812 | 813 | #elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\ |
| 813 | 814 | defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) |
| ... | ... | @@ -856,6 +857,7 @@ |
| 856 | 857 | #define QE_NUM_OF_SNUM 28 |
| 857 | 858 | #define CONFIG_SYS_FSL_SFP_VER_3_0 |
| 858 | 859 | #define CONFIG_SYS_FSL_ERRATUM_A008378 |
| 860 | +#define CONFIG_SYS_FSL_ERRATUM_A009663 | |
| 859 | 861 | |
| 860 | 862 | #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) |
| 861 | 863 | #define CONFIG_E6500 |
drivers/ddr/fsl/fsl_ddr_gen4.c
| ... | ... | @@ -155,7 +155,12 @@ |
| 155 | 155 | ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15); |
| 156 | 156 | ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16); |
| 157 | 157 | ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); |
| 158 | +#ifdef CONFIG_SYS_FSL_ERRATUM_A009663 | |
| 159 | + ddr_out32(&ddr->sdram_interval, | |
| 160 | + regs->ddr_sdram_interval & ~SDRAM_INTERVAL_BSTOPRE); | |
| 161 | +#else | |
| 158 | 162 | ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); |
| 163 | +#endif | |
| 159 | 164 | ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); |
| 160 | 165 | ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); |
| 161 | 166 | #ifndef CONFIG_SYS_FSL_DDR_EMU |
| ... | ... | @@ -397,6 +402,11 @@ |
| 397 | 402 | |
| 398 | 403 | if (timeout <= 0) |
| 399 | 404 | printf("Waiting for D_INIT timeout. Memory may not work.\n"); |
| 405 | + | |
| 406 | +#ifdef CONFIG_SYS_FSL_ERRATUM_A009663 | |
| 407 | + ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); | |
| 408 | +#endif | |
| 409 | + | |
| 400 | 410 | #ifdef CONFIG_DEEP_SLEEP |
| 401 | 411 | if (is_warm_boot()) { |
| 402 | 412 | /* exit self-refresh */ |
include/fsl_ddr_sdram.h