Eric Lee / smarc-uboot

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Commit aa04fef49c70f2eb48365cb2fd8e344a237e93a7

Authored by Marek Vasut
Committed by Stefano Babic
1 parent e24278aff2
Exists in master and in 53 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ARM: mxs: Add Creative ZEN XFi3 board 

Add STMP3780-based XFi3 board. This board is a small PMP device
sporting a CPU which was later rebranded to i.MX233 . Currently
supported is USB gadget mode and both external SD and internal
Phison SD-NAND bridge .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>

Showing 6 changed files with 460 additions and 0 deletions Side-by-side Diff

... ... @@ -980,6 +980,7 @@
980 980 vpac270 xscale/pxa
981 981 zipitz2 xscale/pxa
982 982 mx23_olinuxino i.MX23
  983 + xfi3 i.MX23
983 984 m28evk i.MX28
984 985 sc_sps_1 i.MX28
985 986 m53evk i.MX53
board/creative/xfi3/Makefile
Diff comments   View file @ aa04fef
  1 +#
  2 +# (C) Copyright 2000-2006
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# SPDX-License-Identifier: GPL-2.0+
  6 +#
  7 +
  8 +include $(TOPDIR)/config.mk
  9 +
  10 +LIB = $(obj)lib$(BOARD).o
  11 +
  12 +ifndef CONFIG_SPL_BUILD
  13 +COBJS := xfi3.o
  14 +else
  15 +COBJS := spl_boot.o
  16 +endif
  17 +
  18 +SRCS := $(COBJS:.o=.c)
  19 +OBJS := $(addprefix $(obj),$(COBJS))
  20 +
  21 +$(LIB): $(obj).depend $(OBJS)
  22 + $(call cmd_link_o_target, $(OBJS))
  23 +
  24 +#########################################################################
  25 +
  26 +# defines $(obj).depend target
  27 +include $(SRCTREE)/rules.mk
  28 +
  29 +sinclude $(obj).depend
  30 +
  31 +#########################################################################
board/creative/xfi3/spl_boot.c
Diff comments   View file @ aa04fef
  1 +/*
  2 + * Creative ZEN X-Fi3 setup
  3 + *
  4 + * Copyright (C) 2013 Marek Vasut <marex@denx.de>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <config.h>
  11 +#include <asm/io.h>
  12 +#include <asm/arch/iomux-mx23.h>
  13 +#include <asm/arch/imx-regs.h>
  14 +#include <asm/arch/sys_proto.h>
  15 +
  16 +#define MUX_CONFIG_EMI (MXS_PAD_1V8 | MXS_PAD_12MA | MXS_PAD_PULLUP)
  17 +#define MUX_CONFIG_SSP (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
  18 +#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
  19 +
  20 +const iomux_cfg_t iomux_setup[] = {
  21 + /* EMI */
  22 + MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI,
  23 + MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI,
  24 + MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI,
  25 + MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI,
  26 + MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI,
  27 + MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI,
  28 + MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI,
  29 + MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI,
  30 + MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI,
  31 + MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI,
  32 + MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI,
  33 + MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI,
  34 + MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI,
  35 + MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI,
  36 + MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI,
  37 + MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI,
  38 + MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
  39 + MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
  40 + MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
  41 + MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
  42 + MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
  43 + MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI,
  44 +
  45 + MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI,
  46 + MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI,
  47 + MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI,
  48 + MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI,
  49 + MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI,
  50 + MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI,
  51 + MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI,
  52 + MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI,
  53 + MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI,
  54 + MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI,
  55 + MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI,
  56 + MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI,
  57 + MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI,
  58 + MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
  59 + MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
  60 +
  61 + MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
  62 + MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
  63 + MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
  64 + MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
  65 + MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
  66 + MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
  67 +
  68 + MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD,
  69 + MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD,
  70 + MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD,
  71 + MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD,
  72 + MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD,
  73 + MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD,
  74 + MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD,
  75 + MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD,
  76 + MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD,
  77 + MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD,
  78 + MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
  79 + MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
  80 + MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
  81 + MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
  82 + MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
  83 + MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
  84 + MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
  85 + MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
  86 + MX23_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD,
  87 + MX23_PAD_LCD_RS__LCD_RS | MUX_CONFIG_LCD,
  88 + MX23_PAD_LCD_WR__LCD_WR | MUX_CONFIG_LCD,
  89 + MX23_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
  90 + MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
  91 + MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD,
  92 +
  93 + MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP,
  94 + MX23_PAD_SSP1_DETECT__GPIO_2_1 | MUX_CONFIG_SSP,
  95 + MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP,
  96 + MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP,
  97 + MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP,
  98 + MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP,
  99 + MX23_PAD_SSP1_SCK__SSP1_SCK | MUX_CONFIG_SSP,
  100 + MX23_PAD_GPMI_D07__GPIO_0_7 | MUX_CONFIG_SSP,
  101 +
  102 + MX23_PAD_GPMI_D00__SSP2_DATA0 | MUX_CONFIG_SSP,
  103 + MX23_PAD_GPMI_D01__SSP2_DATA1 | MUX_CONFIG_SSP,
  104 + MX23_PAD_GPMI_D02__SSP2_DATA2 | MUX_CONFIG_SSP,
  105 + MX23_PAD_GPMI_D03__SSP2_DATA3 | MUX_CONFIG_SSP,
  106 + MX23_PAD_GPMI_RDY1__SSP2_CMD | MUX_CONFIG_SSP,
  107 + MX23_PAD_GPMI_WRN__SSP2_SCK | MUX_CONFIG_SSP,
  108 +
  109 + /* PWM -- FIXME */
  110 + MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP,
  111 +};
  112 +
  113 +void mxs_adjust_memory_params(uint32_t *dram_vals)
  114 +{
  115 + /* mDDR configuration values */
  116 + const uint32_t regs[] = {
  117 + 0x01010001, 0x00010000, 0x01000000, 0x00000001,
  118 + 0x00010101, 0x00000001, 0x00010000, 0x01000001,
  119 + 0x01010000, 0x00000001, 0x07000200, 0x04070203,
  120 + 0x02020002, 0x06070a02, 0x0d000201, 0x0305000d,
  121 + 0x02080800, 0x19330f0a, 0x1f1f1c00, 0x020a1313,
  122 + 0x03061323, 0x0000000a, 0x00080008, 0x00200020,
  123 + 0x00200020, 0x00200020, 0x000003f7, 0x00000000,
  124 + 0x00000000, 0x00000000, 0x00000020, 0x00000000,
  125 + 0x001023cd, 0x20410010, 0x00006665, 0x00000000,
  126 + 0x00000101, 0x00000001, 0x00000000, 0x00000000,
  127 + };
  128 + memcpy(dram_vals, regs, sizeof(regs));
  129 +}
  130 +
  131 +void board_init_ll(const uint32_t arg, const uint32_t *resptr)
  132 +{
  133 + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
  134 +}
board/creative/xfi3/xfi3.c
Diff comments   View file @ aa04fef
  1 +/*
  2 + * Creative ZEN X-Fi3 board
  3 + *
  4 + * Copyright (C) 2013 Marek Vasut <marex@denx.de>
  5 + *
  6 + * Hardware investigation done by:
  7 + *
  8 + * Amaury Pouly <amaury.pouly@gmail.com>
  9 + *
  10 + * SPDX-License-Identifier: GPL-2.0+
  11 + */
  12 +
  13 +#include <common.h>
  14 +#include <errno.h>
  15 +#include <asm/gpio.h>
  16 +#include <asm/io.h>
  17 +#include <asm/arch/iomux-mx23.h>
  18 +#include <asm/arch/imx-regs.h>
  19 +#include <asm/arch/clock.h>
  20 +#include <asm/arch/sys_proto.h>
  21 +
  22 +DECLARE_GLOBAL_DATA_PTR;
  23 +
  24 +/*
  25 + * Functions
  26 + */
  27 +int board_early_init_f(void)
  28 +{
  29 + /* IO0 clock at 480MHz */
  30 + mxs_set_ioclk(MXC_IOCLK0, 480000);
  31 +
  32 + /* SSP0 clock at 96MHz */
  33 + mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
  34 +
  35 + return 0;
  36 +}
  37 +
  38 +int dram_init(void)
  39 +{
  40 + return mxs_dram_init();
  41 +}
  42 +
  43 +#ifdef CONFIG_CMD_MMC
  44 +static int xfi3_mmc_cd(int id)
  45 +{
  46 + switch (id) {
  47 + case 0:
  48 + /* The SSP_DETECT is inverted on this board. */
  49 + return gpio_get_value(MX23_PAD_SSP1_DETECT__GPIO_2_1);
  50 + case 1:
  51 + /* Phison bridge always present */
  52 + return 1;
  53 + default:
  54 + return 0;
  55 + }
  56 +}
  57 +
  58 +int board_mmc_init(bd_t *bis)
  59 +{
  60 + int ret;
  61 +
  62 + /* MicroSD slot */
  63 + gpio_direction_input(MX23_PAD_SSP1_DETECT__GPIO_2_1);
  64 + gpio_direction_output(MX23_PAD_GPMI_D07__GPIO_0_7, 0);
  65 + ret = mxsmmc_initialize(bis, 0, NULL, xfi3_mmc_cd);
  66 + if (ret)
  67 + return ret;
  68 +
  69 + /* Phison SD-NAND bridge */
  70 + ret = mxsmmc_initialize(bis, 1, NULL, xfi3_mmc_cd);
  71 +
  72 + return ret;
  73 +}
  74 +#endif
  75 +
  76 +#ifdef CONFIG_VIDEO_MXS
  77 +static int mxsfb_write_byte(uint32_t payload, const unsigned int data)
  78 +{
  79 + struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
  80 + const unsigned int timeout = 0x10000;
  81 +
  82 + if (mxs_wait_mask_clr(&regs->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
  83 + timeout))
  84 + return -ETIMEDOUT;
  85 +
  86 + writel((1 << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
  87 + (1 << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET),
  88 + &regs->hw_lcdif_transfer_count);
  89 +
  90 + writel(LCDIF_CTRL_DATA_SELECT | LCDIF_CTRL_RUN,
  91 + &regs->hw_lcdif_ctrl_clr);
  92 +
  93 + if (data)
  94 + writel(LCDIF_CTRL_DATA_SELECT, &regs->hw_lcdif_ctrl_set);
  95 +
  96 + writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
  97 +
  98 + if (mxs_wait_mask_clr(&regs->hw_lcdif_lcdif_stat_reg, 1 << 29,
  99 + timeout))
  100 + return -ETIMEDOUT;
  101 +
  102 + writel(payload, &regs->hw_lcdif_data);
  103 + return mxs_wait_mask_clr(&regs->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
  104 + timeout);
  105 +}
  106 +
  107 +static void mxsfb_write_register(uint32_t reg, uint32_t data)
  108 +{
  109 + mxsfb_write_byte(reg, 0);
  110 + mxsfb_write_byte(data, 1);
  111 +}
  112 +
  113 +static const struct {
  114 + uint8_t reg;
  115 + uint8_t delay;
  116 + uint16_t val;
  117 +} lcd_regs[] = {
  118 + { 0x01, 0, 0x001c },
  119 + { 0x02, 0, 0x0100 },
  120 + /* Writing 0x30 to reg. 0x03 flips the LCD */
  121 + { 0x03, 0, 0x1038 },
  122 + { 0x08, 0, 0x0808 },
  123 + /* This can contain 0x111 to rotate the LCD. */
  124 + { 0x0c, 0, 0x0000 },
  125 + { 0x0f, 0, 0x0c01 },
  126 + { 0x20, 0, 0x0000 },
  127 + { 0x21, 30, 0x0000 },
  128 + /* Wait 30 mS here */
  129 + { 0x10, 0, 0x0a00 },
  130 + { 0x11, 30, 0x1038 },
  131 + /* Wait 30 mS here */
  132 + { 0x12, 0, 0x1010 },
  133 + { 0x13, 0, 0x0050 },
  134 + { 0x14, 0, 0x4f58 },
  135 + { 0x30, 0, 0x0000 },
  136 + { 0x31, 0, 0x00db },
  137 + { 0x32, 0, 0x0000 },
  138 + { 0x33, 0, 0x0000 },
  139 + { 0x34, 0, 0x00db },
  140 + { 0x35, 0, 0x0000 },
  141 + { 0x36, 0, 0x00af },
  142 + { 0x37, 0, 0x0000 },
  143 + { 0x38, 0, 0x00db },
  144 + { 0x39, 0, 0x0000 },
  145 + { 0x50, 0, 0x0000 },
  146 + { 0x51, 0, 0x0705 },
  147 + { 0x52, 0, 0x0e0a },
  148 + { 0x53, 0, 0x0300 },
  149 + { 0x54, 0, 0x0a0e },
  150 + { 0x55, 0, 0x0507 },
  151 + { 0x56, 0, 0x0000 },
  152 + { 0x57, 0, 0x0003 },
  153 + { 0x58, 0, 0x090a },
  154 + { 0x59, 30, 0x0a09 },
  155 + /* Wait 30 mS here */
  156 + { 0x07, 30, 0x1017 },
  157 + /* Wait 40 mS here */
  158 + { 0x36, 0, 0x00af },
  159 + { 0x37, 0, 0x0000 },
  160 + { 0x38, 0, 0x00db },
  161 + { 0x39, 0, 0x0000 },
  162 + { 0x20, 0, 0x0000 },
  163 + { 0x21, 0, 0x0000 },
  164 +};
  165 +
  166 +void board_mxsfb_system_setup(void)
  167 +{
  168 + struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
  169 + int i;
  170 +
  171 + /* Switch the LCDIF into System-Mode */
  172 + writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DOTCLK_MODE |
  173 + LCDIF_CTRL_BYPASS_COUNT, &regs->hw_lcdif_ctrl_clr);
  174 +
  175 + /* Restart the SmartLCD controller */
  176 + mdelay(50);
  177 + writel(1, &regs->hw_lcdif_ctrl1_set);
  178 + mdelay(50);
  179 + writel(1, &regs->hw_lcdif_ctrl1_clr);
  180 + mdelay(50);
  181 + writel(1, &regs->hw_lcdif_ctrl1_set);
  182 + mdelay(50);
  183 +
  184 + /* Program the SmartLCD controller */
  185 + writel(LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, &regs->hw_lcdif_ctrl1_set);
  186 +
  187 + writel((0x03 << LCDIF_TIMING_CMD_HOLD_OFFSET) |
  188 + (0x03 << LCDIF_TIMING_CMD_SETUP_OFFSET) |
  189 + (0x03 << LCDIF_TIMING_DATA_HOLD_OFFSET) |
  190 + (0x02 << LCDIF_TIMING_DATA_SETUP_OFFSET),
  191 + &regs->hw_lcdif_timing);
  192 +
  193 + /*
  194 + * OTM2201A init and configuration sequence.
  195 + */
  196 + for (i = 0; i < ARRAY_SIZE(lcd_regs); i++) {
  197 + mxsfb_write_register(lcd_regs[i].reg, lcd_regs[i].val);
  198 + if (lcd_regs[i].delay)
  199 + mdelay(lcd_regs[i].delay);
  200 + }
  201 + /* Turn on Framebuffer Upload Mode */
  202 + mxsfb_write_byte(0x22, 0);
  203 +
  204 + writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DATA_SELECT,
  205 + &regs->hw_lcdif_ctrl_set);
  206 +}
  207 +#endif
  208 +
  209 +int board_init(void)
  210 +{
  211 + /* Adress of boot parameters */
  212 + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  213 +
  214 + /* Turn on PWM backlight */
  215 + gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1);
  216 +
  217 + return 0;
  218 +}
  219 +
  220 +int board_eth_init(bd_t *bis)
  221 +{
  222 + usb_eth_initialize(bis);
  223 + return 0;
  224 +}
... ... @@ -206,6 +206,7 @@
206 206 mx28evk_nand arm arm926ejs mx28evk freescale mxs mx28evk:ENV_IS_IN_NAND
207 207 mx28evk_auart_console arm arm926ejs mx28evk freescale mxs mx28evk:MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC
208 208 sc_sps_1 arm arm926ejs sc_sps_1 schulercontrol mxs
  209 +xfi3 arm arm926ejs xfi3 creative mxs xfi3
209 210 nhk8815 arm arm926ejs nhk8815 st nomadik
210 211 nhk8815_onenand arm arm926ejs nhk8815 st nomadik nhk8815:BOOT_ONENAND
211 212 omap5912osk arm arm926ejs - ti omap
include/configs/xfi3.h
Diff comments   View file @ aa04fef
  1 +/*
  2 + * Copyright (C) 2013 Marek Vasut <marex@denx.de>
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +#ifndef __CONFIGS_XFI3_H__
  7 +#define __CONFIGS_XFI3_H__
  8 +
  9 +/* System configurations */
  10 +#define CONFIG_MX23 /* i.MX23 SoC */
  11 +
  12 +/* U-Boot Commands */
  13 +#define CONFIG_SYS_NO_FLASH
  14 +#include <config_cmd_default.h>
  15 +#define CONFIG_DISPLAY_CPUINFO
  16 +#define CONFIG_DOS_PARTITION
  17 +
  18 +#define CONFIG_CMD_CACHE
  19 +#define CONFIG_CMD_EXT2
  20 +#define CONFIG_CMD_FAT
  21 +#define CONFIG_CMD_GPIO
  22 +#define CONFIG_CMD_MMC
  23 +#define CONFIG_CMD_PING
  24 +#define CONFIG_CMD_USB
  25 +#define CONFIG_VIDEO
  26 +
  27 +/* Memory configuration */
  28 +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
  29 +#define PHYS_SDRAM_1 0x40000000 /* Base address */
  30 +#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */
  31 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  32 +
  33 +/* Environment */
  34 +#define CONFIG_ENV_SIZE (16 * 1024)
  35 +#define CONFIG_ENV_IS_NOWHERE
  36 +#define CONFIG_ENV_OVERWRITE
  37 +
  38 +/* Booting Linux */
  39 +#define CONFIG_BOOTDELAY 3
  40 +#define CONFIG_BOOTFILE "uImage"
  41 +#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 "
  42 +#define CONFIG_LOADADDR 0x42000000
  43 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  44 +
  45 +/* LCD */
  46 +#ifdef CONFIG_VIDEO
  47 +#define CONFIG_VIDEO_FONT_4X6
  48 +#define CONFIG_VIDEO_MXS_MODE_SYSTEM
  49 +#define CONFIG_SYS_BLACK_IN_WRITE
  50 +#define LCD_BPP LCD_COLOR16
  51 +#endif
  52 +
  53 +/* USB */
  54 +#ifdef CONFIG_CMD_USB
  55 +#define CONFIG_EHCI_MXS_PORT0
  56 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  57 +
  58 +#define CONFIG_MV_UDC /* ChipIdea CI13xxx UDC */
  59 +#define CONFIG_USB_GADGET_DUALSPEED
  60 +
  61 +#define CONFIG_USB_ETHER
  62 +#define CONFIG_USB_ETH_CDC
  63 +#define CONFIG_NETCONSOLE
  64 +#endif
  65 +
  66 +/* The rest of the configuration is shared */
  67 +#include <configs/mxs.h>
  68 +
  69 +#endif /* __CONFIGS_XFI3_H__ */