Armada100: Enable Ethernet support for GplugD

This patch enables ethernet support for Marvell GplugD board. Network related commands works. Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>

Armada100: Enable Ethernet support for GplugD
This patch enables ethernet support for Marvell GplugD board. Network related commands works. Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
Ajay Bhargav · Albert ARIBAUD
1 parent 79788bb19a
Showing 4 changed files with 128 additions and 2 deletions Side-by-side Diff
arch/arm/include/asm/arch-armada100/armada100.h
arch/arm/include/asm/arch-armada100/mfp.h
board/Marvell/gplugd/gplugd.c
include/configs/gplugd.h
@@ -41,6 +41,10 @@
 /* Functional Clock Selection Mask */
 #define APBC_FNCLKSEL(x)        (((x) & 0xf) << 4)
  
+/* Fast Ethernet Controller Clock register definition */
+#define FE_CLK_RST		0x1
+#define FE_CLK_ENA		0x8
+
 /* Register Base Addresses */
 #define ARMD1_DRAM_BASE		0xB0000000
 #define ARMD1_FEC_BASE		0xC0800000
@@ -82,6 +86,59 @@
 	u32 aprr;	/*0x1020*/
 	u32 acgr;	/*0x1024*/
 	u32 arsr;	/*0x1028*/
+};
+
+/*
+ * Application Subsystem Power Management
+ * Refer Datasheet Appendix A.9
+ */
+struct armd1apmu_registers {
+	u32 pcr;		/* 0x000 */
+	u32 ccr;		/* 0x004 */
+	u32 pad1;
+	u32 ccsr;		/* 0x00C */
+	u32 fc_timer;		/* 0x010 */
+	u32 pad2;
+	u32 ideal_cfg;		/* 0x018 */
+	u8 pad3[0x04C - 0x018 - 4];
+	u32 lcdcrc;		/* 0x04C */
+	u32 cciccrc;		/* 0x050 */
+	u32 sd1crc;		/* 0x054 */
+	u32 sd2crc;		/* 0x058 */
+	u32 usbcrc;		/* 0x05C */
+	u32 nfccrc;		/* 0x060 */
+	u32 dmacrc;		/* 0x064 */
+	u32 pad4;
+	u32 buscrc;		/* 0x06C */
+	u8 pad5[0x07C - 0x06C - 4];
+	u32 wake_clr;		/* 0x07C */
+	u8 pad6[0x090 - 0x07C - 4];
+	u32 core_status;	/* 0x090 */
+	u32 rfsc;		/* 0x094 */
+	u32 imr;		/* 0x098 */
+	u32 irwc;		/* 0x09C */
+	u32 isr;		/* 0x0A0 */
+	u8 pad7[0x0B0 - 0x0A0 - 4];
+	u32 mhst;		/* 0x0B0 */
+	u32 msr;		/* 0x0B4 */
+	u8 pad8[0x0C0 - 0x0B4 - 4];
+	u32 msst;		/* 0x0C0 */
+	u32 pllss;		/* 0x0C4 */
+	u32 smb;		/* 0x0C8 */
+	u32 gccrc;		/* 0x0CC */
+	u8 pad9[0x0D4 - 0x0CC - 4];
+	u32 smccrc;		/* 0x0D4 */
+	u32 pad10;
+	u32 xdcrc;		/* 0x0DC */
+	u32 sd3crc;		/* 0x0E0 */
+	u32 sd4crc;		/* 0x0E4 */
+	u8 pad11[0x0F0 - 0x0E4 - 4];
+	u32 cfcrc;		/* 0x0F0 */
+	u32 mspcrc;		/* 0x0F4 */
+	u32 cmucrc;		/* 0x0F8 */
+	u32 fecrc;		/* 0x0FC */
+	u32 pciecrc;		/* 0x100 */
+	u32 epdcrc;		/* 0x104 */
 };
  
 /*
@@ -64,6 +64,25 @@
 #define MFP105_CI2C_SDA		(MFP_REG(0x1a4) | MFP_AF1 | MFP_DRIVE_MEDIUM)
 #define MFP106_CI2C_SCL		(MFP_REG(0x1a8) | MFP_AF1 | MFP_DRIVE_MEDIUM)
  
+/* Fast Ethernet */
+#define MFP086_ETH_TXCLK	(MFP_REG(0x158) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP087_ETH_TXEN		(MFP_REG(0x15C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP088_ETH_TXDQ3	(MFP_REG(0x160) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP089_ETH_TXDQ2	(MFP_REG(0x164) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP090_ETH_TXDQ1	(MFP_REG(0x168) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP091_ETH_TXDQ0	(MFP_REG(0x16C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP092_ETH_CRS		(MFP_REG(0x170) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP093_ETH_COL		(MFP_REG(0x174) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP094_ETH_RXCLK	(MFP_REG(0x178) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP095_ETH_RXER		(MFP_REG(0x17C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP096_ETH_RXDQ3	(MFP_REG(0x180) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP097_ETH_RXDQ2	(MFP_REG(0x184) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP098_ETH_RXDQ1	(MFP_REG(0x188) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP099_ETH_RXDQ0	(MFP_REG(0x18C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP100_ETH_MDC		(MFP_REG(0x190) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP101_ETH_MDIO		(MFP_REG(0x194) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP103_ETH_RXDV		(MFP_REG(0x19C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+
 /* More macros can be defined here... */
  
 #define MFP_PIN_MAX	117
@@ -33,6 +33,11 @@
 #include <asm/arch/mfp.h>
 #include <asm/arch/armada100.h>
  
+#ifdef CONFIG_ARMADA100_FEC
+#include <net.h>
+#include <netdev.h>
+#endif /* CONFIG_ARMADA100_FEC */
+
 DECLARE_GLOBAL_DATA_PTR;
  
 int board_early_init_f(void)
@@ -45,6 +50,26 @@
 		/* Enable Console on UART3 */
 		MFPO8_UART3_TXD,
 		MFPO9_UART3_RXD,
+
+		/* Ethernet PHY Interface */
+		MFP086_ETH_TXCLK,
+		MFP087_ETH_TXEN,
+		MFP088_ETH_TXDQ3,
+		MFP089_ETH_TXDQ2,
+		MFP090_ETH_TXDQ1,
+		MFP091_ETH_TXDQ0,
+		MFP092_ETH_CRS,
+		MFP093_ETH_COL,
+		MFP094_ETH_RXCLK,
+		MFP095_ETH_RXER,
+		MFP096_ETH_RXDQ3,
+		MFP097_ETH_RXDQ2,
+		MFP098_ETH_RXDQ1,
+		MFP099_ETH_RXDQ0,
+		MFP100_ETH_MDC,
+		MFP101_ETH_MDIO,
+		MFP103_ETH_RXDV,
+
 		MFP_EOC		/*End of configuration*/
 	};
 	/* configure MFP's */
@@ -60,4 +85,17 @@
 	gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
 	return 0;
 }
+
+#ifdef CONFIG_ARMADA100_FEC
+int board_eth_init(bd_t *bis)
+{
+	struct armd1apmu_registers *apmu_regs =
+		(struct armd1apmu_registers *)ARMD1_APMU_BASE;
+
+	/* Enable clock of ethernet controller */
+	writel(FE_CLK_RST | FE_CLK_ENA, &apmu_regs->fecrc);
+
+	return armada100_fec_register(ARMD1_FEC_BASE);
+}
+#endif /* CONFIG_ARMADA100_FEC */
@@ -62,8 +62,20 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_AUTOSCRIPT
 #undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
+
+/* Disable DCACHE */
+#define CONFIG_SYS_DCACHE_OFF
+
+/* Network configuration */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_NET_MULTI
+#define CONFIG_ARMADA100_FEC
+
+/* DHCP Support */
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_DHCP_REQUEST_DELAY		50000
+#endif /* CONFIG_CMD_NET */
  
 /*
  * mv-common.h should be defined after CMD configs since it used them
...	...	@@ -41,6 +41,10 @@
41	41	/* Functional Clock Selection Mask */
42	42	#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)
43	43
	44	+/* Fast Ethernet Controller Clock register definition */
	45	+#define FE_CLK_RST 0x1
	46	+#define FE_CLK_ENA 0x8
	47	+
44	48	/* Register Base Addresses */
45	49	#define ARMD1_DRAM_BASE 0xB0000000
46	50	#define ARMD1_FEC_BASE 0xC0800000
...	...	@@ -82,6 +86,59 @@
82	86	u32 aprr; /0x1020/
83	87	u32 acgr; /0x1024/
84	88	u32 arsr; /0x1028/
	89	+};
	90	+
	91	+/*
	92	+ * Application Subsystem Power Management
	93	+ * Refer Datasheet Appendix A.9
	94	+ */
	95	+struct armd1apmu_registers {
	96	+ u32 pcr; /* 0x000 */
	97	+ u32 ccr; /* 0x004 */
	98	+ u32 pad1;
	99	+ u32 ccsr; /* 0x00C */
	100	+ u32 fc_timer; /* 0x010 */
	101	+ u32 pad2;
	102	+ u32 ideal_cfg; /* 0x018 */
	103	+ u8 pad3[0x04C - 0x018 - 4];
	104	+ u32 lcdcrc; /* 0x04C */
	105	+ u32 cciccrc; /* 0x050 */
	106	+ u32 sd1crc; /* 0x054 */
	107	+ u32 sd2crc; /* 0x058 */
	108	+ u32 usbcrc; /* 0x05C */
	109	+ u32 nfccrc; /* 0x060 */
	110	+ u32 dmacrc; /* 0x064 */
	111	+ u32 pad4;
	112	+ u32 buscrc; /* 0x06C */
	113	+ u8 pad5[0x07C - 0x06C - 4];
	114	+ u32 wake_clr; /* 0x07C */
	115	+ u8 pad6[0x090 - 0x07C - 4];
	116	+ u32 core_status; /* 0x090 */
	117	+ u32 rfsc; /* 0x094 */
	118	+ u32 imr; /* 0x098 */
	119	+ u32 irwc; /* 0x09C */
	120	+ u32 isr; /* 0x0A0 */
	121	+ u8 pad7[0x0B0 - 0x0A0 - 4];
	122	+ u32 mhst; /* 0x0B0 */
	123	+ u32 msr; /* 0x0B4 */
	124	+ u8 pad8[0x0C0 - 0x0B4 - 4];
	125	+ u32 msst; /* 0x0C0 */
	126	+ u32 pllss; /* 0x0C4 */
	127	+ u32 smb; /* 0x0C8 */
	128	+ u32 gccrc; /* 0x0CC */
	129	+ u8 pad9[0x0D4 - 0x0CC - 4];
	130	+ u32 smccrc; /* 0x0D4 */
	131	+ u32 pad10;
	132	+ u32 xdcrc; /* 0x0DC */
	133	+ u32 sd3crc; /* 0x0E0 */
	134	+ u32 sd4crc; /* 0x0E4 */
	135	+ u8 pad11[0x0F0 - 0x0E4 - 4];
	136	+ u32 cfcrc; /* 0x0F0 */
	137	+ u32 mspcrc; /* 0x0F4 */
	138	+ u32 cmucrc; /* 0x0F8 */
	139	+ u32 fecrc; /* 0x0FC */
	140	+ u32 pciecrc; /* 0x100 */
	141	+ u32 epdcrc; /* 0x104 */
85	142	};
86	143
87	144	/*
...	...	@@ -64,6 +64,25 @@
64	64	#define MFP105_CI2C_SDA (MFP_REG(0x1a4) \| MFP_AF1 \| MFP_DRIVE_MEDIUM)
65	65	#define MFP106_CI2C_SCL (MFP_REG(0x1a8) \| MFP_AF1 \| MFP_DRIVE_MEDIUM)
66	66
	67	+/* Fast Ethernet */
	68	+#define MFP086_ETH_TXCLK (MFP_REG(0x158) \| MFP_AF5 \| MFP_DRIVE_MEDIUM)
	69	+#define MFP087_ETH_TXEN (MFP_REG(0x15C) \| MFP_AF5 \| MFP_DRIVE_MEDIUM)
	70	+#define MFP088_ETH_TXDQ3 (MFP_REG(0x160) \| MFP_AF5 \| MFP_DRIVE_MEDIUM)
	71	+#define MFP089_ETH_TXDQ2 (MFP_REG(0x164) \| MFP_AF5 \| MFP_DRIVE_MEDIUM)
	72	+#define MFP090_ETH_TXDQ1 (MFP_REG(0x168) \| MFP_AF5 \| MFP_DRIVE_MEDIUM)
	73	+#define MFP091_ETH_TXDQ0 (MFP_REG(0x16C) \| MFP_AF5 \| MFP_DRIVE_MEDIUM)
	74	+#define MFP092_ETH_CRS (MFP_REG(0x170) \| MFP_AF5 \| MFP_DRIVE_MEDIUM)
	75	+#define MFP093_ETH_COL (MFP_REG(0x174) \| MFP_AF5 \| MFP_DRIVE_MEDIUM)
	76	+#define MFP094_ETH_RXCLK (MFP_REG(0x178) \| MFP_AF5 \| MFP_DRIVE_MEDIUM)
	77	+#define MFP095_ETH_RXER (MFP_REG(0x17C) \| MFP_AF5 \| MFP_DRIVE_MEDIUM)
	78	+#define MFP096_ETH_RXDQ3 (MFP_REG(0x180) \| MFP_AF5 \| MFP_DRIVE_MEDIUM)
	79	+#define MFP097_ETH_RXDQ2 (MFP_REG(0x184) \| MFP_AF5 \| MFP_DRIVE_MEDIUM)
	80	+#define MFP098_ETH_RXDQ1 (MFP_REG(0x188) \| MFP_AF5 \| MFP_DRIVE_MEDIUM)
	81	+#define MFP099_ETH_RXDQ0 (MFP_REG(0x18C) \| MFP_AF5 \| MFP_DRIVE_MEDIUM)
	82	+#define MFP100_ETH_MDC (MFP_REG(0x190) \| MFP_AF5 \| MFP_DRIVE_MEDIUM)
	83	+#define MFP101_ETH_MDIO (MFP_REG(0x194) \| MFP_AF5 \| MFP_DRIVE_MEDIUM)
	84	+#define MFP103_ETH_RXDV (MFP_REG(0x19C) \| MFP_AF5 \| MFP_DRIVE_MEDIUM)
	85	+
67	86	/* More macros can be defined here... */
68	87
69	88	#define MFP_PIN_MAX 117
...	...	@@ -33,6 +33,11 @@
33	33	#include <asm/arch/mfp.h>
34	34	#include <asm/arch/armada100.h>
35	35
	36	+#ifdef CONFIG_ARMADA100_FEC
	37	+#include <net.h>
	38	+#include <netdev.h>
	39	+#endif /* CONFIG_ARMADA100_FEC */
	40	+
36	41	DECLARE_GLOBAL_DATA_PTR;
37	42
38	43	int board_early_init_f(void)
...	...	@@ -45,6 +50,26 @@
45	50	/* Enable Console on UART3 */
46	51	MFPO8_UART3_TXD,
47	52	MFPO9_UART3_RXD,
	53	+
	54	+ /* Ethernet PHY Interface */
	55	+ MFP086_ETH_TXCLK,
	56	+ MFP087_ETH_TXEN,
	57	+ MFP088_ETH_TXDQ3,
	58	+ MFP089_ETH_TXDQ2,
	59	+ MFP090_ETH_TXDQ1,
	60	+ MFP091_ETH_TXDQ0,
	61	+ MFP092_ETH_CRS,
	62	+ MFP093_ETH_COL,
	63	+ MFP094_ETH_RXCLK,
	64	+ MFP095_ETH_RXER,
	65	+ MFP096_ETH_RXDQ3,
	66	+ MFP097_ETH_RXDQ2,
	67	+ MFP098_ETH_RXDQ1,
	68	+ MFP099_ETH_RXDQ0,
	69	+ MFP100_ETH_MDC,
	70	+ MFP101_ETH_MDIO,
	71	+ MFP103_ETH_RXDV,
	72	+
48	73	MFP_EOC /End of configuration/
49	74	};
50	75	/* configure MFP's */
...	...	@@ -60,4 +85,17 @@
60	85	gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
61	86	return 0;
62	87	}
	88	+
	89	+#ifdef CONFIG_ARMADA100_FEC
	90	+int board_eth_init(bd_t *bis)
	91	+{
	92	+ struct armd1apmu_registers *apmu_regs =
	93	+ (struct armd1apmu_registers *)ARMD1_APMU_BASE;
	94	+
	95	+ /* Enable clock of ethernet controller */
	96	+ writel(FE_CLK_RST \| FE_CLK_ENA, &apmu_regs->fecrc);
	97	+
	98	+ return armada100_fec_register(ARMD1_FEC_BASE);
	99	+}
	100	+#endif /* CONFIG_ARMADA100_FEC */
...	...	@@ -62,8 +62,20 @@
62	62	#define CONFIG_CMD_I2C
63	63	#define CONFIG_CMD_AUTOSCRIPT
64	64	#undef CONFIG_CMD_FPGA
65		-#undef CONFIG_CMD_NET
66		-#undef CONFIG_CMD_NFS
	65	+
	66	+/* Disable DCACHE */
	67	+#define CONFIG_SYS_DCACHE_OFF
	68	+
	69	+/* Network configuration */
	70	+#ifdef CONFIG_CMD_NET
	71	+#define CONFIG_CMD_PING
	72	+#define CONFIG_NET_MULTI
	73	+#define CONFIG_ARMADA100_FEC
	74	+
	75	+/* DHCP Support */
	76	+#define CONFIG_CMD_DHCP
	77	+#define CONFIG_BOOTP_DHCP_REQUEST_DELAY 50000
	78	+#endif /* CONFIG_CMD_NET */
67	79
68	80	/*
69	81	* mv-common.h should be defined after CMD configs since it used them