Eric Lee / smarc-uboot

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Commit aa24509041ff8a4892071c2abec023dddd53874f

Authored by wdenk
1 parent aa5590b66f
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Patch by Tolunay Orkun, 14 May 2004: 

Add support for Cogent CSB472 board (8MB Flash Rev)

Showing 11 changed files with 920 additions and 9 deletions Side-by-side Diff

... ... @@ -2,6 +2,9 @@
2 2 Changes since U-Boot 1.1.1:
3 3 ======================================================================
4 4  
  5 +* Patch by Tolunay Orkun, 14 May 2004:
  6 + Add support for Cogent CSB472 board (8MB Flash Rev)
  7 +
5 8 * Patch by Thomas Viehweger, 14 May 2004:
6 9 - flash.h: more flash types added
7 10 - immap_8260.h: some bits added (useful for RMII)
... ... @@ -269,7 +269,7 @@
269 269  
270 270 N: Tolunay Orkun
271 271 E: torkun@nextio.com
272   -D: Support for Cogent CSB272 board
  272 +D: Support for Cogent CSB272 & CSB472 boards
273 273  
274 274 N: Keith Outwater
275 275 E: keith_outwater@mvis.com
... ... @@ -193,7 +193,8 @@
193 193 EBONY PPC440GP
194 194  
195 195 Tolunay Orkun <torkun@nextio.com>
196   - csb272 PPC4xx
  196 + csb272 PPC405GP
  197 + csb472 PPC405GP
197 198  
198 199 Keith Outwater <Keith_Outwater@mvis.com>
199 200  
... ... @@ -60,13 +60,13 @@
60 60 ADCIOP AR405 ASH405 BUBINGA405EP \
61 61 CANBT CPCI405 CPCI4052 CPCI405AB \
62 62 CPCI440 CPCIISER4 CRAYL1 csb272 \
63   - DASA_SIM DP405 DU405 EBONY \
64   - ERIC EXBITGEN HUB405 JSE \
65   - MIP405 MIP405T ML2 ml300 \
66   - OCOTEA OCRTC ORSG PCI405 \
67   - PIP405 PLU405 PMC405 PPChameleonEVB \
68   - VOH405 W7OLMC W7OLMG WALNUT405 \
69   - XPEDITE1K \
  63 + csb472 DASA_SIM DP405 DU405 \
  64 + EBONY ERIC EXBITGEN HUB405 \
  65 + JSE MIP405 MIP405T ML2 \
  66 + ml300 OCOTEA OCRTC ORSG \
  67 + PCI405 PIP405 PLU405 PMC405 \
  68 + PPChameleonEVB VOH405 W7OLMC W7OLMG \
  69 + WALNUT405 XPEDITE1K \
70 70 "
71 71  
72 72 #########################################################################
... ... @@ -602,6 +602,9 @@
602 602 csb272_config: unconfig
603 603 @./mkconfig $(@:_config=) ppc ppc4xx csb272
604 604  
  605 +csb472_config: unconfig
  606 + @./mkconfig $(@:_config=) ppc ppc4xx csb472
  607 +
605 608 DASA_SIM_config: unconfig
606 609 @./mkconfig $(@:_config=) ppc ppc4xx dasa_sim esd
607 610  
board/csb472/Makefile
Diff comments   View file @ aa24509
  1 +#
  2 +# (C) Copyright 2000-2004
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +include $(TOPDIR)/config.mk
  25 +
  26 +LIB = lib$(BOARD).a
  27 +
  28 +#OBJS = $(BOARD).o flash.o
  29 +#OBJS = $(BOARD).o strataflash.o
  30 +OBJS = $(BOARD).o
  31 +
  32 +SOBJS = init.o
  33 +
  34 +
  35 +$(LIB): $(OBJS) $(SOBJS)
  36 + $(AR) crv $@ $^
  37 +
  38 +clean:
  39 + rm -f $(SOBJS) $(OBJS)
  40 +
  41 +distclean: clean
  42 + rm -f $(LIB) core *.bak .depend
  43 +
  44 +#########################################################################
  45 +
  46 +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
  47 + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
  48 +
  49 +sinclude .depend
  50 +
  51 +#########################################################################
board/csb472/config.mk
Diff comments   View file @ aa24509
  1 +#
  2 +# (C) Copyright 2000-2004
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# (C) Copyright 2004
  6 +# Tolunay Orkun, NextIO Inc., torkun@nextio.com.
  7 +#
  8 +# See file CREDITS for list of people who contributed to this
  9 +# project.
  10 +#
  11 +# This program is free software; you can redistribute it and/or
  12 +# modify it under the terms of the GNU General Public License as
  13 +# published by the Free Software Foundation; either version 2 of
  14 +# the License, or (at your option) any later version.
  15 +#
  16 +# This program is distributed in the hope that it will be useful,
  17 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19 +# GNU General Public License for more details.
  20 +#
  21 +# You should have received a copy of the GNU General Public License
  22 +# along with this program; if not, write to the Free Software
  23 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 +# MA 02111-1307 USA
  25 +#
  26 +
  27 +#
  28 +# Cogent CSB472 board
  29 +#
  30 +
  31 +LDFLAGS += $(LINKER_UNDEFS)
  32 +
  33 +TEXT_BASE := 0xFFFC0000
  34 +#TEXT_BASE := 0x00100000
  35 +
  36 +PLATFORM_RELFLAGS := $(PLATFORM_RELFLAGS)
board/csb472/csb472.c
Diff comments   View file @ aa24509
  1 +/*
  2 + * (C) Copyright 2004
  3 + * Tolunay Orkun, Nextio Inc., torkun@nextio.com
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#include <common.h>
  25 +#include <asm/processor.h>
  26 +#include <i2c.h>
  27 +#include <miiphy.h>
  28 +#include <405gp_enet.h>
  29 +
  30 +/*
  31 + * board_early_init_f: do early board initialization
  32 + *
  33 + */
  34 +int board_early_init_f(void)
  35 +{
  36 + /*-------------------------------------------------------------------------+
  37 + | Interrupt controller setup for the Walnut board.
  38 + | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
  39 + | IRQ 16 405GP internally generated; active low; level sensitive
  40 + | IRQ 17-24 RESERVED
  41 + | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
  42 + | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
  43 + | IRQ 27 (EXT IRQ 2) Not Used
  44 + | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
  45 + | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
  46 + | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
  47 + | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
  48 + | Note for Walnut board:
  49 + | An interrupt taken for the FPGA (IRQ 25) indicates that either
  50 + | the Mouse, Keyboard, IRDA, or External Expansion caused the
  51 + | interrupt. The FPGA must be read to determine which device
  52 + | caused the interrupt. The default setting of the FPGA clears
  53 + |
  54 + +-------------------------------------------------------------------------*/
  55 +
  56 + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
  57 + mtdcr (uicer, 0x00000000); /* disable all ints */
  58 + mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
  59 + mtdcr (uicpr, 0xFFFFFF83); /* set int polarities */
  60 + mtdcr (uictr, 0x10000000); /* set int trigger levels */
  61 + mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
  62 + mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
  63 +
  64 + mtebc (epcr, 0xa8400000); /* EBC always driven */
  65 +
  66 + return 0; /* success */
  67 +}
  68 +
  69 +/*
  70 + * checkboard: identify/verify the board we are running
  71 + *
  72 + * Remark: we just assume it is correct board here!
  73 + *
  74 + */
  75 +int checkboard(void)
  76 +{
  77 + printf("BOARD: Cogent CSB472\n");
  78 +
  79 + return 0; /* success */
  80 +}
  81 +
  82 +/*
  83 + * initram: Determine the size of mounted DRAM
  84 + *
  85 + * Size is determined by reading SDRAM configuration registers as
  86 + * configured by initialization code
  87 + *
  88 + */
  89 +long initdram (int board_type)
  90 +{
  91 + ulong tot_size;
  92 + ulong bank_size;
  93 + ulong tmp;
  94 +
  95 + tot_size = 0;
  96 +
  97 + mtdcr (memcfga, mem_mb0cf);
  98 + tmp = mfdcr (memcfgd);
  99 + if (tmp & 0x00000001) {
  100 + bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
  101 + tot_size += bank_size;
  102 + }
  103 +
  104 + mtdcr (memcfga, mem_mb1cf);
  105 + tmp = mfdcr (memcfgd);
  106 + if (tmp & 0x00000001) {
  107 + bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
  108 + tot_size += bank_size;
  109 + }
  110 +
  111 + mtdcr (memcfga, mem_mb2cf);
  112 + tmp = mfdcr (memcfgd);
  113 + if (tmp & 0x00000001) {
  114 + bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
  115 + tot_size += bank_size;
  116 + }
  117 +
  118 + mtdcr (memcfga, mem_mb3cf);
  119 + tmp = mfdcr (memcfgd);
  120 + if (tmp & 0x00000001) {
  121 + bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
  122 + tot_size += bank_size;
  123 + }
  124 +
  125 + return tot_size;
  126 +}
  127 +
  128 +/*
  129 + * last_stage_init: final configurations (such as PHY etc)
  130 + *
  131 + */
  132 +int last_stage_init(void)
  133 +{
  134 + /* initialize the PHY */
  135 + miiphy_reset(CONFIG_PHY_ADDR);
  136 + miiphy_write(CONFIG_PHY_ADDR, PHY_BMCR,
  137 + PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); /* AUTO neg */
  138 + miiphy_write(CONFIG_PHY_ADDR, PHY_FCSCR, 0x0d08); /* LEDs */
  139 +
  140 + return 0; /* success */
  141 +}
  1 +/******************************************************************************
  2 + *
  3 + * This source code has been made available to you by IBM on an AS-IS
  4 + * basis. Anyone receiving this source is licensed under IBM
  5 + * copyrights to use it in any way he or she deems fit, including
  6 + * copying it, modifying it, compiling it, and redistributing it either
  7 + * with or without modifications. No license under IBM patents or
  8 + * patent applications is to be implied by the copyright license.
  9 + *
  10 + * Any user of this software should understand that IBM cannot provide
  11 + * technical support for this software and will not be responsible for
  12 + * any consequences resulting from the use of this software.
  13 + *
  14 + * Any person who transfers this source code or any derivative work
  15 + * must include the IBM copyright notice, this paragraph, and the
  16 + * preceding two paragraphs in the transferred software.
  17 + *
  18 + * COPYRIGHT I B M CORPORATION 1995
  19 + * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
  20 + *
  21 + *****************************************************************************/
  22 +#include <config.h>
  23 +#include <ppc4xx.h>
  24 +
  25 +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
  26 +
  27 +#include <ppc_asm.tmpl>
  28 +#include <ppc_defs.h>
  29 +
  30 +#include <asm/cache.h>
  31 +#include <asm/mmu.h>
  32 +
  33 +#define LI32(reg,val) \
  34 + addis reg,0,val@h;\
  35 + ori reg,reg,val@l
  36 +
  37 +#define WDCR_EBC(reg,val) \
  38 + addi r4,0,reg;\
  39 + mtdcr ebccfga,r4;\
  40 + addis r4,0,val@h;\
  41 + ori r4,r4,val@l;\
  42 + mtdcr ebccfgd,r4
  43 +
  44 +#define WDCR_SDRAM(reg,val) \
  45 + addi r4,0,reg;\
  46 + mtdcr memcfga,r4;\
  47 + addis r4,0,val@h;\
  48 + ori r4,r4,val@l;\
  49 + mtdcr memcfgd,r4
  50 +
  51 +/******************************************************************************
  52 + * Function: ext_bus_cntlr_init
  53 + *
  54 + * Description: Configures EBC Controller and a few basic chip selects.
  55 + *
  56 + * CS0 is setup to get the Boot Flash out of the addresss range
  57 + * so that we may setup a stack. CS7 is setup so that we can
  58 + * access and reset the hardware watchdog.
  59 + *
  60 + * IMPORTANT: For pass1 this code must run from
  61 + * cache since you can not reliably change a peripheral banks
  62 + * timing register (pbxap) while running code from that bank.
  63 + * For ex., since we are running from ROM on bank 0, we can NOT
  64 + * execute the code that modifies bank 0 timings from ROM, so
  65 + * we run it from cache.
  66 + *
  67 + * Notes: Does NOT use the stack.
  68 + *****************************************************************************/
  69 + .section ".text"
  70 + .align 2
  71 + .globl ext_bus_cntlr_init
  72 + .type ext_bus_cntlr_init, @function
  73 +ext_bus_cntlr_init:
  74 + mflr r0
  75 + /********************************************************************
  76 + * Prefetch entire ext_bus_cntrl_init function into the icache.
  77 + * This is necessary because we are going to change the same CS we
  78 + * are executing from. Otherwise a CPU lockup may occur.
  79 + *******************************************************************/
  80 + bl ..getAddr
  81 +..getAddr:
  82 + mflr r3 /* get address of ..getAddr */
  83 +
  84 + /* Calculate number of cache lines for this function */
  85 + addi r4, 0, (((.Lfe0 - ..getAddr) / CFG_CACHELINE_SIZE) + 2)
  86 + mtctr r4
  87 +..ebcloop:
  88 + icbt r0, r3 /* prefetch cache line for addr in r3*/
  89 + addi r3, r3, CFG_CACHELINE_SIZE /* move to next cache line */
  90 + bdnz ..ebcloop /* continue for $CTR cache lines */
  91 +
  92 + /********************************************************************
  93 + * Delay to ensure all accesses to ROM are complete before changing
  94 + * bank 0 timings. 200usec should be enough.
  95 + * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
  96 + *******************************************************************/
  97 + addis r3, 0, 0x0
  98 + ori r3, r3, 0xA000 /* wait 200us from reset */
  99 + mtctr r3
  100 +..spinlp:
  101 + bdnz ..spinlp /* spin loop */
  102 +
  103 + /********************************************************************
  104 + * SETUP CPC0_CR0
  105 + *******************************************************************/
  106 + LI32(r4, 0x00c01030)
  107 + mtdcr cntrl0, r4
  108 +
  109 + /********************************************************************
  110 + * Setup CPC0_CR1: Change PCIINT signal to PerWE
  111 + *******************************************************************/
  112 + mfdcr r4, cntrl1
  113 + ori r4, r4, 0x4000
  114 + mtdcr cntrl1, r4
  115 +
  116 + /********************************************************************
  117 + * Setup External Bus Controller (EBC).
  118 + *******************************************************************/
  119 + WDCR_EBC(epcr, 0xd84c0000)
  120 + /********************************************************************
  121 + * Memory Bank 0 (Intel 28F640J3 Flash) initialization
  122 + *******************************************************************/
  123 + /*WDCR_EBC(pb0ap, 0x03055200)*/
  124 + /*WDCR_EBC(pb0ap, 0x04055200)*/
  125 + WDCR_EBC(pb0ap, 0x08055200)
  126 + WDCR_EBC(pb0cr, 0xff87a000)
  127 + /********************************************************************
  128 + * Memory Bank 3 (Xilinx XC95144 CPLD) initialization
  129 + *******************************************************************/
  130 + /*WDCR_EBC(pb3ap, 0x07869200)*/
  131 + WDCR_EBC(pb3ap, 0x04055200)
  132 + WDCR_EBC(pb3cr, 0xff01c000)
  133 + /********************************************************************
  134 + * Memory Bank 1,2,4-7 (Unused) initialization
  135 + *******************************************************************/
  136 + WDCR_EBC(pb1ap, 0)
  137 + WDCR_EBC(pb1cr, 0)
  138 + WDCR_EBC(pb2ap, 0)
  139 + WDCR_EBC(pb2cr, 0)
  140 + WDCR_EBC(pb4ap, 0)
  141 + WDCR_EBC(pb4cr, 0)
  142 + WDCR_EBC(pb5ap, 0)
  143 + WDCR_EBC(pb5cr, 0)
  144 + WDCR_EBC(pb6ap, 0)
  145 + WDCR_EBC(pb6cr, 0)
  146 + WDCR_EBC(pb7ap, 0)
  147 + WDCR_EBC(pb7cr, 0)
  148 +
  149 + /* We are all done */
  150 + mtlr r0 /* Restore link register */
  151 + blr /* Return to calling function */
  152 +.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
  153 +/* end ext_bus_cntlr_init() */
  154 +
  155 +/******************************************************************************
  156 + * Function: sdram_init
  157 + *
  158 + * Description: Configures SDRAM memory banks.
  159 + *
  160 + * Notes: Does NOT use the stack.
  161 + *****************************************************************************/
  162 + .section ".text"
  163 + .align 2
  164 + .globl sdram_init
  165 + .type sdram_init, @function
  166 +sdram_init:
  167 +
  168 + /*
  169 + * Disable memory controller to allow
  170 + * values to be changed.
  171 + */
  172 + WDCR_SDRAM(mem_mcopt1, 0x00000000)
  173 +
  174 + /*
  175 + * Configure Memory Banks
  176 + */
  177 + WDCR_SDRAM(mem_mb0cf, 0x00062001)
  178 + WDCR_SDRAM(mem_mb1cf, 0x00000000)
  179 + WDCR_SDRAM(mem_mb2cf, 0x00000000)
  180 + WDCR_SDRAM(mem_mb3cf, 0x00000000)
  181 +
  182 + /*
  183 + * Set up SDTR1 (SDRAM Timing Register)
  184 + */
  185 + WDCR_SDRAM(mem_sdtr1, 0x00854009)
  186 +
  187 + /*
  188 + * Set RTR (Refresh Timing Register)
  189 + */
  190 + WDCR_SDRAM(mem_rtr, 0x10000000)
  191 + /* WDCR_SDRAM(mem_rtr, 0x05f00000) */
  192 +
  193 + /********************************************************************
  194 + * Delay to ensure 200usec have elapsed since reset. Assume worst
  195 + * case that the core is running 200Mhz:
  196 + * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
  197 + *******************************************************************/
  198 + addis r3, 0, 0x0000
  199 + ori r3, r3, 0xA000 /* Wait >200us from reset */
  200 + mtctr r3
  201 +..spinlp2:
  202 + bdnz ..spinlp2 /* spin loop */
  203 +
  204 + /********************************************************************
  205 + * Set memory controller options reg, MCOPT1.
  206 + *******************************************************************/
  207 + WDCR_SDRAM(mem_mcopt1,0x80800000)
  208 +
  209 +..sdri_done:
  210 + blr /* Return to calling function */
  211 +.Lfe1: .size sdram_init,.Lfe1-sdram_init
  212 +/* end sdram_init() */
board/csb472/u-boot.lds
Diff comments   View file @ aa24509
  1 +/*
  2 + * (C) Copyright 2000-2004
  3 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +OUTPUT_ARCH(powerpc)
  25 +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
  26 +/* Do we need any of these for elf?
  27 + __DYNAMIC = 0; */
  28 +SECTIONS
  29 +{
  30 + .resetvec 0xFFFFFFFC :
  31 + {
  32 + *(.resetvec)
  33 + } = 0xffff
  34 +
  35 + /* Read-only sections, merged into text segment: */
  36 + . = + SIZEOF_HEADERS;
  37 + .interp : { *(.interp) }
  38 + .hash : { *(.hash) }
  39 + .dynsym : { *(.dynsym) }
  40 + .dynstr : { *(.dynstr) }
  41 + .rel.text : { *(.rel.text) }
  42 + .rela.text : { *(.rela.text) }
  43 + .rel.data : { *(.rel.data) }
  44 + .rela.data : { *(.rela.data) }
  45 + .rel.rodata : { *(.rel.rodata) }
  46 + .rela.rodata : { *(.rela.rodata) }
  47 + .rel.got : { *(.rel.got) }
  48 + .rela.got : { *(.rela.got) }
  49 + .rel.ctors : { *(.rel.ctors) }
  50 + .rela.ctors : { *(.rela.ctors) }
  51 + .rel.dtors : { *(.rel.dtors) }
  52 + .rela.dtors : { *(.rela.dtors) }
  53 + .rel.bss : { *(.rel.bss) }
  54 + .rela.bss : { *(.rela.bss) }
  55 + .rel.plt : { *(.rel.plt) }
  56 + .rela.plt : { *(.rela.plt) }
  57 + .init : { *(.init) }
  58 + .plt : { *(.plt) }
  59 + .text :
  60 + {
  61 + /* WARNING - the following is hand-optimized to fit within */
  62 + /* the sector layout of our flash chips! XXX FIXME XXX */
  63 +
  64 + cpu/ppc4xx/start.o (.text)
  65 + board/csb472/init.o (.text)
  66 + cpu/ppc4xx/kgdb.o (.text)
  67 + cpu/ppc4xx/traps.o (.text)
  68 + cpu/ppc4xx/interrupts.o (.text)
  69 + cpu/ppc4xx/serial.o (.text)
  70 + cpu/ppc4xx/cpu_init.o (.text)
  71 + cpu/ppc4xx/speed.o (.text)
  72 + cpu/ppc4xx/405gp_enet.o (.text)
  73 + common/dlmalloc.o (.text)
  74 + lib_generic/crc32.o (.text)
  75 +
  76 + lib_ppc/extable.o (.text)
  77 + lib_ppc/board.o (.text)
  78 + lib_generic/zlib.o (.text)
  79 +/* . = env_offset;*/
  80 +/* common/environment.o(.text)*/
  81 +
  82 + *(.text)
  83 + *(.fixup)
  84 + *(.got1)
  85 + }
  86 + _etext = .;
  87 + PROVIDE (etext = .);
  88 + .rodata :
  89 + {
  90 + *(.rodata)
  91 + *(.rodata1)
  92 + *(.rodata.str1.4)
  93 + }
  94 + .fini : { *(.fini) } =0
  95 + .ctors : { *(.ctors) }
  96 + .dtors : { *(.dtors) }
  97 +
  98 + /* Read-write section, merged into data segment: */
  99 + . = (. + 0x00FF) & 0xFFFFFF00;
  100 + _erotext = .;
  101 + PROVIDE (erotext = .);
  102 + .reloc :
  103 + {
  104 + *(.got)
  105 + _GOT2_TABLE_ = .;
  106 + *(.got2)
  107 + _FIXUP_TABLE_ = .;
  108 + *(.fixup)
  109 + }
  110 + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
  111 + __fixup_entries = (. - _FIXUP_TABLE_)>>2;
  112 +
  113 + .data :
  114 + {
  115 + *(.data)
  116 + *(.data1)
  117 + *(.sdata)
  118 + *(.sdata2)
  119 + *(.dynamic)
  120 + CONSTRUCTORS
  121 + }
  122 + _edata = .;
  123 + PROVIDE (edata = .);
  124 +
  125 + __u_boot_cmd_start = .;
  126 + .u_boot_cmd : { *(.u_boot_cmd) }
  127 + __u_boot_cmd_end = .;
  128 +
  129 +
  130 + __start___ex_table = .;
  131 + __ex_table : { *(__ex_table) }
  132 + __stop___ex_table = .;
  133 +
  134 + . = ALIGN(256);
  135 + __init_begin = .;
  136 + .text.init : { *(.text.init) }
  137 + .data.init : { *(.data.init) }
  138 + . = ALIGN(256);
  139 + __init_end = .;
  140 +
  141 + __bss_start = .;
  142 + .bss :
  143 + {
  144 + *(.sbss) *(.scommon)
  145 + *(.dynbss)
  146 + *(.bss)
  147 + *(COMMON)
  148 + }
  149 + _end = . ;
  150 + PROVIDE (end = .);
  151 +}
include/configs/csb472.h
Diff comments   View file @ aa24509
  1 +/*
  2 + * (C) Copyright 2004
  3 + * Tolunay Orkun, Nextio Inc., torkun@nextio.com
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +/*
  25 + * board/config.h - configuration options, board specific
  26 + */
  27 +
  28 +#ifndef __CONFIG_H
  29 +#define __CONFIG_H
  30 +
  31 +/*
  32 + * High Level Configuration Options
  33 + * (easy to change)
  34 + */
  35 +
  36 +#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
  37 +#define CONFIG_4xx 1 /* ...member of PPC4xx family */
  38 +#define CONFIG_CSB472 1 /* on a Cogent CSB472 board */
  39 +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */
  40 +#define CONFIG_LAST_STAGE_INIT 1 /* Call last_stage_init() */
  41 +#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
  42 +
  43 +/*
  44 + * OS Bootstrap configuration
  45 + *
  46 + */
  47 +
  48 +#if 0
  49 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
  50 +#else
  51 +#define CONFIG_BOOTDELAY 3 /* autoboot after X seconds */
  52 +#endif
  53 +
  54 +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress when bootdelay = 0 */
  55 +
  56 +#if 1
  57 +#undef CONFIG_BOOTARGS
  58 +#define CONFIG_BOOTCOMMAND \
  59 + "setenv bootargs console=ttyS0,38400 debug " \
  60 + "root=/dev/ram rw ramdisk_size=4096 " \
  61 + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
  62 + "bootm ff800000 ff900000"
  63 +#endif
  64 +
  65 +#if 0
  66 +#undef CONFIG_BOOTARGS
  67 +#define CONFIG_BOOTCOMMAND \
  68 + "bootp; " \
  69 + "setenv bootargs console=ttyS0,38400 debug " \
  70 + "root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
  71 + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
  72 + "bootm"
  73 +#endif
  74 +
  75 +/*
  76 + * BOOTP/DHCP protocol configuration
  77 + *
  78 + */
  79 +#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \
  80 + CONFIG_BOOTP_DNS2 | \
  81 + CONFIG_BOOTP_BOOTFILESIZE )
  82 +/*
  83 + * U-Boot Monitor Command Line Functions Configuration
  84 + *
  85 + */
  86 +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
  87 + CFG_CMD_ASKENV | \
  88 + CFG_CMD_BEDBUG | \
  89 + CFG_CMD_ELF | \
  90 + CFG_CMD_IRQ | \
  91 + CFG_CMD_I2C | \
  92 + CFG_CMD_PCI | \
  93 + CFG_CMD_DATE | \
  94 + CFG_CMD_MII | \
  95 + CFG_CMD_PING | \
  96 + CFG_CMD_DHCP )
  97 +
  98 +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  99 +#include <cmd_confdefs.h>
  100 +
  101 +/*
  102 + * Serial download configuration
  103 + *
  104 + */
  105 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  106 +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  107 +
  108 +/*
  109 + * KGDB Configuration
  110 + *
  111 + */
  112 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  113 +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  114 +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  115 +#endif
  116 +
  117 +/*
  118 + * Miscellaneous configurable options
  119 + *
  120 + */
  121 +#undef CFG_HUSH_PARSER /* use "hush" command parser */
  122 +#ifdef CFG_HUSH_PARSER
  123 +#define CFG_PROMPT_HUSH_PS2 "> " /* hush shell secondary prompt */
  124 +#endif
  125 +
  126 +#define CFG_LONGHELP /* undef to save memory */
  127 +#define CFG_PROMPT "=> " /* Monitor Command Prompt */
  128 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  129 +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  130 +#else
  131 +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  132 +#endif
  133 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  134 +#define CFG_MAXARGS 16 /* max number of command args */
  135 +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  136 +
  137 +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
  138 +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  139 +
  140 +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  141 +#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */
  142 +#define CFG_EXTBDINFO 1 /* To use extended board_info (bd_t) */
  143 +#define CFG_LOAD_ADDR 0x100000 /* default load address */
  144 +
  145 +/*
  146 + * For booting Linux, the board info and command line data
  147 + * have to be in the first 8 MB of memory, since this is
  148 + * the maximum mapped by the Linux kernel during initialization.
  149 + */
  150 +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  151 +
  152 +/*
  153 + * watchdog configuration
  154 + *
  155 + */
  156 +#undef CONFIG_WATCHDOG /* watchdog disabled */
  157 +
  158 +/*
  159 + * UART configuration
  160 + *
  161 + */
  162 +#undef CFG_EXT_SERIAL_CLOCK /* use internal serial clock */
  163 +#undef CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
  164 +#define CFG_BASE_BAUD 691200
  165 +#define CONFIG_BAUDRATE 38400 /* Default baud rate */
  166 +#define CFG_BAUDRATE_TABLE \
  167 + { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 }
  168 +
  169 +/*
  170 + * I2C configuration
  171 + *
  172 + */
  173 +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
  174 +#define CFG_I2C_SPEED 100000 /* I2C speed */
  175 +#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
  176 +
  177 +/*
  178 + * MII PHY configuration
  179 + *
  180 + */
  181 +#define CONFIG_MII 1 /* MII PHY management */
  182 +#define CONFIG_PHY_ADDR 0 /* PHY address */
  183 +#define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */
  184 + /* 32usec min. for LXT971A */
  185 +#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
  186 +
  187 +/*
  188 + * RTC configuration
  189 + *
  190 + * Note that DS1307 RTC is limited to 100Khz I2C bus.
  191 + *
  192 + */
  193 +#define CONFIG_RTC_DS1307 /* Use Dallas 1307 RTC */
  194 +
  195 +/*
  196 + * PCI stuff
  197 + *
  198 + */
  199 +#define CONFIG_PCI /* include pci support */
  200 +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
  201 +#define PCI_HOST_FORCE 1 /* configure as pci host */
  202 +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
  203 +
  204 +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
  205 +#define CONFIG_PCI_PNP /* do pci plug-and-play */
  206 + /* resource configuration */
  207 +#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
  208 +#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
  209 +
  210 +#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
  211 +#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
  212 +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
  213 +#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
  214 +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
  215 +#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
  216 +#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
  217 +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
  218 +
  219 +/*
  220 + * IDE stuff
  221 + *
  222 + */
  223 +#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
  224 +#undef CONFIG_IDE_LED /* no led for ide supported */
  225 +#undef CONFIG_IDE_RESET /* no reset for ide supported */
  226 +
  227 +/*
  228 + * Environment configuration
  229 + *
  230 + */
  231 +#define CFG_ENV_IS_IN_FLASH 1 /* environment is in FLASH */
  232 +#undef CFG_ENV_IS_IN_NVRAM
  233 +#undef CFG_ENV_IS_IN_EEPROM
  234 +
  235 +/*
  236 + * General Memory organization
  237 + *
  238 + * Start addresses for the final memory configuration
  239 + * (Set up by the startup code)
  240 + * Please note that CFG_SDRAM_BASE _must_ start at 0
  241 + */
  242 +#define CFG_SDRAM_BASE 0x00000000
  243 +#define CFG_FLASH_BASE 0xFF800000
  244 +#define CFG_FLASH_SIZE 0x00800000
  245 +#define CFG_MONITOR_BASE TEXT_BASE
  246 +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 KB for Monitor */
  247 +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 KB for malloc() */
  248 +
  249 +#if CFG_MONITOR_BASE < CFG_FLASH_BASE
  250 +#define CFG_RAMSTART
  251 +#endif
  252 +
  253 +#if defined(CFG_ENV_IS_IN_FLASH)
  254 +#define CFG_ENV_IN_OWN_SECTOR 1 /* Give Environment own sector */
  255 +#define CFG_ENV_ADDR 0xFFF00000 /* Address of Environment Sector */
  256 +#define CFG_ENV_SIZE 0x00001000 /* Size of Environment */
  257 +#define CFG_ENV_SECT_SIZE 0x00040000 /* Size of Environment Sector */
  258 +#endif
  259 +
  260 +/*
  261 + * FLASH Device configuration
  262 + *
  263 + */
  264 +#define CFG_FLASH_CFI 1 /* flash is CFI conformant */
  265 +#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
  266 +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
  267 +#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */
  268 +#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
  269 +#define CFG_MAX_FLASH_SECT 64 /* max # of sectors on one chip */
  270 +#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */
  271 +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
  272 +
  273 +/*
  274 + * On Chip Memory location/size
  275 + *
  276 + */
  277 +#define CFG_OCM_DATA_ADDR 0xF8000000
  278 +#define CFG_OCM_DATA_SIZE 0x1000
  279 +
  280 +/*
  281 + * Global info and initial stack
  282 + *
  283 + */
  284 +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of on-chip SRAM */
  285 +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
  286 +#define CFG_GBL_DATA_SIZE 128 /* byte size reserved for initial data */
  287 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  288 +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  289 +
  290 +/*
  291 + * Cache configuration
  292 + *
  293 + */
  294 +#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
  295 + /* have only 8kB, 16kB is save here */
  296 +#define CFG_CACHELINE_SIZE 32
  297 +
  298 +/*
  299 + * Miscellaneous board specific definitions
  300 + *
  301 + */
  302 +#define CONFIG_I2CFAST 1 /* enable "i2cfast" env. setting */
  303 +
  304 +/*
  305 + * Internal Definitions
  306 + *
  307 + * Boot Flags
  308 + *
  309 + */
  310 +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  311 +#define BOOTFLAG_WARM 0x02 /* Software reboot */
  312 +
  313 +#endif /* __CONFIG_H */