Eric Lee / smarc-uboot

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Commit aa4fea4f39d0c834a01b9261a6d64f3b5f600b7b

Authored by Ye Li
Committed by Nitin Garg
1 parent 04b813d468
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 5 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

MLK-20154-2 imx8mm_ddr3l_val: Add SPI NOR support 

iMX8MM DDR3L validation board uses FPGA to link with SPI NOR flash
on ECSPI1 port. Update the codes and configurations to enable the
ECSPI1 to access SPI NOR in u-boot.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

Showing 3 changed files with 11 additions and 24 deletions Side-by-side Diff

board/freescale/imx8mm_val/imx8mm_val.c
Diff comments   View file @ aa4fea4
... ... @@ -73,27 +73,15 @@
73 73 IMX8MM_PAD_ECSPI1_SS0_GPIO5_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
74 74 };
75 75  
76   -static iomux_v3_cfg_t const ecspi2_pads[] = {
77   - IMX8MM_PAD_ECSPI2_SCLK_ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
78   - IMX8MM_PAD_ECSPI2_MOSI_ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
79   - IMX8MM_PAD_ECSPI2_MISO_ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
80   - IMX8MM_PAD_ECSPI2_SS0_GPIO5_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
81   -};
82   -
83 76 static void setup_spi(void)
84 77 {
85 78 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
86   - imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
87 79 gpio_request(IMX_GPIO_NR(5, 9), "ECSPI1 CS");
88   - gpio_request(IMX_GPIO_NR(5, 13), "ECSPI2 CS");
89 80 }
90 81  
91 82 int board_spi_cs_gpio(unsigned bus, unsigned cs)
92 83 {
93   - if (bus == 0)
94   - return IMX_GPIO_NR(5, 9);
95   - else
96   - return IMX_GPIO_NR(5, 13);
  84 + return IMX_GPIO_NR(5, 9);
97 85 }
98 86 #endif
99 87  
configs/imx8mm_ddr3l_val_defconfig
Diff comments   View file @ aa4fea4
... ... @@ -54,4 +54,9 @@
54 54  
55 55 CONFIG_CMD_NAND=y
56 56 CONFIG_CMD_UBI=y
  57 +
  58 +CONFIG_CMD_SF=y
  59 +CONFIG_MXC_SPI=y
  60 +CONFIG_SPI_FLASH=y
  61 +CONFIG_SPI_FLASH_GIGADEVICE=y
include/configs/imx8mm_val.h
Diff comments   View file @ aa4fea4
... ... @@ -265,17 +265,11 @@
265 265 #endif
266 266  
267 267 /* Enable SPI */
268   -#ifndef CONFIG_NAND_MXS
269   -#ifndef CONFIG_FSL_FSPI
270   -#ifdef CONFIG_CMD_SF
271   -#define CONFIG_SPI_FLASH
272   -#define CONFIG_SPI_FLASH_STMICRO
273   -#define CONFIG_MXC_SPI
274   -#define CONFIG_SF_DEFAULT_BUS 0
275   -#define CONFIG_SF_DEFAULT_SPEED 20000000
276   -#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
277   -#endif
278   -#endif
  268 +#ifdef CONFIG_MXC_SPI
  269 +#define CONFIG_SF_DEFAULT_BUS 0
  270 +#define CONFIG_SF_DEFAULT_CS 0
  271 +#define CONFIG_SF_DEFAULT_SPEED 8000000
  272 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
279 273 #endif
280 274  
281 275 #ifdef CONFIG_CMD_NAND