ENGR00329484-2 ARM:MX6: Clear Align bit in SCTLR

This problem is found when debugging QuadSPI. When "A" bit is enabled, unaligned access will cause data abort exception. Actually, we do not want this exception. So clear the align bit for MX6 SOCs. Tested this code with android team colleague and did not find problem. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>

ENGR00329484-2 ARM:MX6: Clear Align bit in SCTLR
This problem is found when debugging QuadSPI. When "A" bit is enabled, unaligned access will cause data abort exception. Actually, we do not want this exception. So clear the align bit for MX6 SOCs. Tested this code with android team colleague and did not find problem. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Peng Fan · Eric Lee · Eric Lee · Eric Lee · Eric Lee · Eric Lee
1 parent 0338ad3a37
Showing 1 changed file with 3 additions and 0 deletions Side-by-side Diff
arch/arm/cpu/armv7/mx6/soc.c
@@ -477,6 +477,9 @@
  
 int arch_cpu_init(void)
 {
+	/* Clear the Align bit in SCTLR */
+	set_cr(get_cr() & ~CR_A);
+
 #if !defined(CONFIG_MX6SX) && !defined(CONFIG_MX6SL)
 	/*
 	 * imx6sl doesn't have pcie at all.
...	...	@@ -477,6 +477,9 @@
477	477
478	478	int arch_cpu_init(void)
479	479	{
	480	+ /* Clear the Align bit in SCTLR */
	481	+ set_cr(get_cr() & ~CR_A);
	482	+
480	483	#if !defined(CONFIG_MX6SX) && !defined(CONFIG_MX6SL)
481	484	/*
482	485	* imx6sl doesn't have pcie at all.