Eric Lee / smarc-uboot

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Commit aa8ac43645243b69faf0e81fab5f0d6fcf4285cf

Authored by Angela Stegmaier
Committed by Tom Rini
1 parent 89831112d4
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ARM: DRA72x: DDR3: Fix EMIF timings for 666MHz clock 

DDR3 timing and latency paramenters were not configured
correctly for 666MHz. Fixing the timing and latency values
according to Data sheet.
This fixes the random crashes seen on DRA72-evm.

Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

Showing 1 changed file with 8 additions and 8 deletions Side-by-side Diff

arch/arm/cpu/armv7/omap5/sdram.c
Diff comments   View file @ aa8ac43
... ... @@ -186,18 +186,18 @@
186 186 };
187 187  
188 188 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
189   - .sdram_config_init = 0x61851AB2,
190   - .sdram_config = 0x61851AB2,
  189 + .sdram_config_init = 0x61862B32,
  190 + .sdram_config = 0x61862B32,
191 191 .sdram_config2 = 0x08000000,
192   - .ref_ctrl = 0x00001035,
193   - .sdram_tim1 = 0xCCCF36B3,
194   - .sdram_tim2 = 0x308F7FDA,
195   - .sdram_tim3 = 0x027F88A8,
  192 + .ref_ctrl = 0x0000144A,
  193 + .sdram_tim1 = 0xD113781C,
  194 + .sdram_tim2 = 0x308F7FE3,
  195 + .sdram_tim3 = 0x009F86A8,
196 196 .read_idle_ctrl = 0x00050000,
197 197 .zq_config = 0x0007190B,
198 198 .temp_alert_config = 0x00000000,
199   - .emif_ddr_phy_ctlr_1_init = 0x0024400A,
200   - .emif_ddr_phy_ctlr_1 = 0x0024400A,
  199 + .emif_ddr_phy_ctlr_1_init = 0x0E24400D,
  200 + .emif_ddr_phy_ctlr_1 = 0x0E24400D,
201 201 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
202 202 .emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
203 203 .emif_ddr_ext_phy_ctrl_3 = 0x00A900A9,