Eric Lee / smarc-uboot

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Commit aaf87f03ad709ff9f00819ef1eb001e878ad0a54

Authored by Fabio Estevam
Committed by Tom Rini
1 parent cb4c833b74
Exists in v2017.01-smarct4x and in 30 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

pci: pcie_imx: Fix hang on mx6qp 

PCI driver currently hangs on mx6qp.

Toggle the reset bit with the appropriate timings to fix the issue.

Based on the FSL kernel driver implementation.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>

Showing 2 changed files with 10 additions and 0 deletions Side-by-side Diff

arch/arm/include/asm/arch-mx6/iomux.h
Diff comments   View file @ aaf87f0
... ... @@ -18,6 +18,8 @@
18 18 #define IOMUXC_GPR1_REF_SSP_EN (1 << 16)
19 19 #define IOMUXC_GPR1_TEST_POWERDOWN (1 << 18)
20 20  
  21 +#define IOMUXC_GPR1_PCIE_SW_RST (1 << 29)
  22 +
21 23 /*
22 24 * IOMUXC_GPR5 bit fields
23 25 */
drivers/pci/pcie_imx.c
Diff comments   View file @ aaf87f0
... ... @@ -19,6 +19,7 @@
19 19 #include <asm/io.h>
20 20 #include <linux/sizes.h>
21 21 #include <errno.h>
  22 +#include <asm/arch/sys_proto.h>
22 23  
23 24 #define PCI_ACCESS_READ 0
24 25 #define PCI_ACCESS_WRITE 1
... ... @@ -430,6 +431,10 @@
430 431 static int imx6_pcie_assert_core_reset(void)
431 432 {
432 433 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  434 +
  435 + if (is_mx6dqp())
  436 + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
  437 +
433 438 #if defined(CONFIG_MX6SX)
434 439 struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
435 440  
... ... @@ -535,6 +540,9 @@
535 540 imx6_pcie_toggle_power();
536 541  
537 542 enable_pcie_clock();
  543 +
  544 + if (is_mx6dqp())
  545 + clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
538 546  
539 547 /*
540 548 * Wait for the clock to settle a bit, when the clock are sourced