s5pc1xx: support the GPIO interface

This patch adds support the GPIO interface Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

s5pc1xx: support the GPIO interface
This patch adds support the GPIO interface Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Minkyu Kang · trix
1 parent 7b92159bd9
Showing 3 changed files with 173 additions and 0 deletions Side-by-side Diff
cpu/arm_cortexa8/s5pc1xx/Makefile
cpu/arm_cortexa8/s5pc1xx/gpio.c
include/asm-arm/arch-s5pc1xx/gpio.h
@@ -33,6 +33,7 @@
  
 COBJS	+= clock.o
 COBJS	+= cpu_info.o
+COBJS	+= gpio.o
 COBJS	+= timer.o
  
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+
+#define CON_MASK(x)		(0xf << ((x) << 2))
+#define CON_SFR(x, v)		((v) << ((x) << 2))
+
+#define DAT_MASK(x)		(0x1 << (x))
+#define DAT_SET(x)		(0x1 << (x))
+
+#define PULL_MASK(x)		(0x3 << ((x) << 1))
+#define PULL_MODE(x, v)		((v) << ((x) << 1))
+
+#define DRV_MASK(x)		(0x3 << ((x) << 1))
+#define DRV_SET(x, m)		((m) << ((x) << 1))
+#define RATE_MASK(x)		(0x1 << (x + 16))
+#define RATE_SET(x)		(0x1 << (x + 16))
+
+void gpio_cfg_pin(struct s5pc1xx_gpio_bank *bank, int gpio, int cfg)
+{
+	unsigned int value;
+
+	value = readl(&bank->con);
+	value &= ~CON_MASK(gpio);
+	value |= CON_SFR(gpio, cfg);
+	writel(value, &bank->con);
+}
+
+void gpio_direction_output(struct s5pc1xx_gpio_bank *bank, int gpio, int en)
+{
+	unsigned int value;
+
+	gpio_cfg_pin(bank, gpio, GPIO_OUTPUT);
+
+	value = readl(&bank->dat);
+	value &= ~DAT_MASK(gpio);
+	if (en)
+		value |= DAT_SET(gpio);
+	writel(value, &bank->dat);
+}
+
+void gpio_direction_input(struct s5pc1xx_gpio_bank *bank, int gpio)
+{
+	gpio_cfg_pin(bank, gpio, GPIO_INPUT);
+}
+
+void gpio_set_value(struct s5pc1xx_gpio_bank *bank, int gpio, int en)
+{
+	unsigned int value;
+
+	value = readl(&bank->dat);
+	value &= ~DAT_MASK(gpio);
+	if (en)
+		value |= DAT_SET(gpio);
+	writel(value, &bank->dat);
+}
+
+unsigned int gpio_get_value(struct s5pc1xx_gpio_bank *bank, int gpio)
+{
+	unsigned int value;
+
+	value = readl(&bank->dat);
+	return !!(value & DAT_MASK(gpio));
+}
+
+void gpio_set_pull(struct s5pc1xx_gpio_bank *bank, int gpio, int mode)
+{
+	unsigned int value;
+
+	value = readl(&bank->pull);
+	value &= ~PULL_MASK(gpio);
+
+	switch (mode) {
+	case GPIO_PULL_DOWN:
+	case GPIO_PULL_UP:
+		value |= PULL_MODE(gpio, mode);
+		break;
+	default:
+		return;
+	}
+
+	writel(value, &bank->pull);
+}
+
+void gpio_set_drv(struct s5pc1xx_gpio_bank *bank, int gpio, int mode)
+{
+	unsigned int value;
+
+	value = readl(&bank->drv);
+	value &= ~DRV_MASK(gpio);
+
+	switch (mode) {
+	case GPIO_DRV_1X:
+	case GPIO_DRV_2X:
+	case GPIO_DRV_3X:
+	case GPIO_DRV_4X:
+		value |= DRV_SET(gpio, mode);
+		break;
+	default:
+		return;
+	}
+
+	writel(value, &bank->drv);
+}
+
+void gpio_set_rate(struct s5pc1xx_gpio_bank *bank, int gpio, int mode)
+{
+	unsigned int value;
+
+	value = readl(&bank->drv);
+	value &= ~RATE_MASK(gpio);
+
+	switch (mode) {
+	case GPIO_DRV_FAST:
+	case GPIO_DRV_SLOW:
+		value |= RATE_SET(gpio);
+		break;
+	default:
+		return;
+	}
+
+	writel(value, &bank->drv);
+}
@@ -124,7 +124,36 @@
 	struct s5pc1xx_gpio_bank gpio_h2;
 	struct s5pc1xx_gpio_bank gpio_h3;
 };
+
+/* functions */
+void gpio_cfg_pin(struct s5pc1xx_gpio_bank *bank, int gpio, int cfg);
+void gpio_direction_output(struct s5pc1xx_gpio_bank *bank, int gpio, int en);
+void gpio_direction_input(struct s5pc1xx_gpio_bank *bank, int gpio);
+void gpio_set_value(struct s5pc1xx_gpio_bank *bank, int gpio, int en);
+unsigned int gpio_get_value(struct s5pc1xx_gpio_bank *bank, int gpio);
+void gpio_set_pull(struct s5pc1xx_gpio_bank *bank, int gpio, int mode);
+void gpio_set_drv(struct s5pc1xx_gpio_bank *bank, int gpio, int mode);
+void gpio_set_rate(struct s5pc1xx_gpio_bank *bank, int gpio, int mode);
 #endif
+
+/* Pin configurations */
+#define GPIO_INPUT	0x0
+#define GPIO_OUTPUT	0x1
+#define GPIO_IRQ	0xf
+#define GPIO_FUNC(x)	(x)
+
+/* Pull mode */
+#define GPIO_PULL_NONE	0x0
+#define GPIO_PULL_DOWN	0x1
+#define GPIO_PULL_UP	0x2
+
+/* Drive Strength level */
+#define GPIO_DRV_1X	0x0
+#define GPIO_DRV_2X	0x1
+#define GPIO_DRV_3X	0x2
+#define GPIO_DRV_4X	0x3
+#define GPIO_DRV_FAST	0x0
+#define GPIO_DRV_SLOW	0x1
  
 #endif
...	...	@@ -33,6 +33,7 @@
33	33
34	34	COBJS += clock.o
35	35	COBJS += cpu_info.o
	36	+COBJS += gpio.o
36	37	COBJS += timer.o
37	38
38	39	SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
	1	+/*
	2	+ * (C) Copyright 2009 Samsung Electronics
	3	+ * Minkyu Kang <mk7.kang@samsung.com>
	4	+ *
	5	+ * This program is free software; you can redistribute it and/or
	6	+ * modify it under the terms of the GNU General Public License as
	7	+ * published by the Free Software Foundation; either version 2 of
	8	+ * the License, or (at your option) any later version.
	9	+ *
	10	+ * This program is distributed in the hope that it will be useful,
	11	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	+ * GNU General Public License for more details.
	14	+ *
	15	+ * You should have received a copy of the GNU General Public License
	16	+ * along with this program; if not, write to the Free Software
	17	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	18	+ * MA 02111-1307 USA
	19	+ */
	20	+
	21	+#include <common.h>
	22	+#include <asm/io.h>
	23	+#include <asm/arch/gpio.h>
	24	+
	25	+#define CON_MASK(x) (0xf << ((x) << 2))
	26	+#define CON_SFR(x, v) ((v) << ((x) << 2))
	27	+
	28	+#define DAT_MASK(x) (0x1 << (x))
	29	+#define DAT_SET(x) (0x1 << (x))
	30	+
	31	+#define PULL_MASK(x) (0x3 << ((x) << 1))
	32	+#define PULL_MODE(x, v) ((v) << ((x) << 1))
	33	+
	34	+#define DRV_MASK(x) (0x3 << ((x) << 1))
	35	+#define DRV_SET(x, m) ((m) << ((x) << 1))
	36	+#define RATE_MASK(x) (0x1 << (x + 16))
	37	+#define RATE_SET(x) (0x1 << (x + 16))
	38	+
	39	+void gpio_cfg_pin(struct s5pc1xx_gpio_bank *bank, int gpio, int cfg)
	40	+{
	41	+ unsigned int value;
	42	+
	43	+ value = readl(&bank->con);
	44	+ value &= ~CON_MASK(gpio);
	45	+ value \|= CON_SFR(gpio, cfg);
	46	+ writel(value, &bank->con);
	47	+}
	48	+
	49	+void gpio_direction_output(struct s5pc1xx_gpio_bank *bank, int gpio, int en)
	50	+{
	51	+ unsigned int value;
	52	+
	53	+ gpio_cfg_pin(bank, gpio, GPIO_OUTPUT);
	54	+
	55	+ value = readl(&bank->dat);
	56	+ value &= ~DAT_MASK(gpio);
	57	+ if (en)
	58	+ value \|= DAT_SET(gpio);
	59	+ writel(value, &bank->dat);
	60	+}
	61	+
	62	+void gpio_direction_input(struct s5pc1xx_gpio_bank *bank, int gpio)
	63	+{
	64	+ gpio_cfg_pin(bank, gpio, GPIO_INPUT);
	65	+}
	66	+
	67	+void gpio_set_value(struct s5pc1xx_gpio_bank *bank, int gpio, int en)
	68	+{
	69	+ unsigned int value;
	70	+
	71	+ value = readl(&bank->dat);
	72	+ value &= ~DAT_MASK(gpio);
	73	+ if (en)
	74	+ value \|= DAT_SET(gpio);
	75	+ writel(value, &bank->dat);
	76	+}
	77	+
	78	+unsigned int gpio_get_value(struct s5pc1xx_gpio_bank *bank, int gpio)
	79	+{
	80	+ unsigned int value;
	81	+
	82	+ value = readl(&bank->dat);
	83	+ return !!(value & DAT_MASK(gpio));
	84	+}
	85	+
	86	+void gpio_set_pull(struct s5pc1xx_gpio_bank *bank, int gpio, int mode)
	87	+{
	88	+ unsigned int value;
	89	+
	90	+ value = readl(&bank->pull);
	91	+ value &= ~PULL_MASK(gpio);
	92	+
	93	+ switch (mode) {
	94	+ case GPIO_PULL_DOWN:
	95	+ case GPIO_PULL_UP:
	96	+ value \|= PULL_MODE(gpio, mode);
	97	+ break;
	98	+ default:
	99	+ return;
	100	+ }
	101	+
	102	+ writel(value, &bank->pull);
	103	+}
	104	+
	105	+void gpio_set_drv(struct s5pc1xx_gpio_bank *bank, int gpio, int mode)
	106	+{
	107	+ unsigned int value;
	108	+
	109	+ value = readl(&bank->drv);
	110	+ value &= ~DRV_MASK(gpio);
	111	+
	112	+ switch (mode) {
	113	+ case GPIO_DRV_1X:
	114	+ case GPIO_DRV_2X:
	115	+ case GPIO_DRV_3X:
	116	+ case GPIO_DRV_4X:
	117	+ value \|= DRV_SET(gpio, mode);
	118	+ break;
	119	+ default:
	120	+ return;
	121	+ }
	122	+
	123	+ writel(value, &bank->drv);
	124	+}
	125	+
	126	+void gpio_set_rate(struct s5pc1xx_gpio_bank *bank, int gpio, int mode)
	127	+{
	128	+ unsigned int value;
	129	+
	130	+ value = readl(&bank->drv);
	131	+ value &= ~RATE_MASK(gpio);
	132	+
	133	+ switch (mode) {
	134	+ case GPIO_DRV_FAST:
	135	+ case GPIO_DRV_SLOW:
	136	+ value \|= RATE_SET(gpio);
	137	+ break;
	138	+ default:
	139	+ return;
	140	+ }
	141	+
	142	+ writel(value, &bank->drv);
	143	+}
...	...	@@ -124,7 +124,36 @@
124	124	struct s5pc1xx_gpio_bank gpio_h2;
125	125	struct s5pc1xx_gpio_bank gpio_h3;
126	126	};
	127	+
	128	+/* functions */
	129	+void gpio_cfg_pin(struct s5pc1xx_gpio_bank *bank, int gpio, int cfg);
	130	+void gpio_direction_output(struct s5pc1xx_gpio_bank *bank, int gpio, int en);
	131	+void gpio_direction_input(struct s5pc1xx_gpio_bank *bank, int gpio);
	132	+void gpio_set_value(struct s5pc1xx_gpio_bank *bank, int gpio, int en);
	133	+unsigned int gpio_get_value(struct s5pc1xx_gpio_bank *bank, int gpio);
	134	+void gpio_set_pull(struct s5pc1xx_gpio_bank *bank, int gpio, int mode);
	135	+void gpio_set_drv(struct s5pc1xx_gpio_bank *bank, int gpio, int mode);
	136	+void gpio_set_rate(struct s5pc1xx_gpio_bank *bank, int gpio, int mode);
127	137	#endif
	138	+
	139	+/* Pin configurations */
	140	+#define GPIO_INPUT 0x0
	141	+#define GPIO_OUTPUT 0x1
	142	+#define GPIO_IRQ 0xf
	143	+#define GPIO_FUNC(x) (x)
	144	+
	145	+/* Pull mode */
	146	+#define GPIO_PULL_NONE 0x0
	147	+#define GPIO_PULL_DOWN 0x1
	148	+#define GPIO_PULL_UP 0x2
	149	+
	150	+/* Drive Strength level */
	151	+#define GPIO_DRV_1X 0x0
	152	+#define GPIO_DRV_2X 0x1
	153	+#define GPIO_DRV_3X 0x2
	154	+#define GPIO_DRV_4X 0x3
	155	+#define GPIO_DRV_FAST 0x0
	156	+#define GPIO_DRV_SLOW 0x1
128	157
129	158	#endif