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Commit aba27acf6711dce0ef1507f2f9f02a80d70a45da

Authored by Dirk Eibach
Committed by Stefan Roese
1 parent aaf5e82560
Exists in master and in 53 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

powerpc/ppc4xx: Use generic accessor functions for gdsys FPGA 

A set of accessor functions was added to be able to access not only
memory mapped FPGA in a generic way.

Thanks to Wolfgang Denk for getting this sorted properly.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>

Showing 16 changed files with 229 additions and 99 deletions Side-by-side Diff

board/gdsys/405ep/405ep.c
Diff comments   View file @ aba27ac
... ... @@ -18,6 +18,12 @@
18 18 #define REFLECTION_TESTPATTERN 0xdede
19 19 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
20 20  
  21 +#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
  22 +#define REFLECTION_TESTREG reflection_low
  23 +#else
  24 +#define REFLECTION_TESTREG reflection_high
  25 +#endif
  26 +
21 27 DECLARE_GLOBAL_DATA_PTR;
22 28  
23 29 int get_fpga_state(unsigned dev)
24 30  
25 31  
... ... @@ -90,23 +96,17 @@
90 96 gd405ep_set_fpga_reset(0);
91 97  
92 98 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
93   - struct ihs_fpga *fpga =
94   - (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k);
95   -#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
96   - u16 *reflection_target = &fpga->reflection_low;
97   -#else
98   - u16 *reflection_target = &fpga->reflection_high;
99   -#endif
100 99 /*
101 100 * wait for fpga out of reset
102 101 */
103 102 ctr = 0;
104 103 while (1) {
105   - out_le16(&fpga->reflection_low,
106   - REFLECTION_TESTPATTERN);
  104 + u16 val;
107 105  
108   - if (in_le16(reflection_target) ==
109   - REFLECTION_TESTPATTERN_INV)
  106 + FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
  107 +
  108 + FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
  109 + if (val == REFLECTION_TESTPATTERN_INV)
110 110 break;
111 111  
112 112 udelay(100000);
board/gdsys/405ep/dlvision-10g.c
Diff comments   View file @ aba27ac
... ... @@ -55,6 +55,8 @@
55 55 RAM_DDR2_64 = 2,
56 56 };
57 57  
  58 +struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
  59 +
58 60 int misc_init_r(void)
59 61 {
60 62 /* startup fans */
... ... @@ -79,10 +81,9 @@
79 81  
80 82 static void print_fpga_info(unsigned dev)
81 83 {
82   - struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(dev);
83   - u16 versions = in_le16(&fpga->versions);
84   - u16 fpga_version = in_le16(&fpga->fpga_version);
85   - u16 fpga_features = in_le16(&fpga->fpga_features);
  84 + u16 versions;
  85 + u16 fpga_version;
  86 + u16 fpga_features;
86 87 unsigned unit_type;
87 88 unsigned hardware_version;
88 89 unsigned feature_rs232;
... ... @@ -96,6 +97,10 @@
96 97  
97 98 printf("FPGA%d: ", dev);
98 99  
  100 + FPGA_GET_REG(dev, versions, &versions);
  101 + FPGA_GET_REG(dev, fpga_version, &fpga_version);
  102 + FPGA_GET_REG(dev, fpga_features, &fpga_features);
  103 +
99 104 hardware_version = versions & 0x000f;
100 105  
101 106 if (fpga_state
... ... @@ -247,8 +252,9 @@
247 252  
248 253 int last_stage_init(void)
249 254 {
250   - struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
251   - u16 versions = in_le16(&fpga->versions);
  255 + u16 versions;
  256 +
  257 + FPGA_GET_REG(0, versions, &versions);
252 258  
253 259 print_fpga_info(0);
254 260 if (get_mc2_present())
board/gdsys/405ep/io.c
Diff comments   View file @ aba27ac
... ... @@ -37,6 +37,8 @@
37 37 HWVER_122 = 3,
38 38 };
39 39  
  40 +struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
  41 +
40 42 int misc_init_r(void)
41 43 {
42 44 /* startup fans */
43 45  
... ... @@ -101,15 +103,18 @@
101 103  
102 104 static void print_fpga_info(void)
103 105 {
104   - struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
105   - u16 versions = in_le16(&fpga->versions);
106   - u16 fpga_version = in_le16(&fpga->fpga_version);
107   - u16 fpga_features = in_le16(&fpga->fpga_features);
  106 + u16 versions;
  107 + u16 fpga_version;
  108 + u16 fpga_features;
108 109 unsigned unit_type;
109 110 unsigned hardware_version;
110 111 unsigned feature_channels;
111 112 unsigned feature_expansion;
112 113  
  114 + FPGA_GET_REG(0, versions, &versions);
  115 + FPGA_GET_REG(0, fpga_version, &fpga_version);
  116 + FPGA_GET_REG(0, fpga_features, &fpga_features);
  117 +
113 118 unit_type = (versions & 0xf000) >> 12;
114 119 hardware_version = versions & 0x000f;
115 120 feature_channels = fpga_features & 0x007f;
... ... @@ -163,7 +168,6 @@
163 168 */
164 169 int last_stage_init(void)
165 170 {
166   - struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
167 171 unsigned int k;
168 172  
169 173 print_fpga_info();
... ... @@ -175,7 +179,7 @@
175 179 configure_gbit_phy(k);
176 180  
177 181 /* take fpga serdes blocks out of reset */
178   - out_le16(&fpga->quad_serdes_reset, 0);
  182 + FPGA_SET_REG(0, quad_serdes_reset, 0);
179 183  
180 184 return 0;
181 185 }
board/gdsys/405ep/iocon.c
Diff comments   View file @ aba27ac
... ... @@ -53,6 +53,8 @@
53 53 RAM_DDR2_32 = 0,
54 54 };
55 55  
  56 +struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
  57 +
56 58 /*
57 59 * Check Board Identity:
58 60 */
... ... @@ -76,10 +78,9 @@
76 78  
77 79 static void print_fpga_info(void)
78 80 {
79   - struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
80   - u16 versions = in_le16(&fpga->versions);
81   - u16 fpga_version = in_le16(&fpga->fpga_version);
82   - u16 fpga_features = in_le16(&fpga->fpga_features);
  81 + u16 versions;
  82 + u16 fpga_version;
  83 + u16 fpga_features;
83 84 unsigned unit_type;
84 85 unsigned hardware_version;
85 86 unsigned feature_compression;
... ... @@ -90,6 +91,10 @@
90 91 unsigned feature_carriers;
91 92 unsigned feature_video_channels;
92 93  
  94 + FPGA_GET_REG(0, versions, &versions);
  95 + FPGA_GET_REG(0, fpga_version, &fpga_version);
  96 + FPGA_GET_REG(0, fpga_features, &fpga_features);
  97 +
93 98 unit_type = (versions & 0xf000) >> 12;
94 99 hardware_version = versions & 0x000f;
95 100 feature_compression = (fpga_features & 0xe000) >> 13;
96 101  
97 102  
98 103  
... ... @@ -211,20 +216,25 @@
211 216  
212 217 /*
213 218 * provide access to fpga gpios (for I2C bitbang)
  219 + * (these may look all too simple but make iocon.h much more readable)
214 220 */
215 221 void fpga_gpio_set(int pin)
216 222 {
217   - out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x18), pin);
  223 + FPGA_SET_REG(0, gpio.set, pin);
218 224 }
219 225  
220 226 void fpga_gpio_clear(int pin)
221 227 {
222   - out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x16), pin);
  228 + FPGA_SET_REG(0, gpio.clear, pin);
223 229 }
224 230  
225 231 int fpga_gpio_get(int pin)
226 232 {
227   - return in_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x14)) & pin;
  233 + u16 val;
  234 +
  235 + FPGA_GET_REG(0, gpio.read, &val);
  236 +
  237 + return val & pin;
228 238 }
229 239  
230 240 void gd405ep_init(void)
board/gdsys/405ep/neo.c
Diff comments   View file @ aba27ac
... ... @@ -28,6 +28,8 @@
28 28 HWVER_300 = 3,
29 29 };
30 30  
  31 +struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
  32 +
31 33 int misc_init_r(void)
32 34 {
33 35 /* startup fans */
... ... @@ -54,10 +56,9 @@
54 56  
55 57 static void print_fpga_info(void)
56 58 {
57   - struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
58   - u16 versions = in_le16(&fpga->versions);
59   - u16 fpga_version = in_le16(&fpga->fpga_version);
60   - u16 fpga_features = in_le16(&fpga->fpga_features);
  59 + u16 versions;
  60 + u16 fpga_version;
  61 + u16 fpga_features;
61 62 int fpga_state = get_fpga_state(0);
62 63 unsigned unit_type;
63 64 unsigned hardware_version;
... ... @@ -73,6 +74,10 @@
73 74 printf(" refelectione test failed\n");
74 75 return;
75 76 }
  77 +
  78 + FPGA_GET_REG(0, versions, &versions);
  79 + FPGA_GET_REG(0, fpga_version, &fpga_version);
  80 + FPGA_GET_REG(0, fpga_features, &fpga_features);
76 81  
77 82 unit_type = (versions & 0xf000) >> 12;
78 83 hardware_version = versions & 0x000f;
board/gdsys/405ex/405ex.c
Diff comments   View file @ aba27ac
... ... @@ -11,6 +11,12 @@
11 11 #define REFLECTION_TESTPATTERN 0xdede
12 12 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
13 13  
  14 +#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
  15 +#define REFLECTION_TESTREG reflection_low
  16 +#else
  17 +#define REFLECTION_TESTREG reflection_high
  18 +#endif
  19 +
14 20 DECLARE_GLOBAL_DATA_PTR;
15 21  
16 22 int get_fpga_state(unsigned dev)
17 23  
18 24  
... ... @@ -220,23 +226,17 @@
220 226 gd405ex_set_fpga_reset(0);
221 227  
222 228 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
223   - struct ihs_fpga *fpga =
224   - (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k);
225   -#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
226   - u16 *reflection_target = &fpga->reflection_low;
227   -#else
228   - u16 *reflection_target = &fpga->reflection_high;
229   -#endif
230 229 /*
231 230 * wait for fpga out of reset
232 231 */
233 232 ctr = 0;
234 233 while (1) {
235   - out_le16(&fpga->reflection_low,
236   - REFLECTION_TESTPATTERN);
  234 + u16 val;
237 235  
238   - if (in_le16(reflection_target) ==
239   - REFLECTION_TESTPATTERN_INV)
  236 + FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
  237 +
  238 + FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
  239 + if (val == REFLECTION_TESTPATTERN_INV)
240 240 break;
241 241  
242 242 udelay(100000);
board/gdsys/405ex/io64.c
Diff comments   View file @ aba27ac
... ... @@ -51,6 +51,8 @@
51 51 HWVER_110 = 1,
52 52 };
53 53  
  54 +struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
  55 +
54 56 static inline void blank_string(int size)
55 57 {
56 58 int i;
... ... @@ -84,10 +86,9 @@
84 86  
85 87 static void print_fpga_info(unsigned dev)
86 88 {
87   - struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(dev);
88   - u16 versions = in_le16(&fpga->versions);
89   - u16 fpga_version = in_le16(&fpga->fpga_version);
90   - u16 fpga_features = in_le16(&fpga->fpga_features);
  89 + u16 versions;
  90 + u16 fpga_version;
  91 + u16 fpga_features;
91 92 int fpga_state = get_fpga_state(dev);
92 93  
93 94 unsigned unit_type;
... ... @@ -95,6 +96,10 @@
95 96 unsigned feature_channels;
96 97 unsigned feature_expansion;
97 98  
  99 + FPGA_GET_REG(dev, versions, &versions);
  100 + FPGA_GET_REG(dev, fpga_version, &fpga_version);
  101 + FPGA_GET_REG(dev, fpga_features, &fpga_features);
  102 +
98 103 printf("FPGA%d: ", dev);
99 104 if (fpga_state & FPGA_STATE_PLATFORM)
100 105 printf("(legacy) ");
... ... @@ -226,8 +231,6 @@
226 231 {
227 232 unsigned int k;
228 233 unsigned int fpga;
229   - struct ihs_fpga *fpga0 = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
230   - struct ihs_fpga *fpga1 = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(1);
231 234 int failed = 0;
232 235 char str_phys[] = "Setup PHYs -";
233 236 char str_serdes[] = "Start SERDES blocks";
234 237  
235 238  
... ... @@ -265,17 +268,16 @@
265 268 /* take fpga serdes blocks out of reset */
266 269 puts(str_serdes);
267 270 udelay(500000);
268   - out_le16(&fpga0->quad_serdes_reset, 0);
269   - out_le16(&fpga1->quad_serdes_reset, 0);
  271 + FPGA_SET_REG(0, quad_serdes_reset, 0);
  272 + FPGA_SET_REG(1, quad_serdes_reset, 0);
270 273 blank_string(strlen(str_serdes));
271 274  
272 275 /* take channels out of reset */
273 276 puts(str_channels);
274 277 udelay(500000);
275 278 for (fpga = 0; fpga < 2; ++fpga) {
276   - u16 *ch0_config_int = &(fpga ? fpga1 : fpga0)->ch0_config_int;
277 279 for (k = 0; k < 32; ++k)
278   - out_le16(ch0_config_int + 4 * k, 0);
  280 + FPGA_SET_REG(fpga, ch[k].config_int, 0);
279 281 }
280 282 blank_string(strlen(str_channels));
281 283  
282 284  
283 285  
... ... @@ -283,16 +285,16 @@
283 285 puts(str_locks);
284 286 udelay(500000);
285 287 for (fpga = 0; fpga < 2; ++fpga) {
286   - u16 *ch0_status_int = &(fpga ? fpga1 : fpga0)->ch0_status_int;
287 288 for (k = 0; k < 32; ++k) {
288   - u16 status = in_le16(ch0_status_int + 4*k);
  289 + u16 status;
  290 + FPGA_GET_REG(k, ch[k].status_int, &status);
289 291 if (!(status & (1 << 4))) {
290 292 failed = 1;
291 293 printf("fpga %d channel %d: no serdes lock\n",
292 294 fpga, k);
293 295 }
294 296 /* reset events */
295   - out_le16(ch0_status_int + 4*k, status);
  297 + FPGA_SET_REG(fpga, ch[k].status_int, 0);
296 298 }
297 299 }
298 300 blank_string(strlen(str_locks));
299 301  
300 302  
... ... @@ -300,14 +302,14 @@
300 302 /* verify hicb_status */
301 303 puts(str_hicb);
302 304 for (fpga = 0; fpga < 2; ++fpga) {
303   - u16 *ch0_hicb_status_int = &(fpga ? fpga1 : fpga0)->ch0_hicb_status_int;
304 305 for (k = 0; k < 32; ++k) {
305   - u16 status = in_le16(ch0_hicb_status_int + 4*k);
  306 + u16 status;
  307 + FPGA_GET_REG(k, hicb_ch[k].status_int, &status);
306 308 if (status)
307 309 printf("fpga %d hicb %d: hicb status %04x\n",
308 310 fpga, k, status);
309 311 /* reset events */
310   - out_le16(ch0_hicb_status_int + 4*k, status);
  312 + FPGA_SET_REG(fpga, hicb_ch[k].status_int, 0);
311 313 }
312 314 }
313 315 blank_string(strlen(str_hicb));
board/gdsys/common/Makefile
Diff comments   View file @ aba27ac
... ... @@ -13,6 +13,8 @@
13 13  
14 14 LIB = $(obj)lib$(VENDOR).o
15 15  
  16 +COBJS-$(CONFIG_SYS_FPGA_COMMON) += fpga.o
  17 +
16 18 COBJS-$(CONFIG_IO) += miiphybb.o
17 19 COBJS-$(CONFIG_IO64) += miiphybb.o
18 20 COBJS-$(CONFIG_IOCON) += osd.o
board/gdsys/common/fpga.c
Diff comments   View file @ aba27ac
  1 +/*
  2 + * (C) Copyright 2013
  3 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
  4 + *
  5 + * See file CREDITS for list of people who contributed to this
  6 + * project.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +
  24 +#include <common.h>
  25 +#include <gdsys_fpga.h>
  26 +
  27 +#include <asm/io.h>
  28 +
  29 +int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
  30 +{
  31 + out_le16(reg, data);
  32 +
  33 + return 0;
  34 +}
  35 +
  36 +int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
  37 +{
  38 + *data = in_le16(reg);
  39 +
  40 + return 0;
  41 +}
board/gdsys/common/osd.c
Diff comments   View file @ aba27ac
... ... @@ -6,8 +6,8 @@
6 6 */
7 7  
8 8 #include <common.h>
9   -#include <i2c.h>
10 9 #include <asm/io.h>
  10 +#include <i2c.h>
11 11  
12 12 #include <gdsys_fpga.h>
13 13  
14 14  
15 15  
16 16  
17 17  
18 18  
19 19  
... ... @@ -54,34 +54,41 @@
54 54 #if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178)
55 55 static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data)
56 56 {
57   - struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
58   - struct ihs_i2c *i2c = &fpga->i2c;
  57 + u16 val;
59 58  
60   - while (in_le16(&fpga->extended_interrupt) & (1 << 12))
61   - ;
62   - out_le16(&i2c->write_mailbox_ext, reg | (data << 8));
63   - out_le16(&i2c->write_mailbox, 0xc400 | (slave << 1));
  59 + do {
  60 + FPGA_GET_REG(screen, extended_interrupt, &val);
  61 + } while (val & (1 << 12));
  62 +
  63 + FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg | (data << 8));
  64 + FPGA_SET_REG(screen, i2c.write_mailbox, 0xc400 | (slave << 1));
64 65 }
65 66  
66 67 static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg)
67 68 {
68   - struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
69   - struct ihs_i2c *i2c = &fpga->i2c;
70 69 unsigned int ctr = 0;
  70 + u16 val;
71 71  
72   - while (in_le16(&fpga->extended_interrupt) & (1 << 12))
73   - ;
74   - out_le16(&fpga->extended_interrupt, 1 << 14);
75   - out_le16(&i2c->write_mailbox_ext, reg);
76   - out_le16(&i2c->write_mailbox, 0xc000 | (slave << 1));
77   - while (!(in_le16(&fpga->extended_interrupt) & (1 << 14))) {
  72 + do {
  73 + FPGA_GET_REG(screen, extended_interrupt, &val);
  74 + } while (val & (1 << 12));
  75 +
  76 + FPGA_SET_REG(screen, extended_interrupt, 1 << 14);
  77 + FPGA_SET_REG(screen, i2c.write_mailbox_ext, reg);
  78 + FPGA_SET_REG(screen, i2c.write_mailbox, 0xc000 | (slave << 1));
  79 +
  80 + FPGA_GET_REG(screen, extended_interrupt, &val);
  81 + while (!(val & (1 << 14))) {
78 82 udelay(100000);
79 83 if (ctr++ > 5) {
80 84 printf("iic receive timeout\n");
81 85 break;
82 86 }
  87 + FPGA_GET_REG(screen, extended_interrupt, &val);
83 88 }
84   - return in_le16(&i2c->read_mailbox_ext) >> 8;
  89 +
  90 + FPGA_GET_REG(screen, i2c.read_mailbox_ext, &val);
  91 + return val >> 8;
85 92 }
86 93 #endif
87 94  
... ... @@ -113,7 +120,6 @@
113 120  
114 121 static void mpc92469ac_set(unsigned screen, unsigned int fout)
115 122 {
116   - struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
117 123 unsigned int n;
118 124 unsigned int m;
119 125 unsigned int bitval = 0;
... ... @@ -134,7 +140,7 @@
134 140 break;
135 141 }
136 142  
137   - out_le16(&fpga->mpc3w_control, (bitval << 9) | m);
  143 + FPGA_SET_REG(screen, mpc3w_control, (bitval << 9) | m);
138 144 }
139 145 #endif
140 146  
141 147  
... ... @@ -249,14 +255,12 @@
249 255 static int osd_write_videomem(unsigned screen, unsigned offset,
250 256 u16 *data, size_t charcount)
251 257 {
252   - struct ihs_fpga *fpga =
253   - (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(screen);
254 258 unsigned int k;
255 259  
256 260 for (k = 0; k < charcount; ++k) {
257 261 if (offset + k >= BUFSIZE)
258 262 return -1;
259   - out_le16(&fpga->videomem + offset + k, data[k]);
  263 + FPGA_SET_REG(screen, videomem[offset + k], data[k]);
260 264 }
261 265  
262 266 return charcount;
263 267  
... ... @@ -302,14 +306,15 @@
302 306  
303 307 int osd_probe(unsigned screen)
304 308 {
305   - struct ihs_fpga *fpga = (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(screen);
306   - struct ihs_osd *osd = &fpga->osd;
307   - u16 version = in_le16(&osd->version);
308   - u16 features = in_le16(&osd->features);
  309 + u16 version;
  310 + u16 features;
309 311 unsigned width;
310 312 unsigned height;
311 313 u8 value;
312 314  
  315 + FPGA_GET_REG(0, osd.version, &version);
  316 + FPGA_GET_REG(0, osd.features, &features);
  317 +
313 318 width = ((features & 0x3f00) >> 8) + 1;
314 319 height = (features & 0x001f) + 1;
315 320  
316 321  
... ... @@ -356,12 +361,13 @@
356 361 fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
357 362 #endif
358 363  
359   - out_le16(&fpga->videocontrol, 0x0002);
360   - out_le16(&osd->control, 0x0049);
  364 + FPGA_SET_REG(screen, videocontrol, 0x0002);
  365 + FPGA_SET_REG(screen, osd.control, 0x0049);
361 366  
362   - out_le16(&osd->xy_size, ((32 - 1) << 8) | (16 - 1));
363   - out_le16(&osd->x_pos, 0x007f);
364   - out_le16(&osd->y_pos, 0x005f);
  367 + FPGA_SET_REG(screen, osd.xy_size, ((32 - 1) << 8) | (16 - 1));
  368 + FPGA_SET_REG(screen, osd.x_pos, 0x007f);
  369 + FPGA_SET_REG(screen, osd.y_pos, 0x005f);
  370 +
365 371  
366 372 return 0;
367 373 }
include/configs/dlvision-10g.h
Diff comments   View file @ aba27ac
... ... @@ -123,6 +123,12 @@
123 123  
124 124 #define CONFIG_SYS_FPGA_COUNT 2
125 125  
  126 +#define CONFIG_SYS_FPGA_PTR { \
  127 + (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
  128 + (struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
  129 +
  130 +#define CONFIG_SYS_FPGA_COMMON
  131 +
126 132 #define CONFIG_SYS_LATCH0_RESET 0xffff
127 133 #define CONFIG_SYS_LATCH0_BOOT 0xffff
128 134 #define CONFIG_SYS_LATCH1_RESET 0xffcf
include/configs/io.h
Diff comments   View file @ aba27ac
... ... @@ -230,6 +230,11 @@
230 230  
231 231 #define CONFIG_SYS_FPGA_COUNT 1
232 232  
  233 +#define CONFIG_SYS_FPGA_PTR \
  234 + { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
  235 +
  236 +#define CONFIG_SYS_FPGA_COMMON
  237 +
233 238 /* Memory Bank 3 (Latches) initialization */
234 239 #define CONFIG_SYS_LATCH_BASE 0x7f200000
235 240 #define CONFIG_SYS_EBC_PB3AP 0xa2015480
include/configs/io64.h
Diff comments   View file @ aba27ac
... ... @@ -498,6 +498,12 @@
498 498  
499 499 #define CONFIG_SYS_FPGA_COUNT 2
500 500  
  501 +#define CONFIG_SYS_FPGA_PTR { \
  502 + (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
  503 + (struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
  504 +
  505 +#define CONFIG_SYS_FPGA_COMMON
  506 +
501 507 #define CONFIG_SYS_LATCH0_RESET 0xffff
502 508 #define CONFIG_SYS_LATCH0_BOOT 0xffff
503 509 #define CONFIG_SYS_LATCH1_RESET 0xffbf
include/configs/iocon.h
Diff comments   View file @ aba27ac
... ... @@ -236,6 +236,11 @@
236 236  
237 237 #define CONFIG_SYS_FPGA_COUNT 1
238 238  
  239 +#define CONFIG_SYS_FPGA_PTR \
  240 + { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
  241 +
  242 +#define CONFIG_SYS_FPGA_COMMON
  243 +
239 244 /* Memory Bank 3 (Latches) initialization */
240 245 #define CONFIG_SYS_LATCH_BASE 0x7f200000
241 246 #define CONFIG_SYS_EBC_PB3AP 0x02025080
include/configs/neo.h
Diff comments   View file @ aba27ac
... ... @@ -222,6 +222,11 @@
222 222  
223 223 #define CONFIG_SYS_FPGA_COUNT 1
224 224  
  225 +#define CONFIG_SYS_FPGA_PTR \
  226 + { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
  227 +
  228 +#define CONFIG_SYS_FPGA_COMMON
  229 +
225 230 /* Memory Bank 3 (Latches) initialization */
226 231 #define CONFIG_SYS_LATCH_BASE 0x7f200000
227 232 #define CONFIG_SYS_EBC_PB3AP 0x92015480
include/gdsys_fpga.h
Diff comments   View file @ aba27ac
... ... @@ -19,6 +19,23 @@
19 19 int get_fpga_state(unsigned dev);
20 20 void print_fpga_state(unsigned dev);
21 21  
  22 +int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data);
  23 +int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data);
  24 +
  25 +extern struct ihs_fpga *fpga_ptr[];
  26 +
  27 +#define FPGA_SET_REG(ix, fld, val) \
  28 + fpga_set_reg((ix), \
  29 + &fpga_ptr[ix]->fld, \
  30 + offsetof(struct ihs_fpga, fld), \
  31 + val)
  32 +
  33 +#define FPGA_GET_REG(ix, fld, val) \
  34 + fpga_get_reg((ix), \
  35 + &fpga_ptr[ix]->fld, \
  36 + offsetof(struct ihs_fpga, fld), \
  37 + val)
  38 +
22 39 struct ihs_gpio {
23 40 u16 read;
24 41 u16 clear;
... ... @@ -67,6 +84,19 @@
67 84 #endif
68 85  
69 86 #ifdef CONFIG_IO64
  87 +
  88 +struct ihs_fpga_channel {
  89 + u16 status_int;
  90 + u16 config_int;
  91 + u16 switch_connect_config;
  92 + u16 tx_destination;
  93 +};
  94 +
  95 +struct ihs_fpga_hicb {
  96 + u16 status_int;
  97 + u16 config_int;
  98 +};
  99 +
70 100 struct ihs_fpga {
71 101 u16 reflection_low; /* 0x0000 */
72 102 u16 versions; /* 0x0002 */
... ... @@ -75,12 +105,9 @@
75 105 u16 reserved_0[5]; /* 0x0008 */
76 106 u16 quad_serdes_reset; /* 0x0012 */
77 107 u16 reserved_1[502]; /* 0x0014 */
78   - u16 ch0_status_int; /* 0x0400 */
79   - u16 ch0_config_int; /* 0x0402 */
80   - u16 reserved_2[126]; /* 0x0404 */
81   - u16 ch0_hicb_status_int;/* 0x0500 */
82   - u16 ch0_hicb_config_int;/* 0x0502 */
83   - u16 reserved_3[7549]; /* 0x0504 */
  108 + struct ihs_fpga_channel ch[32]; /* 0x0400 */
  109 + struct ihs_fpga_channel hicb_ch[32]; /* 0x0500 */
  110 + u16 reserved_2[7487]; /* 0x0580 */
84 111 u16 reflection_high; /* 0x3ffe */
85 112 };
86 113 #endif
... ... @@ -100,7 +127,7 @@
100 127 u16 reflection_high; /* 0x00fe */
101 128 struct ihs_osd osd; /* 0x0100 */
102 129 u16 reserved_3[889]; /* 0x010e */
103   - u16 videomem; /* 0x0800 */
  130 + u16 videomem[31736]; /* 0x0800 */
104 131 };
105 132 #endif
106 133  
... ... @@ -121,7 +148,7 @@
121 148 u16 reserved_4[176]; /* 0x00a0 */
122 149 struct ihs_osd osd; /* 0x0200 */
123 150 u16 reserved_5[761]; /* 0x020e */
124   - u16 videomem; /* 0x0800 */
  151 + u16 videomem[31736]; /* 0x0800 */
125 152 };
126 153 #endif
127 154