Eric Lee / smarc-uboot | Embedian Git Server

Commit abb25f4e9529c1b91d651c74af9bd3f1c955437b

Authored by Marek Vasut 2014-09-08 20:08:45 +0800

Exists in v2017.01-smarct4x and in 37 other branches

arm: socfpga: reset: Add function to reset FPGA bridges

Add function to enable and disable FPGA bridges. This code is used
by the FPGA manager to disable the bridges before programming the
FPGA and will later be also used by the initialization code for the
chip to put the chip into well defined state during startup.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

Showing 2 changed files with 40 additions and 0 deletions Inline Diff

arch/arm/cpu/armv7/socfpga/reset_manager.c
arch/arm/include/asm/arch-socfpga/reset_manager.h

arch/arm/cpu/armv7/socfpga/reset_manager.c

Diff comments View file @ abb25f4

 /*
  *  Copyright (C) 2013 Altera Corporation <www.altera.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/reset_manager.h>
+#include <asm/arch/fpga_manager.h>
 DECLARE_GLOBAL_DATA_PTR;
 static const struct socfpga_reset_manager *reset_manager_base =
 		(void *)SOCFPGA_RSTMGR_ADDRESS;
 /* Toggle reset signal to watchdog (WDT is disabled after this operation!) */
 void socfpga_watchdog_reset(void)
 {
 	/* assert reset for watchdog */
 	setbits_le32(&reset_manager_base->per_mod_reset,
 		     1 << RSTMGR_PERMODRST_L4WD0_LSB);
 	/* deassert watchdog from reset (watchdog in not running state) */
 	clrbits_le32(&reset_manager_base->per_mod_reset,
 		     1 << RSTMGR_PERMODRST_L4WD0_LSB);
 }
 /*
  * Write the reset manager register to cause reset
  */
 void reset_cpu(ulong addr)
 {
 	/* request a warm reset */
 	writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB),
 		&reset_manager_base->ctrl);
 	/*
 	 * infinite loop here as watchdog will trigger and reset
 	 * the processor
 	 */
 	while (1)
 		;
 }
 /*
  * Release peripherals from reset based on handoff
  */
 void reset_deassert_peripherals_handoff(void)
 {
 	writel(0, &reset_manager_base->per_mod_reset);
 }
+#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
+void socfpga_bridges_reset(int enable)
+{
+	/* For SoCFPGA-VT, this is NOP. */
+}
+#else
+#define L3REGS_REMAP_LWHPS2FPGA_MASK	0x10
+#define L3REGS_REMAP_HPS2FPGA_MASK	0x08
+#define L3REGS_REMAP_OCRAM_MASK		0x01
+void socfpga_bridges_reset(int enable)
+{
+	const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
+				L3REGS_REMAP_HPS2FPGA_MASK |
+				L3REGS_REMAP_OCRAM_MASK;
+	if (enable) {
+		/* brdmodrst */
+		writel(0xffffffff, &reset_manager_base->brg_mod_reset);
+	} else {
+		/* Check signal from FPGA. */
+		if (fpgamgr_poll_fpga_ready()) {
+			/* FPGA not ready. Wait for watchdog timeout. */
+			printf("%s: fpga not ready, hanging.\n", __func__);
+			hang();
+		}
+		/* brdmodrst */
+		writel(0, &reset_manager_base->brg_mod_reset);
+		/* Remap the bridges into memory map */
+		writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
+	}
+}
+#endif
 /* Change the reset state for EMAC 0 and EMAC 1 */
 void socfpga_emac_reset(int enable)
 {
 	const void *reset = &reset_manager_base->per_mod_reset;
 	if (enable) {
 		setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB);
 		setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB);
 	} else {
 #if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS)
 		clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB);
 #elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS)
 		clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB);
 #endif
 	}
 }

arch/arm/include/asm/arch-socfpga/reset_manager.h

Diff comments View file @ abb25f4

 /*
  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef	_RESET_MANAGER_H_
 #define	_RESET_MANAGER_H_
 void reset_cpu(ulong addr);
 void reset_deassert_peripherals_handoff(void);
+void socfpga_bridges_reset(int enable);
 void socfpga_emac_reset(int enable);
 void socfpga_watchdog_reset(void);
 struct socfpga_reset_manager {
 	u32	status;
 	u32	ctrl;
 	u32	counts;
 	u32	padding1;
 	u32	mpu_mod_reset;
 	u32	per_mod_reset;
 	u32	per2_mod_reset;
 	u32	brg_mod_reset;
 };
 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
 #else
 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
 #endif
 #define RSTMGR_PERMODRST_EMAC0_LSB	0
 #define RSTMGR_PERMODRST_EMAC1_LSB	1
 #define RSTMGR_PERMODRST_L4WD0_LSB	6
 #endif /* _RESET_MANAGER_H_ */