Commit abb25f4e9529c1b91d651c74af9bd3f1c955437b
1 parent
230fe9b202
Exists in
v2017.01-smarct4x
and in
37 other branches
arm: socfpga: reset: Add function to reset FPGA bridges
Add function to enable and disable FPGA bridges. This code is used by the FPGA manager to disable the bridges before programming the FPGA and will later be also used by the initialization code for the chip to put the chip into well defined state during startup. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
Showing 2 changed files with 40 additions and 0 deletions Side-by-side Diff
arch/arm/cpu/armv7/socfpga/reset_manager.c
| ... | ... | @@ -8,6 +8,7 @@ |
| 8 | 8 | #include <common.h> |
| 9 | 9 | #include <asm/io.h> |
| 10 | 10 | #include <asm/arch/reset_manager.h> |
| 11 | +#include <asm/arch/fpga_manager.h> | |
| 11 | 12 | |
| 12 | 13 | DECLARE_GLOBAL_DATA_PTR; |
| 13 | 14 | |
| ... | ... | @@ -49,6 +50,43 @@ |
| 49 | 50 | { |
| 50 | 51 | writel(0, &reset_manager_base->per_mod_reset); |
| 51 | 52 | } |
| 53 | + | |
| 54 | +#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) | |
| 55 | +void socfpga_bridges_reset(int enable) | |
| 56 | +{ | |
| 57 | + /* For SoCFPGA-VT, this is NOP. */ | |
| 58 | +} | |
| 59 | +#else | |
| 60 | + | |
| 61 | +#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10 | |
| 62 | +#define L3REGS_REMAP_HPS2FPGA_MASK 0x08 | |
| 63 | +#define L3REGS_REMAP_OCRAM_MASK 0x01 | |
| 64 | + | |
| 65 | +void socfpga_bridges_reset(int enable) | |
| 66 | +{ | |
| 67 | + const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK | | |
| 68 | + L3REGS_REMAP_HPS2FPGA_MASK | | |
| 69 | + L3REGS_REMAP_OCRAM_MASK; | |
| 70 | + | |
| 71 | + if (enable) { | |
| 72 | + /* brdmodrst */ | |
| 73 | + writel(0xffffffff, &reset_manager_base->brg_mod_reset); | |
| 74 | + } else { | |
| 75 | + /* Check signal from FPGA. */ | |
| 76 | + if (fpgamgr_poll_fpga_ready()) { | |
| 77 | + /* FPGA not ready. Wait for watchdog timeout. */ | |
| 78 | + printf("%s: fpga not ready, hanging.\n", __func__); | |
| 79 | + hang(); | |
| 80 | + } | |
| 81 | + | |
| 82 | + /* brdmodrst */ | |
| 83 | + writel(0, &reset_manager_base->brg_mod_reset); | |
| 84 | + | |
| 85 | + /* Remap the bridges into memory map */ | |
| 86 | + writel(l3mask, SOCFPGA_L3REGS_ADDRESS); | |
| 87 | + } | |
| 88 | +} | |
| 89 | +#endif | |
| 52 | 90 | |
| 53 | 91 | /* Change the reset state for EMAC 0 and EMAC 1 */ |
| 54 | 92 | void socfpga_emac_reset(int enable) |
arch/arm/include/asm/arch-socfpga/reset_manager.h