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Commit abbab70363dcdb270cbf24d47849214dd3a3e010

Authored by Troy Kisky
Committed by Stefano Babic
1 parent 17c5ef2007
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

mx31/mx35/mx51/mx53/mx6: add watchdog 

Use a common watchdog driver for all these cpus.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>

Showing 16 changed files with 106 additions and 101 deletions Side-by-side Diff

arch/arm/cpu/arm1136/mx31/timer.c
Diff comments   View file @ abbab70
... ... @@ -161,43 +161,4 @@
161 161 {
162 162 return MXC_CLK32;
163 163 }
164   -
165   -void reset_cpu(ulong addr)
166   -{
167   - struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE;
168   - wdog->wcr = WDOG_ENABLE;
169   - while (1)
170   - ;
171   -}
172   -
173   -#ifdef CONFIG_HW_WATCHDOG
174   -void mxc_hw_watchdog_enable(void)
175   -{
176   - struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE;
177   - u16 secs;
178   -
179   - /*
180   - * The timer watchdog can be set between
181   - * 0.5 and 128 Seconds. If not defined
182   - * in configuration file, sets 64 Seconds
183   - */
184   -#ifdef CONFIG_SYS_WD_TIMER_SECS
185   - secs = (CONFIG_SYS_WD_TIMER_SECS << 1) & 0xFF;
186   - if (!secs) secs = 1;
187   -#else
188   - secs = 64;
189   -#endif
190   - setbits_le16(&wdog->wcr, (secs << WDOG_WT_SHIFT) | WDOG_ENABLE
191   - | WDOG_WDZST);
192   -}
193   -
194   -
195   -void mxc_hw_watchdog_reset(void)
196   -{
197   - struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE;
198   -
199   - writew(0x5555, &wdog->wsr);
200   - writew(0xAAAA, &wdog->wsr);
201   -}
202   -#endif
arch/arm/cpu/arm1136/mx35/generic.c
Diff comments   View file @ abbab70
... ... @@ -488,12 +488,6 @@
488 488 return 0;
489 489 }
490 490  
491   -void reset_cpu(ulong addr)
492   -{
493   - struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
494   - writew(4, &wdog->wcr);
495   -}
496   -
497 491 #define RCSR_MEM_CTL_WEIM 0
498 492 #define RCSR_MEM_CTL_NAND 1
499 493 #define RCSR_MEM_CTL_ATA 2
arch/arm/imx-common/cpu.c
Diff comments   View file @ abbab70
... ... @@ -175,11 +175,6 @@
175 175 }
176 176 #endif
177 177  
178   -void reset_cpu(ulong addr)
179   -{
180   - __raw_writew(4, WDOG1_BASE_ADDR);
181   -}
182   -
183 178 u32 get_ahb_clk(void)
184 179 {
185 180 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
arch/arm/include/asm/arch-mx31/clock.h
Diff comments   View file @ abbab70
... ... @@ -58,8 +58,6 @@
58 58 void mx31_uart1_hw_init(void);
59 59 void mx31_uart2_hw_init(void);
60 60 void mx31_spi2_hw_init(void);
61   -void mxc_hw_watchdog_enable(void);
62   -void mxc_hw_watchdog_reset(void);
63 61  
64 62 #endif /* __ASM_ARCH_CLOCK_H */
arch/arm/include/asm/arch-mx31/imx-regs.h
Diff comments   View file @ abbab70
... ... @@ -68,17 +68,6 @@
68 68 u32 test;
69 69 };
70 70  
71   -/* Watchdog Timer (WDOG) registers */
72   -#define WDOG_ENABLE (1 << 2)
73   -#define WDOG_WT_SHIFT 8
74   -#define WDOG_WDZST (1 << 0)
75   -
76   -struct wdog_regs {
77   - u16 wcr; /* Control */
78   - u16 wsr; /* Service */
79   - u16 wrsr; /* Reset Status */
80   -};
81   -
82 71 /* IIM Control Registers */
83 72 struct iim_regs {
84 73 u32 iim_stat;
... ... @@ -687,7 +676,7 @@
687 676  
688 677 #define ARM_PPMRR 0x40000015
689 678  
690   -#define WDOG_BASE 0x53FDC000
  679 +#define WDOG1_BASE_ADDR 0x53FDC000
691 680  
692 681 /*
693 682 * GPIO
arch/arm/include/asm/arch-mx35/imx-regs.h
Diff comments   View file @ abbab70
... ... @@ -80,7 +80,7 @@
80 80 #define GPIO2_BASE_ADDR 0x53FD0000
81 81 #define SDMA_BASE_ADDR 0x53FD4000
82 82 #define RTC_BASE_ADDR 0x53FD8000
83   -#define WDOG_BASE_ADDR 0x53FDC000
  83 +#define WDOG1_BASE_ADDR 0x53FDC000
84 84 #define PWM_BASE_ADDR 0x53FE0000
85 85 #define RTIC_BASE_ADDR 0x53FEC000
86 86 #define IIM_BASE_ADDR 0x53FF0000
... ... @@ -290,15 +290,6 @@
290 290 u32 stat;
291 291 u32 period;
292 292 u32 test;
293   -};
294   -
295   -/* Watchdog Timer (WDOG) registers */
296   -struct wdog_regs {
297   - u16 wcr; /* Control */
298   - u16 wsr; /* Service */
299   - u16 wrsr; /* Reset Status */
300   - u16 wicr; /* Interrupt Control */
301   - u16 wmcr; /* Misc Control */
302 293 };
303 294  
304 295 struct esdc_regs {
arch/arm/include/asm/arch-mx5/imx-regs.h
Diff comments   View file @ abbab70
... ... @@ -218,16 +218,6 @@
218 218 */
219 219 #define WBED 1
220 220  
221   -/*
222   - * WEIM WCR
223   - */
224   -#define BCM 1
225   -#define GBCD(x) (((x) & 0x3) << 1)
226   -#define INTEN (1 << 4)
227   -#define INTPOL (1 << 5)
228   -#define WDOG_EN (1 << 8)
229   -#define WDOG_LIMIT(x) (((x) & 0x3) << 9)
230   -
231 221 #define CS0_128 0
232 222 #define CS0_64M_CS1_64M 1
233 223 #define CS0_64M_CS1_32M_CS2_32M 2
board/davedenx/qong/qong.c
Diff comments   View file @ abbab70
... ... @@ -37,13 +37,6 @@
37 37  
38 38 DECLARE_GLOBAL_DATA_PTR;
39 39  
40   -#ifdef CONFIG_HW_WATCHDOG
41   -void hw_watchdog_reset(void)
42   -{
43   - mxc_hw_watchdog_reset();
44   -}
45   -#endif
46   -
47 40 int dram_init(void)
48 41 {
49 42 /* dram_init must store complete ramsize in gd->ram_size */
... ... @@ -188,7 +181,7 @@
188 181 pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
189 182  
190 183 #ifdef CONFIG_HW_WATCHDOG
191   - mxc_hw_watchdog_enable();
  184 + hw_watchdog_init();
192 185 #endif
193 186  
194 187 return 0;
board/freescale/mx31pdk/mx31pdk.c
Diff comments   View file @ abbab70
... ... @@ -36,13 +36,6 @@
36 36  
37 37 DECLARE_GLOBAL_DATA_PTR;
38 38  
39   -#ifdef CONFIG_HW_WATCHDOG
40   -void hw_watchdog_reset(void)
41   -{
42   - mxc_hw_watchdog_reset();
43   -}
44   -#endif
45   -
46 39 int dram_init(void)
47 40 {
48 41 /* dram_init must store complete ramsize in gd->ram_size */
... ... @@ -98,7 +91,7 @@
98 91 pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
99 92 pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
100 93 #ifdef CONFIG_HW_WATCHDOG
101   - mxc_hw_watchdog_enable();
  94 + hw_watchdog_init();
102 95 #endif
103 96 return 0;
104 97 }
board/hale/tt01/tt01.c
Diff comments   View file @ abbab70
... ... @@ -179,7 +179,7 @@
179 179 int board_late_init(void)
180 180 {
181 181 #ifdef CONFIG_HW_WATCHDOG
182   - mxc_hw_watchdog_enable();
  182 + hw_watchdog_init();
183 183 #endif
184 184  
185 185 return 0;
  1 +Watchdog driver general info
  2 +
  3 +CONFIG_HW_WATCHDOG
  4 + This enables hw_watchdog_reset to be called during various loops,
  5 + including waiting for a character on a serial port. But it
  6 + does not also call hw_watchdog_init. Boards which want this
  7 + enabled must call this function in their board file. This split
  8 + is useful because some rom's enable the watchdog when downloading
  9 + new code, so it must be serviced, but the board would rather it
  10 + was off. And, it cannot always be turned off once on.
  11 +
  12 +CONFIG_WATCHDOG_TIMEOUT_MSECS
  13 + Can be used to change the timeout for i.mx31/35/5x/6x.
  14 + If not given, will default to maximum timeout. This would
  15 + be 128000 msec for i.mx31/35/5x/6x.
  16 +
  17 +CONFIG_AT91SAM9_WATCHDOG
  18 + Available for AT91SAM9 to service the watchdog.
  19 +
  20 +CONFIG_FTWDT010_WATCHDOG
  21 + Available for FTWDT010 to service the watchdog.
  22 +
  23 +CONFIG_FTWDT010_HW_TIMEOUT
  24 + Can be used to change the timeout for FTWDT010.
  25 +
  26 +CONFIG_IMX_WATCHDOG
  27 + Available for i.mx31/35/5x/6x to service the watchdog. This is not
  28 + automatically set because some boards (vision2) still need to define
  29 + their own hw_watchdog_reset routine.
drivers/watchdog/Makefile
Diff comments   View file @ abbab70
... ... @@ -27,6 +27,9 @@
27 27  
28 28 COBJS-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o
29 29 COBJS-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
  30 +ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6))
  31 +COBJS-y += imx_watchdog.o
  32 +endif
30 33 COBJS-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o
31 34 COBJS-$(CONFIG_S5P) += s5p_wdt.o
32 35  
drivers/watchdog/imx_watchdog.c
Diff comments   View file @ abbab70
  1 +/*
  2 + * watchdog.c - driver for i.mx on-chip watchdog
  3 + *
  4 + * Licensed under the GPL-2 or later.
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <asm/io.h>
  9 +#include <watchdog.h>
  10 +#include <asm/arch/imx-regs.h>
  11 +
  12 +struct watchdog_regs {
  13 + u16 wcr; /* Control */
  14 + u16 wsr; /* Service */
  15 + u16 wrsr; /* Reset Status */
  16 +};
  17 +
  18 +#define WCR_WDZST 0x01
  19 +#define WCR_WDBG 0x02
  20 +#define WCR_WDE 0x04 /* WDOG enable */
  21 +#define WCR_WDT 0x08
  22 +#define WCR_WDW 0x80
  23 +#define SET_WCR_WT(x) (x << 8)
  24 +
  25 +#ifdef CONFIG_IMX_WATCHDOG
  26 +void hw_watchdog_reset(void)
  27 +{
  28 + struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
  29 +
  30 + writew(0x5555, &wdog->wsr);
  31 + writew(0xaaaa, &wdog->wsr);
  32 +}
  33 +
  34 +void hw_watchdog_init(void)
  35 +{
  36 + struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
  37 + u16 timeout;
  38 +
  39 + /*
  40 + * The timer watchdog can be set between
  41 + * 0.5 and 128 Seconds. If not defined
  42 + * in configuration file, sets 128 Seconds
  43 + */
  44 +#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
  45 +#define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000
  46 +#endif
  47 + timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1;
  48 + writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT |
  49 + WCR_WDW | SET_WCR_WT(timeout), &wdog->wcr);
  50 + hw_watchdog_reset();
  51 +}
  52 +#endif
  53 +
  54 +void reset_cpu(ulong addr)
  55 +{
  56 + struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
  57 +
  58 + writew(WCR_WDE, &wdog->wcr);
  59 + writew(0x5555, &wdog->wsr);
  60 + writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */
  61 + while (1) {
  62 + /*
  63 + * spin for .5 seconds before reset
  64 + */
  65 + }
  66 +}
include/configs/mx31pdk.h
Diff comments   View file @ abbab70
... ... @@ -61,6 +61,7 @@
61 61 #define CONFIG_MXC_UART
62 62 #define CONFIG_MXC_UART_BASE UART1_BASE
63 63 #define CONFIG_HW_WATCHDOG
  64 +#define CONFIG_IMX_WATCHDOG
64 65 #define CONFIG_MXC_GPIO
65 66  
66 67 #define CONFIG_HARD_SPI
include/configs/qong.h
Diff comments   View file @ abbab70
... ... @@ -52,6 +52,7 @@
52 52  
53 53 #define CONFIG_MXC_GPIO
54 54 #define CONFIG_HW_WATCHDOG
  55 +#define CONFIG_IMX_WATCHDOG
55 56  
56 57 #define CONFIG_MXC_SPI
57 58 #define CONFIG_DEFAULT_SPI_BUS 1
... ... @@ -35,6 +35,7 @@
35 35 * Hardware watchdog
36 36 */
37 37 #ifdef CONFIG_HW_WATCHDOG
  38 + void hw_watchdog_init(void);
38 39 #if defined(__ASSEMBLY__)
39 40 #define WATCHDOG_RESET bl hw_watchdog_reset
40 41 #else