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Commit abc20aba1834c321a638b367c18dcce1bb4e232d

Authored by Marek Vasut
Committed by Albert ARIBAUD
1 parent 3e43c749f2
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

PXA: Rename CONFIG_PXA2[57]X to CONFIG_CPU_PXA2[57]X 

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>

Showing 24 changed files with 80 additions and 76 deletions Side-by-side Diff

arch/arm/cpu/pxa/cpu.c
Diff comments   View file @ abc20ab
... ... @@ -234,21 +234,21 @@
234 234 writel(CONFIG_SYS_GPSR0_VAL, GPSR0);
235 235 writel(CONFIG_SYS_GPSR1_VAL, GPSR1);
236 236 writel(CONFIG_SYS_GPSR2_VAL, GPSR2);
237   -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
  237 +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
238 238 writel(CONFIG_SYS_GPSR3_VAL, GPSR3);
239 239 #endif
240 240  
241 241 writel(CONFIG_SYS_GPCR0_VAL, GPCR0);
242 242 writel(CONFIG_SYS_GPCR1_VAL, GPCR1);
243 243 writel(CONFIG_SYS_GPCR2_VAL, GPCR2);
244   -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
  244 +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
245 245 writel(CONFIG_SYS_GPCR3_VAL, GPCR3);
246 246 #endif
247 247  
248 248 writel(CONFIG_SYS_GPDR0_VAL, GPDR0);
249 249 writel(CONFIG_SYS_GPDR1_VAL, GPDR1);
250 250 writel(CONFIG_SYS_GPDR2_VAL, GPDR2);
251   -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
  251 +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
252 252 writel(CONFIG_SYS_GPDR3_VAL, GPDR3);
253 253 #endif
254 254  
... ... @@ -258,7 +258,7 @@
258 258 writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U);
259 259 writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L);
260 260 writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U);
261   -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
  261 +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
262 262 writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L);
263 263 writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U);
264 264 #endif
... ... @@ -270,7 +270,7 @@
270 270 {
271 271 writel(0, ICLR);
272 272 writel(0, ICMR);
273   -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
  273 +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
274 274 writel(0, ICLR2);
275 275 writel(0, ICMR2);
276 276 #endif
arch/arm/cpu/pxa/start.S
Diff comments   View file @ abc20ab
... ... @@ -39,7 +39,7 @@
39 39 #include <config.h>
40 40 #include <version.h>
41 41  
42   -#ifdef CONFIG_PXA25X
  42 +#ifdef CONFIG_CPU_PXA25X
43 43 #if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800)
44 44 #error "Init SP address must be set to 0xfffff800 for PXA250"
45 45 #endif
... ... @@ -160,7 +160,7 @@
160 160 bl cpu_init_crit
161 161 #endif
162 162  
163   -#ifdef CONFIG_PXA250
  163 +#ifdef CONFIG_CPU_PXA25X
164 164 bl lock_cache_for_stack
165 165 #endif
166 166  
... ... @@ -191,7 +191,7 @@
191 191 mov sp, r4
192 192  
193 193 /* Disable the Dcache RAM lock for stack now */
194   -#ifdef CONFIG_PXA250
  194 +#ifdef CONFIG_CPU_PXA25X
195 195 bl cpu_init_crit
196 196 #endif
197 197  
... ... @@ -307,7 +307,7 @@
307 307 *
308 308 *************************************************************************
309 309 */
310   -#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_PXA250)
  310 +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
311 311 cpu_init_crit:
312 312 /*
313 313 * flush v4 I/D caches
... ... @@ -327,7 +327,7 @@
327 327 mcr p15, 0, r0, c1, c0, 0
328 328  
329 329 mov pc, lr /* back to my caller */
330   -#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_PXA250 */
  330 +#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */
331 331  
332 332 #ifndef CONFIG_SPL_BUILD
333 333 /*
... ... @@ -519,7 +519,7 @@
519 519 * This is useful on PXA25x and PXA26x in early bootstages, where there is no
520 520 * other possible memory available to hold stack.
521 521 */
522   -#ifdef CONFIG_PXA250
  522 +#ifdef CONFIG_CPU_PXA25X
523 523 .macro CPWAIT reg
524 524 mrc p15, 0, \reg, c2, c0, 0
525 525 mov \reg, \reg
... ... @@ -602,5 +602,5 @@
602 602  
603 603 /* 0xfff00000 : 1:1, cached mapping */
604 604 .word (0xfff << 20) | 0x1c1e
605   -#endif /* CONFIG_PXA250 */
  605 +#endif /* CONFIG_CPU_PXA25X */
arch/arm/cpu/pxa/timer.c
Diff comments   View file @ abc20ab
... ... @@ -35,9 +35,9 @@
35 35 #error: interrupts not implemented yet
36 36 #endif
37 37  
38   -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
  38 +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
39 39 #define TIMER_FREQ_HZ 3250000
40   -#elif defined(CONFIG_PXA250)
  40 +#elif defined(CONFIG_CPU_PXA25X)
41 41 #define TIMER_FREQ_HZ 3686400
42 42 #else
43 43 #error "Timer frequency unknown - please config PXA CPU type"
arch/arm/cpu/pxa/usb.c
Diff comments   View file @ abc20ab
... ... @@ -24,7 +24,7 @@
24 24 #include <common.h>
25 25  
26 26 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
27   -# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
  27 +# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X)
28 28  
29 29 #include <asm/arch/pxa-regs.h>
30 30 #include <asm/io.h>
... ... @@ -37,7 +37,7 @@
37 37 writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA);
38 38 udelay(100);
39 39 #endif
40   -#if defined(CONFIG_PXA27X)
  40 +#if defined(CONFIG_CPU_PXA27X)
41 41 /* Enable USB host clock. */
42 42 writel(readl(CKEN) | CKEN10_USBHOST, CKEN);
43 43 #endif
... ... @@ -58,7 +58,7 @@
58 58 #if defined(CONFIG_CPU_MONAHANS)
59 59 writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
60 60 #endif
61   -#if defined(CONFIG_PXA27X)
  61 +#if defined(CONFIG_CPU_PXA27X)
62 62 writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR);
63 63 #endif
64 64 writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR);
... ... @@ -78,7 +78,7 @@
78 78 #if defined(CONFIG_CPU_MONAHANS)
79 79 writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR);
80 80 #endif
81   -#if defined(CONFIG_PXA27X)
  81 +#if defined(CONFIG_CPU_PXA27X)
82 82 writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR);
83 83 #endif
84 84 writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR);
... ... @@ -88,7 +88,7 @@
88 88 writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA);
89 89 udelay(100);
90 90 #endif
91   -#if defined(CONFIG_PXA27X)
  91 +#if defined(CONFIG_CPU_PXA27X)
92 92 /* Disable USB host clock. */
93 93 writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
94 94 #endif
... ... @@ -101,6 +101,6 @@
101 101 return usb_cpu_stop();
102 102 }
103 103  
104   -# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) */
  104 +# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X) */
105 105 #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
arch/arm/include/asm/arch-pxa/pxa-regs.h
Diff comments   View file @ abc20ab
... ... @@ -109,7 +109,7 @@
109 109 #define DCSR13 0x40000034 /* DMA Control / Status Register for Channel 13 */
110 110 #define DCSR14 0x40000038 /* DMA Control / Status Register for Channel 14 */
111 111 #define DCSR15 0x4000003c /* DMA Control / Status Register for Channel 15 */
112   -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
  112 +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
113 113 #define DCSR16 0x40000040 /* DMA Control / Status Register for Channel 16 */
114 114 #define DCSR17 0x40000044 /* DMA Control / Status Register for Channel 17 */
115 115 #define DCSR18 0x40000048 /* DMA Control / Status Register for Channel 18 */
... ... @@ -126,7 +126,7 @@
126 126 #define DCSR29 0x40000074 /* DMA Control / Status Register for Channel 29 */
127 127 #define DCSR30 0x40000078 /* DMA Control / Status Register for Channel 30 */
128 128 #define DCSR31 0x4000007c /* DMA Control / Status Register for Channel 31 */
129   -#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
  129 +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
130 130  
131 131 #define DCSR(x) (0x40000000 | ((x) << 2))
132 132  
... ... @@ -134,7 +134,7 @@
134 134 #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
135 135 #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
136 136  
137   -#if defined(CONFIG_PXA27X) || defined (CONFIG_CPU_MONAHANS)
  137 +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
138 138 #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
139 139 #define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
140 140 #define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
... ... @@ -438,7 +438,7 @@
438 438 /*
439 439 * USB Device Controller
440 440 */
441   -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
  441 +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
442 442  
443 443 #define UDCCR 0x40600000 /* UDC Control Register */
444 444 #define UDCCR_UDE (1 << 0) /* UDC enable */
445 445  
... ... @@ -797,9 +797,9 @@
797 797 #define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST)
798 798 #define UDC_BCR_MASK (0x3ff)
799 799  
800   -#endif /* CONFIG_PXA27X */
  800 +#endif /* CONFIG_CPU_PXA27X */
801 801  
802   -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
  802 +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
803 803  
804 804 /******************************************************************************/
805 805 /*
... ... @@ -870,7 +870,7 @@
870 870 #define UP2OCR_CPVPE (1<<1)
871 871 #define UP2OCR_CPVEN (1<<0)
872 872  
873   -#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
  873 +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
874 874  
875 875 /******************************************************************************/
876 876 /*
... ... @@ -923,7 +923,7 @@
923 923 #define OWER 0x40A00018 /* OS Timer Watchdog Enable Register */
924 924 #define OIER 0x40A0001C /* OS Timer Interrupt Enable Register */
925 925  
926   -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
  926 +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
927 927 #define OSCR4 0x40A00040 /* OS Timer Counter Register 4 */
928 928 #define OSCR5 0x40A00044 /* OS Timer Counter Register 5 */
929 929 #define OSCR6 0x40A00048 /* OS Timer Counter Register 6 */
... ... @@ -951,7 +951,7 @@
951 951 #define OMCR10 0x40A000D8 /* OS Match Control Register 10 */
952 952 #define OMCR11 0x40A000DC /* OS Match Control Register 11 */
953 953  
954   -#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
  954 +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
955 955  
956 956 #define OSSR_M4 (1 << 4) /* Match status channel 4 */
957 957 #define OSSR_M3 (1 << 3) /* Match status channel 3 */
... ... @@ -1052,7 +1052,7 @@
1052 1052 #define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */
1053 1053  
1054 1054 #define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
1055   -#if !defined(CONFIG_PXA27X)
  1055 +#if !defined(CONFIG_CPU_PXA27X)
1056 1056 #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
1057 1057 #endif
1058 1058 #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
... ... @@ -1071,7 +1071,7 @@
1071 1071 #define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */
1072 1072 #define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */
1073 1073 #define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */
1074   -#if defined(CONFIG_PXA27X)
  1074 +#if defined(CONFIG_CPU_PXA27X)
1075 1075 #define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */
1076 1076 #define CKEN24_CAMERA (1 << 24) /* Camera Unit Clock Enable */
1077 1077 #endif
... ... @@ -1087,7 +1087,7 @@
1087 1087 #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
1088 1088 #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
1089 1089  
1090   -#if !defined(CONFIG_PXA27X)
  1090 +#if !defined(CONFIG_CPU_PXA27X)
1091 1091 #define CCCR_L09 (0x1F)
1092 1092 #define CCCR_L27 (0x1)
1093 1093 #define CCCR_L32 (0x2)
... ... @@ -1120,7 +1120,7 @@
1120 1120 #define PWM_PWDUTY1 0x40C00004 /* PWM 1 Duty Cycle Register */
1121 1121 #define PWM_PERVAL1 0x40C00008 /* PWM 1 Period Control Register */
1122 1122  
1123   -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
  1123 +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
1124 1124 #define PWM_CTRL2 0x40B00010 /* PWM 2 Control Register */
1125 1125 #define PWM_PWDUTY2 0x40B00014 /* PWM 2 Duty Cycle Register */
1126 1126 #define PWM_PERVAL2 0x40B00018 /* PWM 2 Period Control Register */
... ... @@ -1128,7 +1128,7 @@
1128 1128 #define PWM_CTRL3 0x40C00010 /* PWM 3 Control Register */
1129 1129 #define PWM_PWDUTY3 0x40C00014 /* PWM 3 Duty Cycle Register */
1130 1130 #define PWM_PERVAL3 0x40C00018 /* PWM 3 Period Control Register */
1131   -#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
  1131 +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
1132 1132  
1133 1133 /*
1134 1134 * Interrupt Controller
1135 1135  
... ... @@ -1140,14 +1140,14 @@
1140 1140 #define ICPR 0x40D00010 /* Interrupt Controller Pending Register */
1141 1141 #define ICCR 0x40D00014 /* Interrupt Controller Control Register */
1142 1142  
1143   -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
  1143 +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
1144 1144 #define ICHP 0x40D00018 /* Interrupt Controller Highest Priority Register */
1145 1145 #define ICIP2 0x40D0009C /* Interrupt Controller IRQ Pending Register 2 */
1146 1146 #define ICMR2 0x40D000A0 /* Interrupt Controller Mask Register 2 */
1147 1147 #define ICLR2 0x40D000A4 /* Interrupt Controller Level Register 2 */
1148 1148 #define ICFP2 0x40D000A8 /* Interrupt Controller FIQ Pending Register 2 */
1149 1149 #define ICPR2 0x40D000AC /* Interrupt Controller Pending Register 2 */
1150   -#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
  1150 +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
1151 1151  
1152 1152 /******************************************************************************/
1153 1153 /*
... ... @@ -1188,7 +1188,7 @@
1188 1188 #define GAFR2_L 0x40E00064 /* GPIO Alternate Function Select Register GPIO<79:64> */
1189 1189 #define GAFR2_U 0x40E00068 /* GPIO Alternate Function Select Register GPIO 80 */
1190 1190  
1191   -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
  1191 +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
1192 1192 #define GPLR3 0x40E00100 /* GPIO Pin-Level Register GPIO<127:96> */
1193 1193 #define GPDR3 0x40E0010C /* GPIO Pin Direction Register GPIO<127:96> */
1194 1194 #define GPSR3 0x40E00118 /* GPIO Pin Output Set Register GPIO<127:96> */
... ... @@ -1198,7 +1198,7 @@
1198 1198 #define GEDR3 0x40E00148 /* GPIO Edge Detect Status Register GPIO<127:96> */
1199 1199 #define GAFR3_L 0x40E0006C /* GPIO Alternate Function Select Register GPIO<111:96> */
1200 1200 #define GAFR3_U 0x40E00070 /* GPIO Alternate Function Select Register GPIO<127:112> */
1201   -#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
  1201 +#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
1202 1202  
1203 1203 #ifdef CONFIG_CPU_MONAHANS
1204 1204 #define GSDR0 0x40E00400 /* Bit-wise Set of GPDR[31:0] */
... ... @@ -1244,7 +1244,7 @@
1244 1244 #define _GEDR(x) (0x40E00048 + (((x) & 0x60) >> 3))
1245 1245 #define _GAFR(x) (0x40E00054 + (((x) & 0x70) >> 2))
1246 1246  
1247   -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
  1247 +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
1248 1248 #define GPLR(x) (((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3))
1249 1249 #define GPDR(x) (((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3))
1250 1250 #define GPSR(x) (((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3))
... ... @@ -2123,7 +2123,7 @@
2123 2123 #define LCCR0_PDD_S 12
2124 2124 #define LCCR0_BM (1 << 20) /* Branch mask */
2125 2125 #define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */
2126   -#if defined(CONFIG_PXA27X)
  2126 +#if defined(CONFIG_CPU_PXA27X)
2127 2127 #define LCCR0_LCDT (1 << 22) /* LCD Panel Type */
2128 2128 #define LCCR0_RDSTM (1 << 23) /* Read Status Interrupt Mask */
2129 2129 #define LCCR0_CMDIM (1 << 24) /* Command Interrupt Mask */
... ... @@ -2249,7 +2249,7 @@
2249 2249 #define LCSR1_IU6 (1 << 29)
2250 2250  
2251 2251 #define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
2252   -#if defined(CONFIG_PXA27X)
  2252 +#if defined(CONFIG_CPU_PXA27X)
2253 2253 #define LDCMD_SOFINT (1 << 22)
2254 2254 #define LDCMD_EOFINT (1 << 21)
2255 2255 #endif
... ... @@ -2480,7 +2480,7 @@
2480 2480 #define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
2481 2481 #define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
2482 2482  
2483   -#if defined(CONFIG_PXA27X)
  2483 +#if defined(CONFIG_CPU_PXA27X)
2484 2484  
2485 2485 #define ARB_CNTRL 0x48000048 /* Arbiter Control Register */
2486 2486  
... ... @@ -2494,7 +2494,7 @@
2494 2494 #define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
2495 2495 #define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
2496 2496  
2497   -#endif /* CONFIG_PXA27X */
  2497 +#endif /* CONFIG_CPU_PXA27X */
2498 2498  
2499 2499 /* LCD registers */
2500 2500 #define LCCR4 0x44000010 /* LCD Controller Control Register 4 */
... ... @@ -2628,7 +2628,7 @@
2628 2628 #define OSCR4 0x40A00040 /* OS Timer Counter Register */
2629 2629 #define OMCR4 0x40A000C0 /* */
2630 2630  
2631   -#endif /* CONFIG_PXA27X */
  2631 +#endif /* CONFIG_CPU_PXA27X */
2632 2632  
2633 2633 #endif /* _PXA_REGS_H_ */
... ... @@ -41,7 +41,9 @@
41 41 #include <lcd.h>
42 42 #include <watchdog.h>
43 43  
44   -#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
  44 +#if defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \
  45 + defined(CONFIG_CPU_MONAHANS)
  46 +#define CONFIG_CPU_PXA
45 47 #include <asm/byteorder.h>
46 48 #endif
47 49  
... ... @@ -512,7 +514,7 @@
512 514 uchar *bmap;
513 515 uchar *fb;
514 516 ushort *fb16;
515   -#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
  517 +#if defined(CONFIG_CPU_PXA)
516 518 struct pxafb_info *fbi = &panel_info.pxa;
517 519 #elif defined(CONFIG_MPC823)
518 520 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
... ... @@ -528,7 +530,7 @@
528 530  
529 531 if (NBITS(panel_info.vl_bpix) < 12) {
530 532 /* Leave room for default color map */
531   -#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
  533 +#if defined(CONFIG_CPU_PXA)
532 534 cmap = (ushort *)fbi->palette;
533 535 #elif defined(CONFIG_MPC823)
534 536 cmap = (ushort *)&(cp->lcd_cmap[BMP_LOGO_OFFSET*sizeof(ushort)]);
... ... @@ -623,7 +625,7 @@
623 625 unsigned long width, height, byte_width;
624 626 unsigned long pwidth = panel_info.vl_col;
625 627 unsigned colors, bpix, bmp_bpix;
626   -#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
  628 +#if defined(CONFIG_CPU_PXA)
627 629 struct pxafb_info *fbi = &panel_info.pxa;
628 630 #elif defined(CONFIG_MPC823)
629 631 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
... ... @@ -663,7 +665,7 @@
663 665 #if !defined(CONFIG_MCC200)
664 666 /* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */
665 667 if (bmp_bpix == 8) {
666   -#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
  668 +#if defined(CONFIG_CPU_PXA)
667 669 cmap = (ushort *)fbi->palette;
668 670 #elif defined(CONFIG_MPC823)
669 671 cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]);
... ... @@ -752,7 +754,7 @@
752 754 WATCHDOG_RESET();
753 755 for (j = 0; j < width; j++) {
754 756 if (bpix != 16) {
755   -#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS || defined(CONFIG_ATMEL_LCD)
  757 +#if defined(CONFIG_CPU_PXA) || defined(CONFIG_ATMEL_LCD)
756 758 *(fb++) = *(bmap++);
757 759 #elif defined(CONFIG_MPC823) || defined(CONFIG_MCC200)
758 760 *(fb++) = 255 - *(bmap++);
drivers/mmc/pxa_mmc.c
Diff comments   View file @ abc20ab
... ... @@ -129,7 +129,7 @@
129 129 writel(~MMC_I_MASK_RXFIFO_RD_REQ, MMC_I_MASK);
130 130 while (len) {
131 131 if (readl(MMC_I_REG) & MMC_I_REG_RXFIFO_RD_REQ) {
132   -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
  132 +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
133 133 int i;
134 134 for (i = min(len, 32); i; i--) {
135 135 *dst++ = readb(MMC_RXFIFO);
... ... @@ -560,7 +560,8 @@
560 560 /* Reset device interface type */
561 561 mmc_dev.if_type = IF_TYPE_UNKNOWN;
562 562  
563   -#if defined (CONFIG_LUBBOCK) || (defined (CONFIG_GUMSTIX) && !defined(CONFIG_PXA27X))
  563 +#if defined(CONFIG_LUBBOCK) || \
  564 + (defined(CONFIG_GUMSTIX) && !defined(CONFIG_CPU_PXA27X))
564 565 set_GPIO_mode(GPIO6_MMCCLK_MD);
565 566 set_GPIO_mode(GPIO8_MMCCS0_MD);
566 567 #endif
... ... @@ -633,7 +634,7 @@
633 634 writel(0, MMC_CLKRT); /* 20 MHz */
634 635 resp = mmc_cmd(MMC_CMD_SELECT_CARD, rca, 0, MMC_CMDAT_R1);
635 636  
636   -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
  637 +#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
637 638 if (IF_TYPE_SD == mmc_dev.if_type) {
638 639 resp = mmc_cmd(MMC_CMD_APP_CMD, rca, 0, MMC_CMDAT_R1);
639 640 resp = mmc_cmd(SD_CMD_APP_SET_BUS_WIDTH, 0, 2, MMC_CMDAT_R1);
drivers/mmc/pxa_mmc_gen.c
Diff comments   View file @ abc20ab
... ... @@ -30,12 +30,12 @@
30 30 #include <asm/io.h>
31 31  
32 32 /* PXAMMC Generic default config for various CPUs */
33   -#if defined(CONFIG_PXA250)
  33 +#if defined(CONFIG_CPU_PXA25X)
34 34 #define PXAMMC_FIFO_SIZE 1
35 35 #define PXAMMC_MIN_SPEED 312500
36 36 #define PXAMMC_MAX_SPEED 20000000
37 37 #define PXAMMC_HOST_CAPS (0)
38   -#elif defined(CONFIG_PXA27X)
  38 +#elif defined(CONFIG_CPU_PXA27X)
39 39 #define PXAMMC_CRC_SKIP
40 40 #define PXAMMC_FIFO_SIZE 32
41 41 #define PXAMMC_MIN_SPEED 304000
drivers/net/lan91c96.h
Diff comments   View file @ abc20ab
... ... @@ -68,7 +68,7 @@
68 68  
69 69 #define SMC_IO_EXTENT 16
70 70  
71   -#ifdef CONFIG_PXA250
  71 +#ifdef CONFIG_CPU_PXA25X
72 72  
73 73 #ifdef CONFIG_LUBBOCK
74 74 #define SMC_IO_SHIFT 2
... ... @@ -146,7 +146,7 @@
146 146 }; \
147 147 })
148 148  
149   -#else /* if not CONFIG_PXA250 */
  149 +#else /* if not CONFIG_CPU_PXA25X */
150 150  
151 151 /*
152 152 * We have only 16 Bit PCMCIA access on Socket 0
drivers/net/smc91111.h
Diff comments   View file @ abc20ab
... ... @@ -78,7 +78,7 @@
78 78  
79 79 #define SMC_IO_EXTENT 16
80 80  
81   -#ifdef CONFIG_PXA250
  81 +#ifdef CONFIG_CPU_PXA25X
82 82  
83 83 #ifdef CONFIG_XSENGINE
84 84 #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+((r)<<1))))
... ... @@ -180,7 +180,7 @@
180 180 }; \
181 181 })
182 182  
183   -#elif defined(CONFIG_LEON) /* if not CONFIG_PXA250 */
  183 +#elif defined(CONFIG_LEON) /* if not CONFIG_CPU_PXA25X */
184 184  
185 185 #define SMC_LEON_SWAP16(_x_) ({ word _x = (_x_); ((_x << 8) | (_x >> 8)); })
186 186  
... ... @@ -249,7 +249,7 @@
249 249 }; \
250 250 }while(0)
251 251  
252   -#else /* if not CONFIG_PXA250 and not CONFIG_LEON */
  252 +#else /* if not CONFIG_CPU_PXA25X and not CONFIG_LEON */
253 253  
254 254 #ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */
255 255 /*
drivers/serial/serial_pxa.c
Diff comments   View file @ abc20ab
... ... @@ -49,7 +49,7 @@
49 49 #define BTUART_INDEX 0
50 50 #define FFUART_INDEX 1
51 51 #define STUART_INDEX 2
52   -#elif CONFIG_PXA250
  52 +#elif CONFIG_CPU_PXA25X
53 53 #define UART_CLK_BASE (1 << 4) /* HWUART */
54 54 #define UART_CLK_REG CKEN
55 55 #define HWUART_INDEX 0
... ... @@ -68,7 +68,7 @@
68 68 * Only PXA250 has HWUART, to avoid poluting the code with more macros,
69 69 * artificially introduce this.
70 70 */
71   -#ifndef CONFIG_PXA250
  71 +#ifndef CONFIG_CPU_PXA25X
72 72 #define HWUART_INDEX 0xff
73 73 #endif
74 74  
drivers/serial/usbtty.h
Diff comments   View file @ abc20ab
... ... @@ -31,7 +31,7 @@
31 31 #include <usb/omap1510_udc.h>
32 32 #elif defined(CONFIG_MUSB_UDC)
33 33 #include <usb/musb_udc.h>
34   -#elif defined(CONFIG_PXA27X)
  34 +#elif defined(CONFIG_CPU_PXA27X)
35 35 #include <usb/pxa27x_udc.h>
36 36 #elif defined(CONFIG_SPEAR3XX) || defined(CONFIG_SPEAR600)
37 37 #include <usb/spr_udc.h>
drivers/usb/gadget/Makefile
Diff comments   View file @ abc20ab
... ... @@ -37,7 +37,7 @@
37 37 COBJS-$(CONFIG_OMAP1510) += omap1510_udc.o
38 38 COBJS-$(CONFIG_OMAP1610) += omap1510_udc.o
39 39 COBJS-$(CONFIG_MPC885_FAMILY) += mpc8xx_udc.o
40   -COBJS-$(CONFIG_PXA27X) += pxa27x_udc.o
  40 +COBJS-$(CONFIG_CPU_PXA27X) += pxa27x_udc.o
41 41 COBJS-$(CONFIG_SPEARUDC) += spr_udc.o
42 42 endif
43 43 endif
include/configs/balloon3.h
Diff comments   View file @ abc20ab
... ... @@ -25,7 +25,7 @@
25 25 /*
26 26 * High Level Board Configuration Options
27 27 */
28   -#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */
  28 +#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
29 29 #define CONFIG_BALLOON3 1 /* Balloon3 board */
30 30  
31 31 /*
include/configs/colibri_pxa270.h
Diff comments   View file @ abc20ab
... ... @@ -25,7 +25,7 @@
25 25 /*
26 26 * High Level Board Configuration Options
27 27 */
28   -#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */
  28 +#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
29 29 #define CONFIG_VPAC270 1 /* Toradex Colibri PXA270 board */
30 30  
31 31 #undef CONFIG_BOARD_LATE_INIT
include/configs/lubbock.h
Diff comments   View file @ abc20ab
... ... @@ -34,7 +34,7 @@
34 34 * High Level Configuration Options
35 35 * (easy to change)
36 36 */
37   -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
  37 +#define CONFIG_CPU_PXA25X 1 /* This is an PXA250 CPU */
38 38 #define CONFIG_LUBBOCK 1 /* on an LUBBOCK Board */
39 39 #define CONFIG_LCD 1
40 40 #ifdef CONFIG_LCD
include/configs/palmld.h
Diff comments   View file @ abc20ab
... ... @@ -25,7 +25,7 @@
25 25 /*
26 26 * High Level Board Configuration Options
27 27 */
28   -#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */
  28 +#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
29 29 #define CONFIG_PALMLD 1 /* Palm LifeDrive board */
30 30  
31 31 /*
include/configs/palmtc.h
Diff comments   View file @ abc20ab
... ... @@ -27,7 +27,7 @@
27 27 /*
28 28 * High Level Board Configuration Options
29 29 */
30   -#define CONFIG_PXA250 1 /* Intel PXA255 CPU */
  30 +#define CONFIG_CPU_PXA25X 1 /* Intel PXA255 CPU */
31 31 #define CONFIG_PALMTC 1 /* Palm Tungsten|C board */
32 32  
33 33 /*
include/configs/pxa255_idp.h
Diff comments   View file @ abc20ab
... ... @@ -55,7 +55,7 @@
55 55 * High Level Configuration Options
56 56 * (easy to change)
57 57 */
58   -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
  58 +#define CONFIG_CPU_PXA25X 1 /* This is an PXA250 CPU */
59 59  
60 60 #undef CONFIG_LCD
61 61 #ifdef CONFIG_LCD
include/configs/trizepsiv.h
Diff comments   View file @ abc20ab
... ... @@ -40,7 +40,7 @@
40 40 * High Level Configuration Options
41 41 * (easy to change)
42 42 */
43   -#define CONFIG_PXA27X 1 /* This is an PXA27x CPU */
  43 +#define CONFIG_CPU_PXA27X 1 /* This is an PXA27x CPU */
44 44  
45 45 #define CONFIG_MMC 1
46 46 #define CONFIG_BOARD_LATE_INIT
include/configs/vpac270.h
Diff comments   View file @ abc20ab
... ... @@ -25,7 +25,7 @@
25 25 /*
26 26 * High Level Board Configuration Options
27 27 */
28   -#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */
  28 +#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
29 29 #define CONFIG_VPAC270 1 /* Voipac PXA270 board */
30 30 #define CONFIG_SYS_TEXT_BASE 0xa0000000
31 31  
include/configs/xaeniax.h
Diff comments   View file @ abc20ab
... ... @@ -40,7 +40,7 @@
40 40 * High Level Configuration Options
41 41 * (easy to change)
42 42 */
43   -#define CONFIG_PXA250 1 /* This is an PXA255 CPU */
  43 +#define CONFIG_CPU_PXA25X 1 /* This is an PXA255 CPU */
44 44 #define CONFIG_XAENIAX 1 /* on a xaeniax board */
45 45 #define CONFIG_SYS_TEXT_BASE 0x0
46 46  
include/configs/zipitz2.h
Diff comments   View file @ abc20ab
... ... @@ -25,7 +25,7 @@
25 25 /*
26 26 * High Level Board Configuration Options
27 27 */
28   -#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */
  28 +#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
29 29 #define CONFIG_ZIPITZ2 1 /* Zipit Z2 board */
30 30 #define CONFIG_SYS_TEXT_BASE 0x0
31 31  
... ... @@ -87,7 +87,8 @@
87 87 u_char vl_wbf; /* Wait between frames */
88 88 } vidinfo_t;
89 89  
90   -#elif defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
  90 +#elif defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \
  91 + defined CONFIG_CPU_MONAHANS
91 92 /*
92 93 * PXA LCD DMA descriptor
93 94 */
... ... @@ -195,7 +196,7 @@
195 196 void *priv; /* Pointer to driver-specific data */
196 197 } vidinfo_t;
197 198  
198   -#endif /* CONFIG_MPC823, CONFIG_PXA250 or CONFIG_MCC200 or CONFIG_ATMEL_LCD */
  199 +#endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_MCC200, CONFIG_ATMEL_LCD */
199 200  
200 201 extern vidinfo_t panel_info;
201 202