new PHY @ e1000 - 2nd try

Add 82541ER device with latest integrated IGP2 PHY. Introduced CONFIG_E1000_FALLBACK_MAC for NIC bring-up with empty eeprom. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>

new PHY @ e1000 - 2nd try
Add 82541ER device with latest integrated IGP2 PHY. Introduced CONFIG_E1000_FALLBACK_MAC for NIC bring-up with empty eeprom. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Andre Schwarz · Ben Warren
1 parent c2b7da5522
Showing 4 changed files with 98 additions and 13 deletions Side-by-side Diff
README
drivers/net/e1000.c
drivers/net/e1000.h
include/pci_ids.h
@@ -751,6 +751,9 @@
 		CONFIG_E1000
 		Support for Intel 8254x gigabit chips.
  
+		CONFIG_E1000_FALLBACK_MAC
+		default MAC for empty eeprom after production.
+
 		CONFIG_EEPRO100
 		Support for Intel 82557/82559/82559ER chips.
 		Optional CONFIG_EEPRO100_SROM_WRITE enables eeprom
 /**************************************************************************
-Inter Pro 1000 for ppcboot/das-u-boot
+Intel Pro 1000 for ppcboot/das-u-boot
 Drivers are port from Intel's Linux driver e1000-4.3.15
 and from Etherboot pro 1000 driver by mrakes at vivato dot net
 tested on both gig copper and gig fiber boards
@@ -82,6 +82,7 @@
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
 };
  
 /* Function forward declarations */
@@ -512,6 +513,11 @@
 		/* Invert the last bit if this is the second device */
 		nic->enetaddr[5] += 1;
 	}
+#ifdef CONFIG_E1000_FALLBACK_MAC
+	if ( *(u32*)(nic->enetaddr) == 0 || *(u32*)(nic->enetaddr) == ~0 )
+		for ( i=0; i < NODE_ADDRESS_SIZE; i++ )
+			nic->enetaddr[i] = (CONFIG_E1000_FALLBACK_MAC >> (8*(5-i))) & 0xff;
+#endif
 #else
 	/*
 	 * The AP1000's e1000 has no eeprom; the MAC address is stored in the
@@ -639,6 +645,9 @@
 	case E1000_DEV_ID_82546EB_FIBER:
 		hw->mac_type = e1000_82546;
 		break;
+	case E1000_DEV_ID_82541ER:
+	        hw->mac_type = e1000_82541_rev_2;
+	        break;
 	default:
 		/* Should never have loaded on this device */
 		return -E1000_ERR_MAC_TYPE;
@@ -2485,6 +2494,36 @@
 	return 0;
 }
  
+static int
+e1000_set_phy_type(struct e1000_hw *hw)
+{
+    DEBUGFUNC();
+
+    if(hw->mac_type == e1000_undefined)
+        return -E1000_ERR_PHY_TYPE;
+
+    switch(hw->phy_id) {
+    case M88E1000_E_PHY_ID:
+    case M88E1000_I_PHY_ID:
+    case M88E1011_I_PHY_ID:
+        hw->phy_type = e1000_phy_m88;
+        break;
+    case IGP01E1000_I_PHY_ID:
+        if(hw->mac_type == e1000_82541 ||
+           hw->mac_type == e1000_82541_rev_2) {
+            hw->phy_type = e1000_phy_igp;
+            break;
+        }
+        /* Fall Through */
+    default:
+        /* Should never have loaded on this device */
+        hw->phy_type = e1000_phy_undefined;
+        return -E1000_ERR_PHY_TYPE;
+    }
+
+    return E1000_SUCCESS;
+}
+
 /******************************************************************************
 * Probes the expected PHY address for known PHY IDs
 *
@@ -2493,6 +2532,7 @@
 static int
 e1000_detect_gig_phy(struct e1000_hw *hw)
 {
+	int32_t phy_init_status;
 	uint16_t phy_id_high, phy_id_low;
 	int match = FALSE;
  
  
@@ -2526,11 +2566,19 @@
 		if (hw->phy_id == M88E1011_I_PHY_ID)
 			match = TRUE;
 		break;
+	case e1000_82541_rev_2:
+		if(hw->phy_id == IGP01E1000_I_PHY_ID)
+			match = TRUE;
+
+		break;
 	default:
 		DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
 		return -E1000_ERR_CONFIG;
 	}
-	if (match) {
+
+	phy_init_status = e1000_set_phy_type(hw);
+
+	if ((match) && (phy_init_status == E1000_SUCCESS)) {
 		DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
 		return 0;
 	}
@@ -2985,7 +3033,7 @@
 			free(nic);
 			return 0;
 		}
-#ifndef CONFIG_AP1000
+#if !(defined(CONFIG_AP1000) || defined(CONFIG_MVBC_1G))
 		if (e1000_validate_eeprom_checksum(nic) < 0) {
 			printf("The EEPROM Checksum Is Not Valid\n");
 			free(hw);
@@ -71,6 +71,8 @@
 	e1000_82540,
 	e1000_82545,
 	e1000_82546,
+	e1000_82541,
+	e1000_82541_rev_2,
 	e1000_num_macs
 } e1000_mac_type;
  
@@ -168,6 +170,13 @@
 	e1000_1000t_rx_status_undefined = 0xFF
 } e1000_1000t_rx_status;
  
+typedef enum {
+    e1000_phy_m88 = 0,
+    e1000_phy_igp,
+    e1000_phy_igp_2,
+    e1000_phy_undefined = 0xFF
+} e1000_phy_type;
+
 struct e1000_phy_info {
 	e1000_cable_length cable_length;
 	e1000_10bt_ext_dist_enable extended_10bt_distance;
@@ -184,14 +193,19 @@
 };
  
 /* Error Codes */
-#define E1000_SUCCESS      0
-#define E1000_ERR_EEPROM   1
-#define E1000_ERR_PHY      2
-#define E1000_ERR_CONFIG   3
-#define E1000_ERR_PARAM    4
-#define E1000_ERR_MAC_TYPE 5
-#define E1000_ERR_NOLINK   6
-#define E1000_ERR_TIMEOUT  7
+#define E1000_SUCCESS      			0
+#define E1000_ERR_EEPROM   			1
+#define E1000_ERR_PHY      			2
+#define E1000_ERR_CONFIG   			3
+#define E1000_ERR_PARAM    			4
+#define E1000_ERR_MAC_TYPE 			5
+#define E1000_ERR_PHY_TYPE 			6
+#define E1000_ERR_NOLINK   			7
+#define E1000_ERR_TIMEOUT  			8
+#define E1000_ERR_RESET   			9
+#define E1000_ERR_MASTER_REQUESTS_PENDING 	10
+#define E1000_ERR_HOST_INTERFACE_COMMAND 	11
+#define E1000_BLK_PHY_RESET   			12
  
 /* PCI Device IDs */
 #define E1000_DEV_ID_82542          0x1000
@@ -207,7 +221,8 @@
 #define E1000_DEV_ID_82545EM_FIBER  0x1011
 #define E1000_DEV_ID_82546EB_COPPER 0x1010
 #define E1000_DEV_ID_82546EB_FIBER  0x1012
-#define NUM_DEV_IDS 13
+#define E1000_DEV_ID_82541ER        0x1078
+#define NUM_DEV_IDS 14
  
 #define NODE_ADDRESS_SIZE 6
 #define ETH_LENGTH_OF_ADDRESS 6
@@ -799,6 +814,8 @@
 	pci_dev_t pdev;
 	uint8_t *hw_addr;
 	e1000_mac_type mac_type;
+	e1000_phy_type phy_type;
+	uint32_t phy_init_script;
 	e1000_media_type media_type;
 	e1000_lan_loc lan_loc;
 	e1000_fc_type fc;
  
@@ -1517,8 +1534,23 @@
 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14	/* Extended PHY Specific Control */
 #define M88E1000_RX_ERR_CNTR       0x15	/* Receive Error Counter */
  
-#define MAX_PHY_REG_ADDRESS 0x1F	/* 5 bit address bus (0-0x1F) */
+#define MAX_PHY_REG_ADDRESS 	0x1F	/* 5 bit address bus (0-0x1F) */
  
+/* IGP01E1000 specifics */
+#define IGP01E1000_IEEE_REGS_PAGE  	0x0000
+#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
+#define IGP01E1000_IEEE_FORCE_GIGA      0x0140
+
+/* IGP01E1000 Specific Registers */
+#define IGP01E1000_PHY_PORT_CONFIG 	0x10 /* PHY Specific Port Config Register */
+#define IGP01E1000_PHY_PORT_STATUS 	0x11 /* PHY Specific Status Register */
+#define IGP01E1000_PHY_PORT_CTRL   	0x12 /* PHY Specific Control Register */
+#define IGP01E1000_PHY_LINK_HEALTH 	0x13 /* PHY Link Health Register */
+#define IGP01E1000_GMII_FIFO       	0x14 /* GMII FIFO Register */
+#define IGP01E1000_PHY_CHANNEL_QUALITY 	0x15 /* PHY Channel Quality Register */
+#define IGP02E1000_PHY_POWER_MGMT      	0x19
+#define IGP01E1000_PHY_PAGE_SELECT     	0x1F /* PHY Page Select Core Register */
+
 /* PHY Control Register */
 #define MII_CR_SPEED_SELECT_MSB 0x0040	/* bits 6,13: 10=1000, 01=100, 00=10 */
 #define MII_CR_COLL_TEST_ENABLE 0x0080	/* Collision test enable */
@@ -1729,6 +1761,7 @@
 #define M88E1011_I_PHY_ID  0x01410C20
 #define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
 #define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
+#define IGP01E1000_I_PHY_ID  0x02A80380
  
 /* Miscellaneous PHY bit definitions. */
 #define PHY_PREAMBLE        0xFFFFFFFF
@@ -1810,6 +1810,7 @@
 #define PCI_DEVICE_ID_INTEL_82434	0x04a3
 #define PCI_DEVICE_ID_INTEL_I960	0x0960
 #define PCI_DEVICE_ID_INTEL_I960RM	0x0962
+#define PCI_DEVICE_ID_INTEL_82541ER 0x1078
 #define PCI_DEVICE_ID_INTEL_82542	0x1000
 #define PCI_DEVICE_ID_INTEL_82543GC_FIBER	0x1001
 #define PCI_DEVICE_ID_INTEL_82543GC_COPPER	0x1004
...	...	@@ -751,6 +751,9 @@
751	751	CONFIG_E1000
752	752	Support for Intel 8254x gigabit chips.
753	753
	754	+ CONFIG_E1000_FALLBACK_MAC
	755	+ default MAC for empty eeprom after production.
	756	+
754	757	CONFIG_EEPRO100
755	758	Support for Intel 82557/82559/82559ER chips.
756	759	Optional CONFIG_EEPRO100_SROM_WRITE enables eeprom
1	1	/**************************************************************************
2		-Inter Pro 1000 for ppcboot/das-u-boot
	2	+Intel Pro 1000 for ppcboot/das-u-boot
3	3	Drivers are port from Intel's Linux driver e1000-4.3.15
4	4	and from Etherboot pro 1000 driver by mrakes at vivato dot net
5	5	tested on both gig copper and gig fiber boards
...	...	@@ -82,6 +82,7 @@
82	82	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
83	83	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
84	84	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
	85	+ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
85	86	};
86	87
87	88	/* Function forward declarations */
...	...	@@ -512,6 +513,11 @@
512	513	/* Invert the last bit if this is the second device */
513	514	nic->enetaddr[5] += 1;
514	515	}
	516	+#ifdef CONFIG_E1000_FALLBACK_MAC
	517	+ if ( (u32)(nic->enetaddr) == 0 \|\| (u32)(nic->enetaddr) == ~0 )
	518	+ for ( i=0; i < NODE_ADDRESS_SIZE; i++ )
	519	+ nic->enetaddr[i] = (CONFIG_E1000_FALLBACK_MAC >> (8*(5-i))) & 0xff;
	520	+#endif
515	521	#else
516	522	/*
517	523	* The AP1000's e1000 has no eeprom; the MAC address is stored in the
...	...	@@ -639,6 +645,9 @@
639	645	case E1000_DEV_ID_82546EB_FIBER:
640	646	hw->mac_type = e1000_82546;
641	647	break;
	648	+ case E1000_DEV_ID_82541ER:
	649	+ hw->mac_type = e1000_82541_rev_2;
	650	+ break;
642	651	default:
643	652	/* Should never have loaded on this device */
644	653	return -E1000_ERR_MAC_TYPE;
...	...	@@ -2485,6 +2494,36 @@
2485	2494	return 0;
2486	2495	}
2487	2496
	2497	+static int
	2498	+e1000_set_phy_type(struct e1000_hw *hw)
	2499	+{
	2500	+ DEBUGFUNC();
	2501	+
	2502	+ if(hw->mac_type == e1000_undefined)
	2503	+ return -E1000_ERR_PHY_TYPE;
	2504	+
	2505	+ switch(hw->phy_id) {
	2506	+ case M88E1000_E_PHY_ID:
	2507	+ case M88E1000_I_PHY_ID:
	2508	+ case M88E1011_I_PHY_ID:
	2509	+ hw->phy_type = e1000_phy_m88;
	2510	+ break;
	2511	+ case IGP01E1000_I_PHY_ID:
	2512	+ if(hw->mac_type == e1000_82541 \|\|
	2513	+ hw->mac_type == e1000_82541_rev_2) {
	2514	+ hw->phy_type = e1000_phy_igp;
	2515	+ break;
	2516	+ }
	2517	+ /* Fall Through */
	2518	+ default:
	2519	+ /* Should never have loaded on this device */
	2520	+ hw->phy_type = e1000_phy_undefined;
	2521	+ return -E1000_ERR_PHY_TYPE;
	2522	+ }
	2523	+
	2524	+ return E1000_SUCCESS;
	2525	+}
	2526	+
2488	2527	/******************************************************************************
2489	2528	* Probes the expected PHY address for known PHY IDs
2490	2529	*
...	...	@@ -2493,6 +2532,7 @@
2493	2532	static int
2494	2533	e1000_detect_gig_phy(struct e1000_hw *hw)
2495	2534	{
	2535	+ int32_t phy_init_status;
2496	2536	uint16_t phy_id_high, phy_id_low;
2497	2537	int match = FALSE;
2498	2538
2499	2539
...	...	@@ -2526,11 +2566,19 @@
2526	2566	if (hw->phy_id == M88E1011_I_PHY_ID)
2527	2567	match = TRUE;
2528	2568	break;
	2569	+ case e1000_82541_rev_2:
	2570	+ if(hw->phy_id == IGP01E1000_I_PHY_ID)
	2571	+ match = TRUE;
	2572	+
	2573	+ break;
2529	2574	default:
2530	2575	DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
2531	2576	return -E1000_ERR_CONFIG;
2532	2577	}
2533		- if (match) {
	2578	+
	2579	+ phy_init_status = e1000_set_phy_type(hw);
	2580	+
	2581	+ if ((match) && (phy_init_status == E1000_SUCCESS)) {
2534	2582	DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
2535	2583	return 0;
2536	2584	}
...	...	@@ -2985,7 +3033,7 @@
2985	3033	free(nic);
2986	3034	return 0;
2987	3035	}
2988		-#ifndef CONFIG_AP1000
	3036	+#if !(defined(CONFIG_AP1000) \|\| defined(CONFIG_MVBC_1G))
2989	3037	if (e1000_validate_eeprom_checksum(nic) < 0) {
2990	3038	printf("The EEPROM Checksum Is Not Valid\n");
2991	3039	free(hw);
...	...	@@ -71,6 +71,8 @@
71	71	e1000_82540,
72	72	e1000_82545,
73	73	e1000_82546,
	74	+ e1000_82541,
	75	+ e1000_82541_rev_2,
74	76	e1000_num_macs
75	77	} e1000_mac_type;
76	78
...	...	@@ -168,6 +170,13 @@
168	170	e1000_1000t_rx_status_undefined = 0xFF
169	171	} e1000_1000t_rx_status;
170	172
	173	+typedef enum {
	174	+ e1000_phy_m88 = 0,
	175	+ e1000_phy_igp,
	176	+ e1000_phy_igp_2,
	177	+ e1000_phy_undefined = 0xFF
	178	+} e1000_phy_type;
	179	+
171	180	struct e1000_phy_info {
172	181	e1000_cable_length cable_length;
173	182	e1000_10bt_ext_dist_enable extended_10bt_distance;
...	...	@@ -184,14 +193,19 @@
184	193	};
185	194
186	195	/* Error Codes */
187		-#define E1000_SUCCESS 0
188		-#define E1000_ERR_EEPROM 1
189		-#define E1000_ERR_PHY 2
190		-#define E1000_ERR_CONFIG 3
191		-#define E1000_ERR_PARAM 4
192		-#define E1000_ERR_MAC_TYPE 5
193		-#define E1000_ERR_NOLINK 6
194		-#define E1000_ERR_TIMEOUT 7
	196	+#define E1000_SUCCESS 0
	197	+#define E1000_ERR_EEPROM 1
	198	+#define E1000_ERR_PHY 2
	199	+#define E1000_ERR_CONFIG 3
	200	+#define E1000_ERR_PARAM 4
	201	+#define E1000_ERR_MAC_TYPE 5
	202	+#define E1000_ERR_PHY_TYPE 6
	203	+#define E1000_ERR_NOLINK 7
	204	+#define E1000_ERR_TIMEOUT 8
	205	+#define E1000_ERR_RESET 9
	206	+#define E1000_ERR_MASTER_REQUESTS_PENDING 10
	207	+#define E1000_ERR_HOST_INTERFACE_COMMAND 11
	208	+#define E1000_BLK_PHY_RESET 12
195	209
196	210	/* PCI Device IDs */
197	211	#define E1000_DEV_ID_82542 0x1000
...	...	@@ -207,7 +221,8 @@
207	221	#define E1000_DEV_ID_82545EM_FIBER 0x1011
208	222	#define E1000_DEV_ID_82546EB_COPPER 0x1010
209	223	#define E1000_DEV_ID_82546EB_FIBER 0x1012
210		-#define NUM_DEV_IDS 13
	224	+#define E1000_DEV_ID_82541ER 0x1078
	225	+#define NUM_DEV_IDS 14
211	226
212	227	#define NODE_ADDRESS_SIZE 6
213	228	#define ETH_LENGTH_OF_ADDRESS 6
...	...	@@ -799,6 +814,8 @@
799	814	pci_dev_t pdev;
800	815	uint8_t *hw_addr;
801	816	e1000_mac_type mac_type;
	817	+ e1000_phy_type phy_type;
	818	+ uint32_t phy_init_script;
802	819	e1000_media_type media_type;
803	820	e1000_lan_loc lan_loc;
804	821	e1000_fc_type fc;
805	822
...	...	@@ -1517,8 +1534,23 @@
1517	1534	#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
1518	1535	#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
1519	1536
1520		-#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
	1537	+#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1521	1538
	1539	+/* IGP01E1000 specifics */
	1540	+#define IGP01E1000_IEEE_REGS_PAGE 0x0000
	1541	+#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
	1542	+#define IGP01E1000_IEEE_FORCE_GIGA 0x0140
	1543	+
	1544	+/* IGP01E1000 Specific Registers */
	1545	+#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
	1546	+#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
	1547	+#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */
	1548	+#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
	1549	+#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */
	1550	+#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
	1551	+#define IGP02E1000_PHY_POWER_MGMT 0x19
	1552	+#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
	1553	+
1522	1554	/* PHY Control Register */
1523	1555	#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
1524	1556	#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
...	...	@@ -1729,6 +1761,7 @@
1729	1761	#define M88E1011_I_PHY_ID 0x01410C20
1730	1762	#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
1731	1763	#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
	1764	+#define IGP01E1000_I_PHY_ID 0x02A80380
1732	1765
1733	1766	/* Miscellaneous PHY bit definitions. */
1734	1767	#define PHY_PREAMBLE 0xFFFFFFFF
...	...	@@ -1810,6 +1810,7 @@
1810	1810	#define PCI_DEVICE_ID_INTEL_82434 0x04a3
1811	1811	#define PCI_DEVICE_ID_INTEL_I960 0x0960
1812	1812	#define PCI_DEVICE_ID_INTEL_I960RM 0x0962
	1813	+#define PCI_DEVICE_ID_INTEL_82541ER 0x1078
1813	1814	#define PCI_DEVICE_ID_INTEL_82542 0x1000
1814	1815	#define PCI_DEVICE_ID_INTEL_82543GC_FIBER 0x1001
1815	1816	#define PCI_DEVICE_ID_INTEL_82543GC_COPPER 0x1004