Eric Lee / smarc-uboot

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Commit ac3d121c3577c2c9ac1881086d6d843762d7a29d

Authored by Heiko Stuebner
Committed by Kever Yang
1 parent ab800e5a6f
Exists in smarc_8mq_lf_v2020.04 and in 9 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

rockchip: px30: sync the main px30 dtsi from mainline 

There have been multiple peripherals added to the main px30 dtsi
in the Linux kernel since its addition to u-boot. So to make it easier
to sync board devicetrees, update the core dtsi from Linux.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Showing 1 changed file with 171 additions and 11 deletions Side-by-side Diff

arch/arm/dts/px30.dtsi
Diff comments   View file @ ac3d121
... ... @@ -10,6 +10,7 @@
10 10 #include <dt-bindings/pinctrl/rockchip.h>
11 11 #include <dt-bindings/power/px30-power.h>
12 12 #include <dt-bindings/soc/rockchip,boot-mode.h>
  13 +#include <dt-bindings/thermal/thermal.h>
13 14  
14 15 / {
15 16 compatible = "rockchip,px30";
16 17  
... ... @@ -113,16 +114,11 @@
113 114 compatible = "operating-points-v2";
114 115 opp-shared;
115 116  
116   - opp-408000000 {
117   - opp-hz = /bits/ 64 <408000000>;
118   - opp-microvolt = <950000 950000 1350000>;
119   - clock-latency-ns = <40000>;
120   - opp-suspend;
121   - };
122 117 opp-600000000 {
123 118 opp-hz = /bits/ 64 <600000000>;
124 119 opp-microvolt = <950000 950000 1350000>;
125 120 clock-latency-ns = <40000>;
  121 + opp-suspend;
126 122 };
127 123 opp-816000000 {
128 124 opp-hz = /bits/ 64 <816000000>;
... ... @@ -186,6 +182,55 @@
186 182 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
187 183 };
188 184  
  185 + thermal_zones: thermal-zones {
  186 + soc_thermal: soc-thermal {
  187 + polling-delay-passive = <20>;
  188 + polling-delay = <1000>;
  189 + sustainable-power = <750>;
  190 + thermal-sensors = <&tsadc 0>;
  191 +
  192 + trips {
  193 + threshold: trip-point-0 {
  194 + temperature = <70000>;
  195 + hysteresis = <2000>;
  196 + type = "passive";
  197 + };
  198 +
  199 + target: trip-point-1 {
  200 + temperature = <85000>;
  201 + hysteresis = <2000>;
  202 + type = "passive";
  203 + };
  204 +
  205 + soc_crit: soc-crit {
  206 + temperature = <115000>;
  207 + hysteresis = <2000>;
  208 + type = "critical";
  209 + };
  210 + };
  211 +
  212 + cooling-maps {
  213 + map0 {
  214 + trip = <&target>;
  215 + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  216 + contribution = <4096>;
  217 + };
  218 +
  219 + map1 {
  220 + trip = <&target>;
  221 + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  222 + contribution = <4096>;
  223 + };
  224 + };
  225 + };
  226 +
  227 + gpu_thermal: gpu-thermal {
  228 + polling-delay-passive = <100>; /* milliseconds */
  229 + polling-delay = <1000>; /* milliseconds */
  230 + thermal-sensors = <&tsadc 1>;
  231 + };
  232 + };
  233 +
189 234 xin24m: xin24m {
190 235 compatible = "fixed-clock";
191 236 #clock-cells = <0>;
... ... @@ -370,6 +415,36 @@
370 415 compatible = "rockchip,px30-io-voltage-domain";
371 416 status = "disabled";
372 417 };
  418 +
  419 + lvds: lvds {
  420 + compatible = "rockchip,px30-lvds";
  421 + phys = <&dsi_dphy>;
  422 + phy-names = "dphy";
  423 + rockchip,grf = <&grf>;
  424 + rockchip,output = "lvds";
  425 + status = "disabled";
  426 +
  427 + ports {
  428 + #address-cells = <1>;
  429 + #size-cells = <0>;
  430 +
  431 + port@0 {
  432 + reg = <0>;
  433 + #address-cells = <1>;
  434 + #size-cells = <0>;
  435 +
  436 + lvds_vopb_in: endpoint@0 {
  437 + reg = <0>;
  438 + remote-endpoint = <&vopb_out_lvds>;
  439 + };
  440 +
  441 + lvds_vopl_in: endpoint@1 {
  442 + reg = <1>;
  443 + remote-endpoint = <&vopl_out_lvds>;
  444 + };
  445 + };
  446 + };
  447 + };
373 448 };
374 449  
375 450 uart1: serial@ff158000 {
... ... @@ -650,6 +725,26 @@
650 725 };
651 726 };
652 727  
  728 + tsadc: tsadc@ff280000 {
  729 + compatible = "rockchip,px30-tsadc";
  730 + reg = <0x0 0xff280000 0x0 0x100>;
  731 + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
  732 + assigned-clocks = <&cru SCLK_TSADC>;
  733 + assigned-clock-rates = <50000>;
  734 + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
  735 + clock-names = "tsadc", "apb_pclk";
  736 + resets = <&cru SRST_TSADC>;
  737 + reset-names = "tsadc-apb";
  738 + rockchip,grf = <&grf>;
  739 + rockchip,hw-tshut-temp = <120000>;
  740 + pinctrl-names = "init", "default", "sleep";
  741 + pinctrl-0 = <&tsadc_otp_gpio>;
  742 + pinctrl-1 = <&tsadc_otp_out>;
  743 + pinctrl-2 = <&tsadc_otp_gpio>;
  744 + #thermal-sensor-cells = <1>;
  745 + status = "disabled";
  746 + };
  747 +
653 748 saradc: saradc@ff288000 {
654 749 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
655 750 reg = <0x0 0xff288000 0x0 0x100>;
656 751  
... ... @@ -706,12 +801,48 @@
706 801 #reset-cells = <1>;
707 802 };
708 803  
  804 + usb2phy_grf: syscon@ff2c0000 {
  805 + compatible = "rockchip,px30-usb2phy-grf", "syscon",
  806 + "simple-mfd";
  807 + reg = <0x0 0xff2c0000 0x0 0x10000>;
  808 + #address-cells = <1>;
  809 + #size-cells = <1>;
  810 +
  811 + u2phy: usb2-phy@100 {
  812 + compatible = "rockchip,px30-usb2phy";
  813 + reg = <0x100 0x20>;
  814 + clocks = <&pmucru SCLK_USBPHY_REF>;
  815 + clock-names = "phyclk";
  816 + #clock-cells = <0>;
  817 + assigned-clocks = <&cru USB480M>;
  818 + assigned-clock-parents = <&u2phy>;
  819 + clock-output-names = "usb480m_phy";
  820 + status = "disabled";
  821 +
  822 + u2phy_host: host-port {
  823 + #phy-cells = <0>;
  824 + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
  825 + interrupt-names = "linestate";
  826 + status = "disabled";
  827 + };
  828 +
  829 + u2phy_otg: otg-port {
  830 + #phy-cells = <0>;
  831 + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
  832 + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
  833 + <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
  834 + interrupt-names = "otg-bvalid", "otg-id",
  835 + "linestate";
  836 + status = "disabled";
  837 + };
  838 + };
  839 + };
  840 +
709 841 dsi_dphy: phy@ff2e0000 {
710 842 compatible = "rockchip,px30-dsi-dphy";
711 843 reg = <0x0 0xff2e0000 0x0 0x10000>;
712 844 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
713 845 clock-names = "ref", "pclk";
714   - #clock-cells = <0>;
715 846 resets = <&cru SRST_MIPIDSIPHY_P>;
716 847 reset-names = "apb";
717 848 #phy-cells = <0>;
... ... @@ -731,6 +862,8 @@
731 862 g-rx-fifo-size = <280>;
732 863 g-tx-fifo-size = <256 128 128 64 32 16>;
733 864 g-use-dma;
  865 + phys = <&u2phy_otg>;
  866 + phy-names = "usb2-phy";
734 867 power-domains = <&power PX30_PD_USB>;
735 868 status = "disabled";
736 869 };
... ... @@ -741,6 +874,8 @@
741 874 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
742 875 clocks = <&cru HCLK_HOST>;
743 876 clock-names = "usbhost";
  877 + phys = <&u2phy_host>;
  878 + phy-names = "usb";
744 879 power-domains = <&power PX30_PD_USB>;
745 880 status = "disabled";
746 881 };
... ... @@ -751,6 +886,8 @@
751 886 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
752 887 clocks = <&cru HCLK_HOST>;
753 888 clock-names = "usbhost";
  889 + phys = <&u2phy_host>;
  890 + phy-names = "usb";
754 891 power-domains = <&power PX30_PD_USB>;
755 892 status = "disabled";
756 893 };
757 894  
758 895  
... ... @@ -823,17 +960,30 @@
823 960 status = "disabled";
824 961 };
825 962  
  963 + gpu: gpu@ff400000 {
  964 + compatible = "rockchip,px30-mali", "arm,mali-bifrost";
  965 + reg = <0x0 0xff400000 0x0 0x4000>;
  966 + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
  967 + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
  968 + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
  969 + interrupt-names = "job", "mmu", "gpu";
  970 + clocks = <&cru SCLK_GPU>;
  971 + #cooling-cells = <2>;
  972 + power-domains = <&power PX30_PD_GPU>;
  973 + status = "disabled";
  974 + };
  975 +
826 976 dsi: dsi@ff450000 {
827 977 compatible = "rockchip,px30-mipi-dsi";
828 978 reg = <0x0 0xff450000 0x0 0x10000>;
829 979 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
830   - clocks = <&cru PCLK_MIPI_DSI>, <&dsi_dphy>;
831   - clock-names = "pclk", "pll";
832   - resets = <&cru SRST_MIPIDSI_HOST_P>;
833   - reset-names = "apb";
  980 + clocks = <&cru PCLK_MIPI_DSI>;
  981 + clock-names = "pclk";
834 982 phys = <&dsi_dphy>;
835 983 phy-names = "dphy";
836 984 power-domains = <&power PX30_PD_VO>;
  985 + resets = <&cru SRST_MIPIDSI_HOST_P>;
  986 + reset-names = "apb";
837 987 rockchip,grf = <&grf>;
838 988 #address-cells = <1>;
839 989 #size-cells = <0>;
... ... @@ -883,6 +1033,11 @@
883 1033 reg = <0>;
884 1034 remote-endpoint = <&dsi_in_vopb>;
885 1035 };
  1036 +
  1037 + vopb_out_lvds: endpoint@1 {
  1038 + reg = <1>;
  1039 + remote-endpoint = <&lvds_vopb_in>;
  1040 + };
886 1041 };
887 1042 };
888 1043  
... ... @@ -919,6 +1074,11 @@
919 1074 vopl_out_dsi: endpoint@0 {
920 1075 reg = <0>;
921 1076 remote-endpoint = <&dsi_in_vopl>;
  1077 + };
  1078 +
  1079 + vopl_out_lvds: endpoint@1 {
  1080 + reg = <1>;
  1081 + remote-endpoint = <&lvds_vopl_in>;
922 1082 };
923 1083 };
924 1084 };