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Commit acb90e8338734004aed6e0cb47585c96611ce9c9

Authored by Hou Zhiqiang
Committed by York Sun
1 parent 06651b9456
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

fsl-lsch2: csu: correct the workaround A-010315 

The implementation of function set_pcie_ns_access() uses a wrong
argument. The structure array ns_dev has a member 'ind' which is
initialized by CSU_CSLX_*. It should use the 'ind' directly to
address the PCIe's CSL register (CSL_base + CSU_CSLX_PCIE*).

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[YS: Revise commit message]
Reviewed-by: York Sun <york.sun@nxp.com>

Showing 2 changed files with 11 additions and 11 deletions Inline Diff

board/freescale/common/ns_access.c
Diff comments   View file @ acb90e8
1 /* 1 /*
2 * Copyright 2014 Freescale Semiconductor 2 * Copyright 2014 Freescale Semiconductor
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <common.h> 7 #include <common.h>
8 #include <asm/io.h> 8 #include <asm/io.h>
9 #include <fsl_csu.h> 9 #include <fsl_csu.h>
10 #include <asm/arch/ns_access.h> 10 #include <asm/arch/ns_access.h>
11 #include <asm/arch/fsl_serdes.h> 11 #include <asm/arch/fsl_serdes.h>
12 12
13 void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val) 13 void set_devices_ns_access(unsigned long index, u16 val)
14 { 14 {
15 u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR; 15 u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
16 u32 *reg; 16 u32 *reg;
17 uint32_t tmp; 17 uint32_t tmp;
18 18
19 reg = base + ns_dev->ind / 2; 19 reg = base + index / 2;
20 tmp = in_be32(reg); 20 tmp = in_be32(reg);
21 if (ns_dev->ind % 2 == 0) { 21 if (index % 2 == 0) {
22 tmp &= 0x0000ffff; 22 tmp &= 0x0000ffff;
23 tmp |= val << 16; 23 tmp |= val << 16;
24 } else { 24 } else {
25 tmp &= 0xffff0000; 25 tmp &= 0xffff0000;
26 tmp |= val; 26 tmp |= val;
27 } 27 }
28 28
29 out_be32(reg, tmp); 29 out_be32(reg, tmp);
30 } 30 }
31 31
32 static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num) 32 static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
33 { 33 {
34 int i; 34 int i;
35 35
36 for (i = 0; i < num; i++) 36 for (i = 0; i < num; i++)
37 set_devices_ns_access(ns_dev + i, ns_dev[i].val); 37 set_devices_ns_access(ns_dev[i].ind, ns_dev[i].val);
38 } 38 }
39 39
40 void enable_layerscape_ns_access(void) 40 void enable_layerscape_ns_access(void)
41 { 41 {
42 #ifdef CONFIG_ARM64 42 #ifdef CONFIG_ARM64
43 if (current_el() == 3) 43 if (current_el() == 3)
44 #endif 44 #endif
45 enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); 45 enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
46 } 46 }
47 47
48 void set_pcie_ns_access(int pcie, u16 val) 48 void set_pcie_ns_access(int pcie, u16 val)
49 { 49 {
50 switch (pcie) { 50 switch (pcie) {
51 #ifdef CONFIG_PCIE1 51 #ifdef CONFIG_PCIE1
52 case PCIE1: 52 case PCIE1:
53 set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1], val); 53 set_devices_ns_access(CSU_CSLX_PCIE1, val);
54 set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1_IO], val); 54 set_devices_ns_access(CSU_CSLX_PCIE1_IO, val);
55 return; 55 return;
56 #endif 56 #endif
57 #ifdef CONFIG_PCIE2 57 #ifdef CONFIG_PCIE2
58 case PCIE2: 58 case PCIE2:
59 set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2], val); 59 set_devices_ns_access(CSU_CSLX_PCIE2, val);
60 set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2_IO], val); 60 set_devices_ns_access(CSU_CSLX_PCIE2_IO, val);
61 return; 61 return;
62 #endif 62 #endif
63 #ifdef CONFIG_PCIE3 63 #ifdef CONFIG_PCIE3
64 case PCIE3: 64 case PCIE3:
65 set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3], val); 65 set_devices_ns_access(CSU_CSLX_PCIE3, val);
66 set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3_IO], val); 66 set_devices_ns_access(CSU_CSLX_PCIE3_IO, val);
67 return; 67 return;
68 #endif 68 #endif
69 default: 69 default:
70 debug("The PCIE%d doesn't exist!\n", pcie); 70 debug("The PCIE%d doesn't exist!\n", pcie);
71 return; 71 return;
72 } 72 }
73 } 73 }
74 74
1 /* 1 /*
2 * Copyright 2015 Freescale Semiconductor 2 * Copyright 2015 Freescale Semiconductor
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 * 5 *
6 */ 6 */
7 7
8 #ifndef __FSL_CSU_H__ 8 #ifndef __FSL_CSU_H__
9 #define __FSL_CSU_H__ 9 #define __FSL_CSU_H__
10 10
11 enum csu_cslx_access { 11 enum csu_cslx_access {
12 CSU_NS_SUP_R = 0x08, 12 CSU_NS_SUP_R = 0x08,
13 CSU_NS_SUP_W = 0x80, 13 CSU_NS_SUP_W = 0x80,
14 CSU_NS_SUP_RW = 0x88, 14 CSU_NS_SUP_RW = 0x88,
15 CSU_NS_USER_R = 0x04, 15 CSU_NS_USER_R = 0x04,
16 CSU_NS_USER_W = 0x40, 16 CSU_NS_USER_W = 0x40,
17 CSU_NS_USER_RW = 0x44, 17 CSU_NS_USER_RW = 0x44,
18 CSU_S_SUP_R = 0x02, 18 CSU_S_SUP_R = 0x02,
19 CSU_S_SUP_W = 0x20, 19 CSU_S_SUP_W = 0x20,
20 CSU_S_SUP_RW = 0x22, 20 CSU_S_SUP_RW = 0x22,
21 CSU_S_USER_R = 0x01, 21 CSU_S_USER_R = 0x01,
22 CSU_S_USER_W = 0x10, 22 CSU_S_USER_W = 0x10,
23 CSU_S_USER_RW = 0x11, 23 CSU_S_USER_RW = 0x11,
24 CSU_ALL_RW = 0xff, 24 CSU_ALL_RW = 0xff,
25 }; 25 };
26 26
27 struct csu_ns_dev { 27 struct csu_ns_dev {
28 unsigned long ind; 28 unsigned long ind;
29 uint32_t val; 29 uint32_t val;
30 }; 30 };
31 31
32 void enable_layerscape_ns_access(void); 32 void enable_layerscape_ns_access(void);
33 void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val); 33 void set_devices_ns_access(unsigned long, u16 val);
34 void set_pcie_ns_access(int pcie, u16 val); 34 void set_pcie_ns_access(int pcie, u16 val);
35 35
36 #endif 36 #endif
37 37