Eric Lee / smarc-uboot

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Commit acb90e8338734004aed6e0cb47585c96611ce9c9

Authored by Hou Zhiqiang
Committed by York Sun
1 parent 06651b9456
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

fsl-lsch2: csu: correct the workaround A-010315 

The implementation of function set_pcie_ns_access() uses a wrong
argument. The structure array ns_dev has a member 'ind' which is
initialized by CSU_CSLX_*. It should use the 'ind' directly to
address the PCIe's CSL register (CSL_base + CSU_CSLX_PCIE*).

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[YS: Revise commit message]
Reviewed-by: York Sun <york.sun@nxp.com>

Showing 2 changed files with 11 additions and 11 deletions Side-by-side Diff

board/freescale/common/ns_access.c
Diff comments   View file @ acb90e8
... ... @@ -10,15 +10,15 @@
10 10 #include <asm/arch/ns_access.h>
11 11 #include <asm/arch/fsl_serdes.h>
12 12  
13   -void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val)
  13 +void set_devices_ns_access(unsigned long index, u16 val)
14 14 {
15 15 u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
16 16 u32 *reg;
17 17 uint32_t tmp;
18 18  
19   - reg = base + ns_dev->ind / 2;
  19 + reg = base + index / 2;
20 20 tmp = in_be32(reg);
21   - if (ns_dev->ind % 2 == 0) {
  21 + if (index % 2 == 0) {
22 22 tmp &= 0x0000ffff;
23 23 tmp |= val << 16;
24 24 } else {
... ... @@ -34,7 +34,7 @@
34 34 int i;
35 35  
36 36 for (i = 0; i < num; i++)
37   - set_devices_ns_access(ns_dev + i, ns_dev[i].val);
  37 + set_devices_ns_access(ns_dev[i].ind, ns_dev[i].val);
38 38 }
39 39  
40 40 void enable_layerscape_ns_access(void)
41 41  
42 42  
... ... @@ -50,20 +50,20 @@
50 50 switch (pcie) {
51 51 #ifdef CONFIG_PCIE1
52 52 case PCIE1:
53   - set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1], val);
54   - set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1_IO], val);
  53 + set_devices_ns_access(CSU_CSLX_PCIE1, val);
  54 + set_devices_ns_access(CSU_CSLX_PCIE1_IO, val);
55 55 return;
56 56 #endif
57 57 #ifdef CONFIG_PCIE2
58 58 case PCIE2:
59   - set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2], val);
60   - set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2_IO], val);
  59 + set_devices_ns_access(CSU_CSLX_PCIE2, val);
  60 + set_devices_ns_access(CSU_CSLX_PCIE2_IO, val);
61 61 return;
62 62 #endif
63 63 #ifdef CONFIG_PCIE3
64 64 case PCIE3:
65   - set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3], val);
66   - set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3_IO], val);
  65 + set_devices_ns_access(CSU_CSLX_PCIE3, val);
  66 + set_devices_ns_access(CSU_CSLX_PCIE3_IO, val);
67 67 return;
68 68 #endif
69 69 default:
... ... @@ -30,7 +30,7 @@
30 30 };
31 31  
32 32 void enable_layerscape_ns_access(void);
33   -void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val);
  33 +void set_devices_ns_access(unsigned long, u16 val);
34 34 void set_pcie_ns_access(int pcie, u16 val);
35 35  
36 36 #endif