Eric Lee / smarc-uboot

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Commit acbda20bc8466f9262dfacccf43c39495fd467e1

Authored by Peng Fan
Committed by guoyin.chen
1 parent 99859095c1
Exists in smarc-imx_v2015.04_4.1.15_1.0.0_ga and in 1 other branch imx_v2015.04_4.1.15_1.0.0_ga

MLK-12346 imx: mx7d: switch to use DRAM_PLL, but not DRAM_ALT_CLK_ROOT 

To simplify kernel clock management, we switch to use DRAM_PLL for
DRAM controller and DDR PHY, but not use DRAM_ALT_CLK_ROOT.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

Showing 6 changed files with 79 additions and 24 deletions Side-by-side Diff

board/freescale/mx7d_12x12_ddr3_arm2/imximage.cfg
Diff comments   View file @ acbda20
... ... @@ -48,8 +48,11 @@
48 48 * value value to be stored in the register
49 49 */
50 50  
51   -DATA 4 0x3038a080 0x15000000
52   -DATA 4 0x30389880 0x01000000
  51 +DATA 4 0x30360070 0x00703021
  52 +DATA 4 0x30360090 0x0
  53 +DATA 4 0x30360070 0x00603021
  54 +CHECK_BITS_SET 4 0x30360070 0x80000000
  55 +DATA 4 0x30389880 0x1
53 56  
54 57 DATA 4 0x30340004 0x4F400005
55 58  
board/freescale/mx7d_12x12_ddr3_arm2/plugin.S
Diff comments   View file @ acbda20
... ... @@ -45,13 +45,28 @@
45 45 bne FREQ_DEFAULT_533
46 46  
47 47 /* Change to 400Mhz for TO1.1 */
  48 + ldr r0, =ANATOP_BASE_ADDR
  49 + ldr r1, =0x70
  50 + ldr r2, =0x00703021
  51 + str r2, [r0, r1]
  52 + ldr r1, =0x90
  53 + ldr r2, =0x0
  54 + str r2, [r0, r1]
  55 + ldr r1, =0x70
  56 + ldr r2, =0x00603021
  57 + str r2, [r0, r1]
  58 +
  59 + ldr r3, =0x80000000
  60 +wait_lock:
  61 + ldr r2, [r0, r1]
  62 + and r2, r3
  63 + cmp r2, r3
  64 + bne wait_lock
  65 +
48 66 ldr r0, =CCM_BASE_ADDR
49   - ldr r1, =0x15000000
50   - ldr r2, =0xa080
51   - str r1, [r0, r2]
52   - ldr r1, =0x01000000
53   - ldr r2, =0x9880
54   - str r1, [r0, r2]
  67 + ldr r1, =0x9880
  68 + ldr r2, =0x1
  69 + str r2, [r0, r1]
55 70  
56 71 FREQ_DEFAULT_533:
57 72 .endm
board/freescale/mx7d_19x19_ddr3_arm2/imximage.cfg
Diff comments   View file @ acbda20
... ... @@ -49,8 +49,12 @@
49 49 * Address absolute address of the register
50 50 * value value to be stored in the register
51 51 */
52   -DATA 4 0x3038a080 0x15000000
53   -DATA 4 0x30389880 0x01000000
  52 +
  53 +DATA 4 0x30360070 0x00703021
  54 +DATA 4 0x30360090 0x0
  55 +DATA 4 0x30360070 0x00603021
  56 +CHECK_BITS_SET 4 0x30360070 0x80000000
  57 +DATA 4 0x30389880 0x1
54 58  
55 59 DATA 4 0x30340004 0x4F400005
56 60  
board/freescale/mx7d_19x19_ddr3_arm2/plugin.S
Diff comments   View file @ acbda20
... ... @@ -45,13 +45,28 @@
45 45 bne FREQ_DEFAULT_533
46 46  
47 47 /* Change to 400Mhz for TO1.1 */
  48 + ldr r0, =ANATOP_BASE_ADDR
  49 + ldr r1, =0x70
  50 + ldr r2, =0x00703021
  51 + str r2, [r0, r1]
  52 + ldr r1, =0x90
  53 + ldr r2, =0x0
  54 + str r2, [r0, r1]
  55 + ldr r1, =0x70
  56 + ldr r2, =0x00603021
  57 + str r2, [r0, r1]
  58 +
  59 + ldr r3, =0x80000000
  60 +wait_lock:
  61 + ldr r2, [r0, r1]
  62 + and r2, r3
  63 + cmp r2, r3
  64 + bne wait_lock
  65 +
48 66 ldr r0, =CCM_BASE_ADDR
49   - ldr r1, =0x15000000
50   - ldr r2, =0xa080
51   - str r1, [r0, r2]
52   - ldr r1, =0x01000000
53   - ldr r2, =0x9880
54   - str r1, [r0, r2]
  67 + ldr r1, =0x9880
  68 + ldr r2, =0x1
  69 + str r2, [r0, r1]
55 70  
56 71 FREQ_DEFAULT_533:
57 72 .endm
board/freescale/mx7dsabresd/imximage.cfg
Diff comments   View file @ acbda20
... ... @@ -50,8 +50,11 @@
50 50 * value value to be stored in the register
51 51 */
52 52  
53   -DATA 4 0x3038a080 0x15000000
54   -DATA 4 0x30389880 0x01000000
  53 +DATA 4 0x30360070 0x00703021
  54 +DATA 4 0x30360090 0x0
  55 +DATA 4 0x30360070 0x00603021
  56 +CHECK_BITS_SET 4 0x30360070 0x80000000
  57 +DATA 4 0x30389880 0x1
55 58  
56 59 DATA 4 0x30340004 0x4F400005
57 60  
board/freescale/mx7dsabresd/plugin.S
Diff comments   View file @ acbda20
... ... @@ -45,13 +45,28 @@
45 45 bne FREQ_DEFAULT_533
46 46  
47 47 /* Change to 400Mhz for TO1.1 */
  48 + ldr r0, =ANATOP_BASE_ADDR
  49 + ldr r1, =0x70
  50 + ldr r2, =0x00703021
  51 + str r2, [r0, r1]
  52 + ldr r1, =0x90
  53 + ldr r2, =0x0
  54 + str r2, [r0, r1]
  55 + ldr r1, =0x70
  56 + ldr r2, =0x00603021
  57 + str r2, [r0, r1]
  58 +
  59 + ldr r3, =0x80000000
  60 +wait_lock:
  61 + ldr r2, [r0, r1]
  62 + and r2, r3
  63 + cmp r2, r3
  64 + bne wait_lock
  65 +
48 66 ldr r0, =CCM_BASE_ADDR
49   - ldr r1, =0x15000000
50   - ldr r2, =0xa080
51   - str r1, [r0, r2]
52   - ldr r1, =0x01000000
53   - ldr r2, =0x9880
54   - str r1, [r0, r2]
  67 + ldr r1, =0x9880
  68 + ldr r2, =0x1
  69 + str r2, [r0, r1]
55 70  
56 71 FREQ_DEFAULT_533:
57 72 .endm