Commit add63f94a9c3bbe1af3fdf3f4c56a5185a4c0504
Committed by
York Sun
York Sun
1 parent
068789773d
Exists in
smarc_8mq_lf_v2020.04
and in
22 other branches
arch: powerpc: update the eLBC IP input clock
eLBC IP clock is always a constant divisor of platform clock pre-defined per SoC. Clock ratio register (LCRR) used in current implementation governs eLBC IP output cloc. Update sys_info->freq_localbus to represent eLBC input clock with value constant divisor of platform clock. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Showing 4 changed files with 24 additions and 40 deletions Side-by-side Diff
README
| ... | ... | @@ -507,6 +507,9 @@ |
| 507 | 507 | CONFIG_SYS_FSL_IFC_CLK_DIV |
| 508 | 508 | Defines divider of platform clock(clock input to IFC controller). |
| 509 | 509 | |
| 510 | + CONFIG_SYS_FSL_LBC_CLK_DIV | |
| 511 | + Defines divider of platform clock(clock input to eLBC controller). | |
| 512 | + | |
| 510 | 513 | CONFIG_SYS_FSL_PBL_PBI |
| 511 | 514 | It enables addition of RCW (Power on reset configuration) in built image. |
| 512 | 515 | Please refer doc/README.pblimage for more details |
arch/powerpc/cpu/mpc85xx/Kconfig
| ... | ... | @@ -1337,6 +1337,24 @@ |
| 1337 | 1337 | Defines divider of platform clock(clock input to |
| 1338 | 1338 | IFC controller). |
| 1339 | 1339 | |
| 1340 | +config SYS_FSL_LBC_CLK_DIV | |
| 1341 | + int "Divider of platform clock" | |
| 1342 | + depends on FSL_ELBC || ARCH_MPC8540 || \ | |
| 1343 | + ARCH_MPC8548 || ARCH_MPC8541 || \ | |
| 1344 | + ARCH_MPC8555 || ARCH_MPC8560 || \ | |
| 1345 | + ARCH_MPC8568 | |
| 1346 | + | |
| 1347 | + default 2 if ARCH_P2041 || \ | |
| 1348 | + ARCH_P3041 || \ | |
| 1349 | + ARCH_P4080 || \ | |
| 1350 | + ARCH_P5020 || \ | |
| 1351 | + ARCH_P5040 | |
| 1352 | + default 1 | |
| 1353 | + | |
| 1354 | + help | |
| 1355 | + Defines divider of platform clock(clock input to | |
| 1356 | + eLBC controller). | |
| 1357 | + | |
| 1340 | 1358 | source "board/freescale/b4860qds/Kconfig" |
| 1341 | 1359 | source "board/freescale/bsc9131rdb/Kconfig" |
| 1342 | 1360 | source "board/freescale/bsc9132qds/Kconfig" |
arch/powerpc/cpu/mpc85xx/speed.c
| ... | ... | @@ -607,32 +607,8 @@ |
| 607 | 607 | #endif /* CONFIG_FSL_CORENET */ |
| 608 | 608 | |
| 609 | 609 | #if defined(CONFIG_FSL_LBC) |
| 610 | - uint lcrr_div; | |
| 611 | -#if defined(CONFIG_SYS_LBC_LCRR) | |
| 612 | - /* We will program LCRR to this value later */ | |
| 613 | - lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; | |
| 614 | -#else | |
| 615 | - lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV; | |
| 616 | -#endif | |
| 617 | - if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { | |
| 618 | -#if defined(CONFIG_FSL_CORENET) | |
| 619 | - /* If this is corenet based SoC, bit-representation | |
| 620 | - * for four times the clock divider values. | |
| 621 | - */ | |
| 622 | - lcrr_div *= 4; | |
| 623 | -#elif !defined(CONFIG_ARCH_MPC8540) && !defined(CONFIG_ARCH_MPC8541) && \ | |
| 624 | - !defined(CONFIG_ARCH_MPC8555) && !defined(CONFIG_ARCH_MPC8560) | |
| 625 | - /* | |
| 626 | - * Yes, the entire PQ38 family use the same | |
| 627 | - * bit-representation for twice the clock divider values. | |
| 628 | - */ | |
| 629 | - lcrr_div *= 2; | |
| 630 | -#endif | |
| 631 | - sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div; | |
| 632 | - } else { | |
| 633 | - /* In case anyone cares what the unknown value is */ | |
| 634 | - sys_info->freq_localbus = lcrr_div; | |
| 635 | - } | |
| 610 | + sys_info->freq_localbus = sys_info->freq_systembus / | |
| 611 | + CONFIG_SYS_FSL_LBC_CLK_DIV; | |
| 636 | 612 | #endif |
| 637 | 613 | |
| 638 | 614 | #if defined(CONFIG_FSL_IFC) |
arch/powerpc/cpu/mpc86xx/speed.c
| ... | ... | @@ -24,7 +24,6 @@ |
| 24 | 24 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
| 25 | 25 | volatile ccsr_gur_t *gur = &immap->im_gur; |
| 26 | 26 | uint plat_ratio, e600_ratio; |
| 27 | - uint lcrr_div; | |
| 28 | 27 | |
| 29 | 28 | plat_ratio = (gur->porpllsr) & 0x0000003e; |
| 30 | 29 | plat_ratio >>= 1; |
| ... | ... | @@ -78,19 +77,7 @@ |
| 78 | 77 | break; |
| 79 | 78 | } |
| 80 | 79 | |
| 81 | -#if defined(CONFIG_SYS_LBC_LCRR) | |
| 82 | - /* We will program LCRR to this value later */ | |
| 83 | - lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV; | |
| 84 | -#else | |
| 85 | - lcrr_div = in_be32(&immap->im_lbc.lcrr) & LCRR_CLKDIV; | |
| 86 | -#endif | |
| 87 | - if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) { | |
| 88 | - sys_info->freq_localbus = sys_info->freq_systembus | |
| 89 | - / (lcrr_div * 2); | |
| 90 | - } else { | |
| 91 | - /* In case anyone cares what the unknown value is */ | |
| 92 | - sys_info->freq_localbus = lcrr_div; | |
| 93 | - } | |
| 80 | + sys_info->freq_localbus = sys_info->freq_systembus; | |
| 94 | 81 | } |
| 95 | 82 | |
| 96 | 83 |