x86: crownbay: Add SPI flash support

The Crown Bay board has an SST25VF016B flash connected to the Tunnel Creek processor SPI controller used as the BIOS media where U-Boot is stored. Enable this flash support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>

x86: crownbay: Add SPI flash support
The Crown Bay board has an SST25VF016B flash connected to the Tunnel Creek processor SPI controller used as the BIOS media where U-Boot is stored. Enable this flash support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng · Simon Glass
1 parent 63faf2507d
Showing 3 changed files with 42 additions and 1 deletions Side-by-side Diff
arch/x86/cpu/queensbay/tnc.c
arch/x86/include/asm/arch-queensbay/tnc.h
include/configs/crownbay.h
@@ -6,18 +6,42 @@
  
 #include <common.h>
 #include <asm/io.h>
+#include <asm/pci.h>
 #include <asm/post.h>
+#include <asm/arch/tnc.h>
 #include <asm/arch/fsp/fsp_support.h>
 #include <asm/processor.h>
  
+static void unprotect_spi_flash(void)
+{
+	u32 bc;
+
+	bc = pci_read_config32(PCH_LPC_DEV, 0xd8);
+	bc |= 0x1;	/* unprotect the flash */
+	pci_write_config32(PCH_LPC_DEV, 0xd8, bc);
+}
+
 int arch_cpu_init(void)
 {
+	struct pci_controller *hose;
+	int ret;
+
 	post_code(POST_CPU_INIT);
 #ifdef CONFIG_SYS_X86_TSC_TIMER
 	timer_set_base(rdtsc());
 #endif
  
-	return x86_cpu_init_f();
+	ret = x86_cpu_init_f();
+	if (ret)
+		return ret;
+
+	ret = pci_early_init_hose(&hose);
+	if (ret)
+		return ret;
+
+	unprotect_spi_flash();
+
+	return 0;
 }
  
 int print_cpuinfo(void)
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _X86_ARCH_TNC_H_
+#define _X86_ARCH_TNC_H_
+
+#include <pci.h>
+
+/* PCI Configuration Space (D31:F0): LPC */
+#define PCH_LPC_DEV	PCI_BDF(0, 0x1f, 0)
+
+#endif /* _X86_ARCH_TNC_H_ */
@@ -45,6 +45,8 @@
 #define CONFIG_SCSI_DEV_LIST            \
 	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA}
  
+#define CONFIG_SPI_FLASH_SST
+
 /* Video is not supported */
 #undef CONFIG_VIDEO
 #undef CONFIG_CFB_CONSOLE
...	...	@@ -6,18 +6,42 @@
6	6
7	7	#include <common.h>
8	8	#include <asm/io.h>
	9	+#include <asm/pci.h>
9	10	#include <asm/post.h>
	11	+#include <asm/arch/tnc.h>
10	12	#include <asm/arch/fsp/fsp_support.h>
11	13	#include <asm/processor.h>
12	14
	15	+static void unprotect_spi_flash(void)
	16	+{
	17	+ u32 bc;
	18	+
	19	+ bc = pci_read_config32(PCH_LPC_DEV, 0xd8);
	20	+ bc \|= 0x1; /* unprotect the flash */
	21	+ pci_write_config32(PCH_LPC_DEV, 0xd8, bc);
	22	+}
	23	+
13	24	int arch_cpu_init(void)
14	25	{
	26	+ struct pci_controller *hose;
	27	+ int ret;
	28	+
15	29	post_code(POST_CPU_INIT);
16	30	#ifdef CONFIG_SYS_X86_TSC_TIMER
17	31	timer_set_base(rdtsc());
18	32	#endif
19	33
20		- return x86_cpu_init_f();
	34	+ ret = x86_cpu_init_f();
	35	+ if (ret)
	36	+ return ret;
	37	+
	38	+ ret = pci_early_init_hose(&hose);
	39	+ if (ret)
	40	+ return ret;
	41	+
	42	+ unprotect_spi_flash();
	43	+
	44	+ return 0;
21	45	}
22	46
23	47	int print_cpuinfo(void)
	1	+/*
	2	+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
	3	+ *
	4	+ * SPDX-License-Identifier: GPL-2.0+
	5	+ */
	6	+
	7	+#ifndef _X86_ARCH_TNC_H_
	8	+#define _X86_ARCH_TNC_H_
	9	+
	10	+#include <pci.h>
	11	+
	12	+/* PCI Configuration Space (D31:F0): LPC */
	13	+#define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0)
	14	+
	15	+#endif /* _X86_ARCH_TNC_H_ */
...	...	@@ -45,6 +45,8 @@
45	45	#define CONFIG_SCSI_DEV_LIST \
46	46	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA}
47	47
	48	+#define CONFIG_SPI_FLASH_SST
	49	+
48	50	/* Video is not supported */
49	51	#undef CONFIG_VIDEO
50	52	#undef CONFIG_CFB_CONSOLE