arm: amlogic: p212: Add support for Ethernet with Internal PHY

This patch adds support for the Internal RMII Ethernet PHY on the Amlogic P212 Reference Board. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

arm: amlogic: p212: Add support for Ethernet with Internal PHY
This patch adds support for the Internal RMII Ethernet PHY on the Amlogic P212 Reference Board. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Neil Armstrong · Tom Rini
1 parent ea990816fe
Showing 3 changed files with 44 additions and 1 deletions Side-by-side Diff
board/amlogic/p212/p212.c
configs/p212_defconfig
include/configs/p212.h
@@ -9,7 +9,14 @@
 #include <dm.h>
 #include <asm/io.h>
 #include <asm/arch/gxbb.h>
+#include <asm/arch/sm.h>
+#include <phy.h>
  
+#define EFUSE_SN_OFFSET		20
+#define EFUSE_SN_SIZE		16
+#define EFUSE_MAC_OFFSET	52
+#define EFUSE_MAC_SIZE		6
+
 int board_init(void)
 {
 	return 0;
@@ -17,6 +24,36 @@
  
 int misc_init_r(void)
 {
-       return 0;
+	u8 mac_addr[EFUSE_MAC_SIZE];
+	char serial[EFUSE_SN_SIZE];
+	ssize_t len;
+
+	/* Set RMII mode */
+	out_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_INVERT_RMII_CLK |
+				 GXBB_ETH_REG_0_CLK_EN);
+
+	/* Use Internal PHY */
+	out_le32(GXBB_ETH_REG_2, 0x10110181);
+	out_le32(GXBB_ETH_REG_3, 0xe40908ff);
+
+	/* Enable power and clock gate */
+	setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH);
+	clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK);
+
+	if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
+		len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
+					  mac_addr, EFUSE_MAC_SIZE);
+		if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
+			eth_env_set_enetaddr("ethaddr", mac_addr);
+	}
+
+	if (!env_get("serial#")) {
+		len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
+			EFUSE_SN_SIZE);
+		if (len == EFUSE_SN_SIZE)
+			env_set("serial#", serial);
+	}
+
+	return 0;
 }
@@ -20,6 +20,10 @@
 CONFIG_DM_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_MESON_GX=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_MESON_GXL=y
+CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_MESON_GXL=y
 CONFIG_DEBUG_UART_MESON=y
@@ -12,6 +12,8 @@
  
 #define CONFIG_MISC_INIT_R
  
+#define CONFIG_PHY_ADDR 		8
+
 /* Serial setup */
 #define CONFIG_CONS_INDEX		0
...	...	@@ -9,7 +9,14 @@
9	9	#include <dm.h>
10	10	#include <asm/io.h>
11	11	#include <asm/arch/gxbb.h>
	12	+#include <asm/arch/sm.h>
	13	+#include <phy.h>
12	14
	15	+#define EFUSE_SN_OFFSET 20
	16	+#define EFUSE_SN_SIZE 16
	17	+#define EFUSE_MAC_OFFSET 52
	18	+#define EFUSE_MAC_SIZE 6
	19	+
13	20	int board_init(void)
14	21	{
15	22	return 0;
...	...	@@ -17,6 +24,36 @@
17	24
18	25	int misc_init_r(void)
19	26	{
20		- return 0;
	27	+ u8 mac_addr[EFUSE_MAC_SIZE];
	28	+ char serial[EFUSE_SN_SIZE];
	29	+ ssize_t len;
	30	+
	31	+ /* Set RMII mode */
	32	+ out_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_INVERT_RMII_CLK \|
	33	+ GXBB_ETH_REG_0_CLK_EN);
	34	+
	35	+ /* Use Internal PHY */
	36	+ out_le32(GXBB_ETH_REG_2, 0x10110181);
	37	+ out_le32(GXBB_ETH_REG_3, 0xe40908ff);
	38	+
	39	+ /* Enable power and clock gate */
	40	+ setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH);
	41	+ clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK);
	42	+
	43	+ if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
	44	+ len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
	45	+ mac_addr, EFUSE_MAC_SIZE);
	46	+ if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
	47	+ eth_env_set_enetaddr("ethaddr", mac_addr);
	48	+ }
	49	+
	50	+ if (!env_get("serial#")) {
	51	+ len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial,
	52	+ EFUSE_SN_SIZE);
	53	+ if (len == EFUSE_SN_SIZE)
	54	+ env_set("serial#", serial);
	55	+ }
	56	+
	57	+ return 0;
21	58	}
...	...	@@ -20,6 +20,10 @@
20	20	CONFIG_DM_GPIO=y
21	21	CONFIG_DM_MMC=y
22	22	CONFIG_MMC_MESON_GX=y
	23	+CONFIG_DM_ETH=y
	24	+CONFIG_ETH_DESIGNWARE=y
	25	+CONFIG_PHY_MESON_GXL=y
	26	+CONFIG_NET_RANDOM_ETHADDR=y
23	27	CONFIG_PINCTRL=y
24	28	CONFIG_PINCTRL_MESON_GXL=y
25	29	CONFIG_DEBUG_UART_MESON=y
...	...	@@ -12,6 +12,8 @@
12	12
13	13	#define CONFIG_MISC_INIT_R
14	14
	15	+#define CONFIG_PHY_ADDR 8
	16	+
15	17	/* Serial setup */
16	18	#define CONFIG_CONS_INDEX 0
17	19