powerpc/mpc8536ds: Add eSPI support for MPC8536DS

1. The SD_DATA[4:7] signals are shared with the SPI chip selects on 8536DS, so don't set MPC85xx_PMUXCR_SD_DATA that config eSDHC data bus-width to 4-bit and enable SPI signals. 2. Add eSPI controller and SPI-FLASH definition. Signed-off-by: Xie Xiaobo <r63061@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

powerpc/mpc8536ds: Add eSPI support for MPC8536DS
1. The SD_DATA[4:7] signals are shared with the SPI chip selects on 8536DS, so don't set MPC85xx_PMUXCR_SD_DATA that config eSDHC data bus-width to 4-bit and enable SPI signals. 2. Add eSPI controller and SPI-FLASH definition. Signed-off-by: Xie Xiaobo <r63061@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Xie Xiaobo · Kumar Gala
1 parent 867b06f434
Showing 3 changed files with 21 additions and 4 deletions Side-by-side Diff
arch/powerpc/include/asm/immap_85xx.h
board/freescale/mpc8536ds/mpc8536ds.c
include/configs/MPC8536DS.h
@@ -1934,7 +1934,12 @@
 	u8	res1[8];
 	u32	gpporcr;	/* General-purpose POR configuration */
 	u8	res2[12];
+#if defined(CONFIG_MPC8536)
+	u32	gencfgr;	/* General Configuration Register */
+#define MPC85xx_GENCFGR_SDHC_WP_INV	0x20000000
+#else
 	u32	gpiocr;		/* GPIO control */
+#endif
 	u8	res3[12];
 #if defined(CONFIG_MPC8569)
 	u32	plppar1;	/* Platform port pin assignment 1 */
 /*
- * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008-2010, 2011 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  
@@ -49,10 +49,8 @@
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  
 	setbits_be32(&gur->pmuxcr,
-			(MPC85xx_PMUXCR_SD_DATA |
-			 MPC85xx_PMUXCR_SDHC_CD |
+			(MPC85xx_PMUXCR_SDHC_CD |
 			 MPC85xx_PMUXCR_SDHC_WP));
-
 #endif
 	return 0;
 }
@@ -77,6 +77,7 @@
 #define CONFIG_MPC8536DS	1
  
 #define CONFIG_FSL_ELBC		1	/* Has Enhanced localbus controller */
+#define CONFIG_SPI_FLASH	1	/* Has SPI Flash */
 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
 #define CONFIG_PCI1		1	/* Enable PCI controller 1 */
 #define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
@@ -456,6 +457,19 @@
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
 #define CONFIG_SYS_EEPROM_BUS_NUM	1
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_HARD_SPI
+#define CONFIG_FSL_ESPI
+
+#if defined(CONFIG_SPI_FLASH)
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED	10000000
+#define CONFIG_SF_DEFAULT_MODE	0
+#endif
  
 /*
  * General PCI
...	...	@@ -1934,7 +1934,12 @@
1934	1934	u8 res1[8];
1935	1935	u32 gpporcr; /* General-purpose POR configuration */
1936	1936	u8 res2[12];
	1937	+#if defined(CONFIG_MPC8536)
	1938	+ u32 gencfgr; /* General Configuration Register */
	1939	+#define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000
	1940	+#else
1937	1941	u32 gpiocr; /* GPIO control */
	1942	+#endif
1938	1943	u8 res3[12];
1939	1944	#if defined(CONFIG_MPC8569)
1940	1945	u32 plppar1; /* Platform port pin assignment 1 */
1	1	/*
2		- * Copyright 2008-2010 Freescale Semiconductor, Inc.
	2	+ * Copyright 2008-2010, 2011 Freescale Semiconductor, Inc.
3	3	*
4	4	* See file CREDITS for list of people who contributed to this
5	5	* project.
6	6
...	...	@@ -49,10 +49,8 @@
49	49	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
50	50
51	51	setbits_be32(&gur->pmuxcr,
52		- (MPC85xx_PMUXCR_SD_DATA \|
53		- MPC85xx_PMUXCR_SDHC_CD \|
	52	+ (MPC85xx_PMUXCR_SDHC_CD \|
54	53	MPC85xx_PMUXCR_SDHC_WP));
55		-
56	54	#endif
57	55	return 0;
58	56	}
...	...	@@ -77,6 +77,7 @@
77	77	#define CONFIG_MPC8536DS 1
78	78
79	79	#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
	80	+#define CONFIG_SPI_FLASH 1 /* Has SPI Flash */
80	81	#define CONFIG_PCI 1 /* Enable PCI/PCIE */
81	82	#define CONFIG_PCI1 1 /* Enable PCI controller 1 */
82	83	#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
...	...	@@ -456,6 +457,19 @@
456	457	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
457	458	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
458	459	#define CONFIG_SYS_EEPROM_BUS_NUM 1
	460	+
	461	+/*
	462	+ * eSPI - Enhanced SPI
	463	+ */
	464	+#define CONFIG_HARD_SPI
	465	+#define CONFIG_FSL_ESPI
	466	+
	467	+#if defined(CONFIG_SPI_FLASH)
	468	+#define CONFIG_SPI_FLASH_SPANSION
	469	+#define CONFIG_CMD_SF
	470	+#define CONFIG_SF_DEFAULT_SPEED 10000000
	471	+#define CONFIG_SF_DEFAULT_MODE 0
	472	+#endif
459	473
460	474	/*
461	475	* General PCI