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Commit ae74de0dfd4543a18cf1aee68eb1daeb9c125fde

Authored by Patrice Chotard
Committed by Tom Rini
1 parent e6e5ecc5e2
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

serial: stm32: Rename serial_stm32x7.c to serial_stm32.c 

Now this driver is used across stm32f4, stm32f7 and stm32h7
SoCs family, give it a generic name.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>

Showing 10 changed files with 237 additions and 237 deletions Side-by-side Diff

arch/arm/mach-stm32/Kconfig
Diff comments   View file @ ae74de0
... ... @@ -38,7 +38,7 @@
38 38 select STM32_SDRAM
39 39 select STM32_RCC
40 40 select STM32_RESET
41   - select STM32X7_SERIAL
  41 + select STM32_SERIAL
42 42 select SYSCON
43 43  
44 44 source "arch/arm/mach-stm32/stm32f4/Kconfig"
configs/stm32f429-discovery_defconfig
Diff comments   View file @ ae74de0
... ... @@ -31,5 +31,5 @@
31 31 CONFIG_STM32_SDRAM=y
32 32 CONFIG_DM_RESET=y
33 33 CONFIG_STM32_RESET=y
34   -CONFIG_STM32X7_SERIAL=y
  34 +CONFIG_STM32_SERIAL=y
configs/stm32f469-discovery_defconfig
Diff comments   View file @ ae74de0
... ... @@ -39,5 +39,5 @@
39 39 CONFIG_STM32_SDRAM=y
40 40 CONFIG_DM_RESET=y
41 41 CONFIG_STM32_RESET=y
42   -CONFIG_STM32X7_SERIAL=y
  42 +CONFIG_STM32_SERIAL=y
configs/stm32f746-disco_defconfig
Diff comments   View file @ ae74de0
... ... @@ -60,7 +60,7 @@
60 60 CONFIG_STM32_SDRAM=y
61 61 CONFIG_DM_RESET=y
62 62 CONFIG_STM32_RESET=y
63   -CONFIG_STM32X7_SERIAL=y
  63 +CONFIG_STM32_SERIAL=y
64 64 CONFIG_DM_SPI=y
65 65 CONFIG_STM32_QSPI=y
66 66 CONFIG_OF_LIBFDT_OVERLAY=y
drivers/serial/Kconfig
Diff comments   View file @ ae74de0
... ... @@ -529,7 +529,7 @@
529 529 on STiH410 SoC. This is a basic implementation, it supports
530 530 following baudrate 9600, 19200, 38400, 57600 and 115200.
531 531  
532   -config STM32X7_SERIAL
  532 +config STM32_SERIAL
533 533 bool "STMicroelectronics STM32 SoCs on-chip UART"
534 534 depends on DM_SERIAL && (STM32F4 || STM32F7 || STM32H7)
535 535 help
drivers/serial/Makefile
Diff comments   View file @ ae74de0
... ... @@ -44,7 +44,7 @@
44 44 obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
45 45 obj-$(CONFIG_STI_ASC_SERIAL) += serial_sti_asc.o
46 46 obj-$(CONFIG_PIC32_SERIAL) += serial_pic32.o
47   -obj-$(CONFIG_STM32X7_SERIAL) += serial_stm32x7.o
  47 +obj-$(CONFIG_STM32_SERIAL) += serial_stm32.o
48 48 obj-$(CONFIG_BCM283X_MU_SERIAL) += serial_bcm283x_mu.o
49 49 obj-$(CONFIG_MSM_SERIAL) += serial_msm.o
50 50 obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o
drivers/serial/serial_stm32.c
Diff comments   View file @ ae74de0
  1 +/*
  2 + * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
  3 + * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <clk.h>
  10 +#include <dm.h>
  11 +#include <asm/io.h>
  12 +#include <serial.h>
  13 +#include <asm/arch/stm32.h>
  14 +#include "serial_stm32.h"
  15 +
  16 +DECLARE_GLOBAL_DATA_PTR;
  17 +
  18 +static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
  19 +{
  20 + struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
  21 + bool stm32f4 = plat->uart_info->stm32f4;
  22 + fdt_addr_t base = plat->base;
  23 + u32 int_div, mantissa, fraction, oversampling;
  24 +
  25 + int_div = DIV_ROUND_CLOSEST(plat->clock_rate, baudrate);
  26 +
  27 + if (int_div < 16) {
  28 + oversampling = 8;
  29 + setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
  30 + } else {
  31 + oversampling = 16;
  32 + clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
  33 + }
  34 +
  35 + mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
  36 + fraction = int_div % oversampling;
  37 +
  38 + writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));
  39 +
  40 + return 0;
  41 +}
  42 +
  43 +static int stm32_serial_getc(struct udevice *dev)
  44 +{
  45 + struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
  46 + bool stm32f4 = plat->uart_info->stm32f4;
  47 + fdt_addr_t base = plat->base;
  48 +
  49 + if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_RXNE) == 0)
  50 + return -EAGAIN;
  51 +
  52 + return readl(base + RDR_OFFSET(stm32f4));
  53 +}
  54 +
  55 +static int stm32_serial_putc(struct udevice *dev, const char c)
  56 +{
  57 + struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
  58 + bool stm32f4 = plat->uart_info->stm32f4;
  59 + fdt_addr_t base = plat->base;
  60 +
  61 + if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_TXE) == 0)
  62 + return -EAGAIN;
  63 +
  64 + writel(c, base + TDR_OFFSET(stm32f4));
  65 +
  66 + return 0;
  67 +}
  68 +
  69 +static int stm32_serial_pending(struct udevice *dev, bool input)
  70 +{
  71 + struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
  72 + bool stm32f4 = plat->uart_info->stm32f4;
  73 + fdt_addr_t base = plat->base;
  74 +
  75 + if (input)
  76 + return readl(base + ISR_OFFSET(stm32f4)) &
  77 + USART_SR_FLAG_RXNE ? 1 : 0;
  78 + else
  79 + return readl(base + ISR_OFFSET(stm32f4)) &
  80 + USART_SR_FLAG_TXE ? 0 : 1;
  81 +}
  82 +
  83 +static int stm32_serial_probe(struct udevice *dev)
  84 +{
  85 + struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
  86 + struct clk clk;
  87 + fdt_addr_t base = plat->base;
  88 + int ret;
  89 + bool stm32f4;
  90 + u8 uart_enable_bit;
  91 +
  92 + plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
  93 + stm32f4 = plat->uart_info->stm32f4;
  94 + uart_enable_bit = plat->uart_info->uart_enable_bit;
  95 +
  96 + ret = clk_get_by_index(dev, 0, &clk);
  97 + if (ret < 0)
  98 + return ret;
  99 +
  100 + ret = clk_enable(&clk);
  101 + if (ret) {
  102 + dev_err(dev, "failed to enable clock\n");
  103 + return ret;
  104 + }
  105 +
  106 + plat->clock_rate = clk_get_rate(&clk);
  107 + if (plat->clock_rate < 0) {
  108 + clk_disable(&clk);
  109 + return plat->clock_rate;
  110 + };
  111 +
  112 + /* Disable uart-> disable overrun-> enable uart */
  113 + clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
  114 + BIT(uart_enable_bit));
  115 + if (plat->uart_info->has_overrun_disable)
  116 + setbits_le32(base + CR3_OFFSET(stm32f4), USART_CR3_OVRDIS);
  117 + if (plat->uart_info->has_fifo)
  118 + setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
  119 + setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
  120 + BIT(uart_enable_bit));
  121 +
  122 + return 0;
  123 +}
  124 +
  125 +static const struct udevice_id stm32_serial_id[] = {
  126 + { .compatible = "st,stm32-uart", .data = (ulong)&stm32f4_info},
  127 + { .compatible = "st,stm32f7-uart", .data = (ulong)&stm32f7_info},
  128 + { .compatible = "st,stm32h7-uart", .data = (ulong)&stm32h7_info},
  129 + {}
  130 +};
  131 +
  132 +static int stm32_serial_ofdata_to_platdata(struct udevice *dev)
  133 +{
  134 + struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
  135 +
  136 + plat->base = devfdt_get_addr(dev);
  137 + if (plat->base == FDT_ADDR_T_NONE)
  138 + return -EINVAL;
  139 +
  140 + return 0;
  141 +}
  142 +
  143 +static const struct dm_serial_ops stm32_serial_ops = {
  144 + .putc = stm32_serial_putc,
  145 + .pending = stm32_serial_pending,
  146 + .getc = stm32_serial_getc,
  147 + .setbrg = stm32_serial_setbrg,
  148 +};
  149 +
  150 +U_BOOT_DRIVER(serial_stm32) = {
  151 + .name = "serial_stm32",
  152 + .id = UCLASS_SERIAL,
  153 + .of_match = of_match_ptr(stm32_serial_id),
  154 + .ofdata_to_platdata = of_match_ptr(stm32_serial_ofdata_to_platdata),
  155 + .platdata_auto_alloc_size = sizeof(struct stm32x7_serial_platdata),
  156 + .ops = &stm32_serial_ops,
  157 + .probe = stm32_serial_probe,
  158 + .flags = DM_FLAG_PRE_RELOC,
  159 +};
drivers/serial/serial_stm32.h
Diff comments   View file @ ae74de0
  1 +/*
  2 + * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
  3 + * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef _SERIAL_STM32_
  9 +#define _SERIAL_STM32_
  10 +
  11 +#define CR1_OFFSET(x) (x ? 0x0c : 0x00)
  12 +#define CR3_OFFSET(x) (x ? 0x14 : 0x08)
  13 +#define BRR_OFFSET(x) (x ? 0x08 : 0x0c)
  14 +#define ISR_OFFSET(x) (x ? 0x00 : 0x1c)
  15 +/*
  16 + * STM32F4 has one Data Register (DR) for received or transmitted
  17 + * data, so map Receive Data Register (RDR) and Transmit Data
  18 + * Register (TDR) at the same offset
  19 + */
  20 +#define RDR_OFFSET(x) (x ? 0x04 : 0x24)
  21 +#define TDR_OFFSET(x) (x ? 0x04 : 0x28)
  22 +
  23 +struct stm32_uart_info {
  24 + u8 uart_enable_bit; /* UART_CR1_UE */
  25 + bool stm32f4; /* true for STM32F4, false otherwise */
  26 + bool has_overrun_disable;
  27 + bool has_fifo;
  28 +};
  29 +
  30 +struct stm32_uart_info stm32f4_info = {
  31 + .stm32f4 = true,
  32 + .uart_enable_bit = 13,
  33 + .has_overrun_disable = false,
  34 + .has_fifo = false,
  35 +};
  36 +
  37 +struct stm32_uart_info stm32f7_info = {
  38 + .uart_enable_bit = 0,
  39 + .stm32f4 = false,
  40 + .has_overrun_disable = true,
  41 + .has_fifo = false,
  42 +};
  43 +
  44 +struct stm32_uart_info stm32h7_info = {
  45 + .uart_enable_bit = 0,
  46 + .stm32f4 = false,
  47 + .has_overrun_disable = true,
  48 + .has_fifo = true,
  49 +};
  50 +
  51 +/* Information about a serial port */
  52 +struct stm32x7_serial_platdata {
  53 + fdt_addr_t base; /* address of registers in physical memory */
  54 + struct stm32_uart_info *uart_info;
  55 + unsigned long int clock_rate;
  56 +};
  57 +
  58 +#define USART_CR1_FIFOEN BIT(29)
  59 +#define USART_CR1_OVER8 BIT(15)
  60 +#define USART_CR1_TE BIT(3)
  61 +#define USART_CR1_RE BIT(2)
  62 +
  63 +#define USART_CR3_OVRDIS BIT(12)
  64 +
  65 +#define USART_SR_FLAG_RXNE BIT(5)
  66 +#define USART_SR_FLAG_TXE BIT(7)
  67 +
  68 +#define USART_BRR_F_MASK GENMASK(7, 0)
  69 +#define USART_BRR_M_SHIFT 4
  70 +#define USART_BRR_M_MASK GENMASK(15, 4)
  71 +
  72 +#endif
drivers/serial/serial_stm32x7.c
View file @ ae74de0
1   -/*
2   - * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
3   - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -#include <clk.h>
10   -#include <dm.h>
11   -#include <asm/io.h>
12   -#include <serial.h>
13   -#include <asm/arch/stm32.h>
14   -#include "serial_stm32x7.h"
15   -
16   -DECLARE_GLOBAL_DATA_PTR;
17   -
18   -static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
19   -{
20   - struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
21   - bool stm32f4 = plat->uart_info->stm32f4;
22   - fdt_addr_t base = plat->base;
23   - u32 int_div, mantissa, fraction, oversampling;
24   -
25   - int_div = DIV_ROUND_CLOSEST(plat->clock_rate, baudrate);
26   -
27   - if (int_div < 16) {
28   - oversampling = 8;
29   - setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
30   - } else {
31   - oversampling = 16;
32   - clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
33   - }
34   -
35   - mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
36   - fraction = int_div % oversampling;
37   -
38   - writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));
39   -
40   - return 0;
41   -}
42   -
43   -static int stm32_serial_getc(struct udevice *dev)
44   -{
45   - struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
46   - bool stm32f4 = plat->uart_info->stm32f4;
47   - fdt_addr_t base = plat->base;
48   -
49   - if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_RXNE) == 0)
50   - return -EAGAIN;
51   -
52   - return readl(base + RDR_OFFSET(stm32f4));
53   -}
54   -
55   -static int stm32_serial_putc(struct udevice *dev, const char c)
56   -{
57   - struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
58   - bool stm32f4 = plat->uart_info->stm32f4;
59   - fdt_addr_t base = plat->base;
60   -
61   - if ((readl(base + ISR_OFFSET(stm32f4)) & USART_SR_FLAG_TXE) == 0)
62   - return -EAGAIN;
63   -
64   - writel(c, base + TDR_OFFSET(stm32f4));
65   -
66   - return 0;
67   -}
68   -
69   -static int stm32_serial_pending(struct udevice *dev, bool input)
70   -{
71   - struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
72   - bool stm32f4 = plat->uart_info->stm32f4;
73   - fdt_addr_t base = plat->base;
74   -
75   - if (input)
76   - return readl(base + ISR_OFFSET(stm32f4)) &
77   - USART_SR_FLAG_RXNE ? 1 : 0;
78   - else
79   - return readl(base + ISR_OFFSET(stm32f4)) &
80   - USART_SR_FLAG_TXE ? 0 : 1;
81   -}
82   -
83   -static int stm32_serial_probe(struct udevice *dev)
84   -{
85   - struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
86   - struct clk clk;
87   - fdt_addr_t base = plat->base;
88   - int ret;
89   - bool stm32f4;
90   - u8 uart_enable_bit;
91   -
92   - plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
93   - stm32f4 = plat->uart_info->stm32f4;
94   - uart_enable_bit = plat->uart_info->uart_enable_bit;
95   -
96   - ret = clk_get_by_index(dev, 0, &clk);
97   - if (ret < 0)
98   - return ret;
99   -
100   - ret = clk_enable(&clk);
101   - if (ret) {
102   - dev_err(dev, "failed to enable clock\n");
103   - return ret;
104   - }
105   -
106   - plat->clock_rate = clk_get_rate(&clk);
107   - if (plat->clock_rate < 0) {
108   - clk_disable(&clk);
109   - return plat->clock_rate;
110   - };
111   -
112   - /* Disable uart-> disable overrun-> enable uart */
113   - clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
114   - BIT(uart_enable_bit));
115   - if (plat->uart_info->has_overrun_disable)
116   - setbits_le32(base + CR3_OFFSET(stm32f4), USART_CR3_OVRDIS);
117   - if (plat->uart_info->has_fifo)
118   - setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
119   - setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
120   - BIT(uart_enable_bit));
121   -
122   - return 0;
123   -}
124   -
125   -static const struct udevice_id stm32_serial_id[] = {
126   - { .compatible = "st,stm32-uart", .data = (ulong)&stm32f4_info},
127   - { .compatible = "st,stm32f7-uart", .data = (ulong)&stm32f7_info},
128   - { .compatible = "st,stm32h7-uart", .data = (ulong)&stm32h7_info},
129   - {}
130   -};
131   -
132   -static int stm32_serial_ofdata_to_platdata(struct udevice *dev)
133   -{
134   - struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
135   -
136   - plat->base = devfdt_get_addr(dev);
137   - if (plat->base == FDT_ADDR_T_NONE)
138   - return -EINVAL;
139   -
140   - return 0;
141   -}
142   -
143   -static const struct dm_serial_ops stm32_serial_ops = {
144   - .putc = stm32_serial_putc,
145   - .pending = stm32_serial_pending,
146   - .getc = stm32_serial_getc,
147   - .setbrg = stm32_serial_setbrg,
148   -};
149   -
150   -U_BOOT_DRIVER(serial_stm32) = {
151   - .name = "serial_stm32x7",
152   - .id = UCLASS_SERIAL,
153   - .of_match = of_match_ptr(stm32_serial_id),
154   - .ofdata_to_platdata = of_match_ptr(stm32_serial_ofdata_to_platdata),
155   - .platdata_auto_alloc_size = sizeof(struct stm32x7_serial_platdata),
156   - .ops = &stm32_serial_ops,
157   - .probe = stm32_serial_probe,
158   - .flags = DM_FLAG_PRE_RELOC,
159   -};
drivers/serial/serial_stm32x7.h
View file @ ae74de0
1   -/*
2   - * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
3   - * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#ifndef _SERIAL_STM32_X7_
9   -#define _SERIAL_STM32_X7_
10   -
11   -#define CR1_OFFSET(x) (x ? 0x0c : 0x00)
12   -#define CR3_OFFSET(x) (x ? 0x14 : 0x08)
13   -#define BRR_OFFSET(x) (x ? 0x08 : 0x0c)
14   -#define ISR_OFFSET(x) (x ? 0x00 : 0x1c)
15   -/*
16   - * STM32F4 has one Data Register (DR) for received or transmitted
17   - * data, so map Receive Data Register (RDR) and Transmit Data
18   - * Register (TDR) at the same offset
19   - */
20   -#define RDR_OFFSET(x) (x ? 0x04 : 0x24)
21   -#define TDR_OFFSET(x) (x ? 0x04 : 0x28)
22   -
23   -struct stm32_uart_info {
24   - u8 uart_enable_bit; /* UART_CR1_UE */
25   - bool stm32f4; /* true for STM32F4, false otherwise */
26   - bool has_overrun_disable;
27   - bool has_fifo;
28   -};
29   -
30   -struct stm32_uart_info stm32f4_info = {
31   - .stm32f4 = true,
32   - .uart_enable_bit = 13,
33   - .has_overrun_disable = false,
34   - .has_fifo = false,
35   -};
36   -
37   -struct stm32_uart_info stm32f7_info = {
38   - .uart_enable_bit = 0,
39   - .stm32f4 = false,
40   - .has_overrun_disable = true,
41   - .has_fifo = false,
42   -};
43   -
44   -struct stm32_uart_info stm32h7_info = {
45   - .uart_enable_bit = 0,
46   - .stm32f4 = false,
47   - .has_overrun_disable = true,
48   - .has_fifo = true,
49   -};
50   -
51   -/* Information about a serial port */
52   -struct stm32x7_serial_platdata {
53   - fdt_addr_t base; /* address of registers in physical memory */
54   - struct stm32_uart_info *uart_info;
55   - unsigned long int clock_rate;
56   -};
57   -
58   -#define USART_CR1_FIFOEN BIT(29)
59   -#define USART_CR1_OVER8 BIT(15)
60   -#define USART_CR1_TE BIT(3)
61   -#define USART_CR1_RE BIT(2)
62   -
63   -#define USART_CR3_OVRDIS BIT(12)
64   -
65   -#define USART_SR_FLAG_RXNE BIT(5)
66   -#define USART_SR_FLAG_TXE BIT(7)
67   -
68   -#define USART_BRR_F_MASK GENMASK(7, 0)
69   -#define USART_BRR_M_SHIFT 4
70   -#define USART_BRR_M_MASK GENMASK(15, 4)
71   -
72   -#endif