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Commit aec6f8c59f7b24b46156917a1f41f647c3fa01aa

Authored by Masahiro Yamada
Committed by Tom Rini
1 parent 6bde1ec10f
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

powerpc: mpc8xx: remove FLAGADM board support 

This board has been orphaned for a while and old enough.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Showing 12 changed files with 1 additions and 1373 deletions Side-by-side Diff

arch/powerpc/cpu/mpc8xx/Kconfig
Diff comments   View file @ aec6f8c
... ... @@ -14,9 +14,6 @@
14 14 config TARGET_ESTEEM192E
15 15 bool "Support ESTEEM192E"
16 16  
17   -config TARGET_FLAGADM
18   - bool "Support FLAGADM"
19   -
20 17 config TARGET_HERMES
21 18 bool "Support hermes"
22 19  
... ... @@ -127,7 +124,6 @@
127 124 source "board/eltec/mhpc/Kconfig"
128 125 source "board/emk/top860/Kconfig"
129 126 source "board/esteem192e/Kconfig"
130   -source "board/flagadm/Kconfig"
131 127 source "board/hermes/Kconfig"
132 128 source "board/icu862/Kconfig"
133 129 source "board/ip860/Kconfig"
board/flagadm/Kconfig
View file @ aec6f8c
1   -if TARGET_FLAGADM
2   -
3   -config SYS_BOARD
4   - string
5   - default "flagadm"
6   -
7   -config SYS_CONFIG_NAME
8   - string
9   - default "FLAGADM"
10   -
11   -endif
board/flagadm/MAINTAINERS
View file @ aec6f8c
1   -FLAGADM BOARD
2   -M: Kári Davíðsson <kd@flaga.is>
3   -S: Orphan (since 2014-06)
4   -F: board/flagadm/
5   -F: include/configs/FLAGADM.h
6   -F: configs/FLAGADM_defconfig
board/flagadm/Makefile
View file @ aec6f8c
1   -#
2   -# (C) Copyright 2001-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -obj-y = flagadm.o flash.o
board/flagadm/flagadm.c
View file @ aec6f8c
1   -/*
2   - * (C) Copyright 2001
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -#include <mpc8xx.h>
10   -
11   -#define _NOT_USED_ 0xFFFFFFFF
12   -
13   -/*Orginal table, GPL4 disabled*/
14   -const uint sdram_table[] =
15   -{
16   - /* single read (offset 0x00 in upm ram) */
17   - 0x1f07cc04, 0xeeaeec04, 0x11adcc04, 0xefbbac00,
18   - 0x1ff74c47,
19   - /* Precharge */
20   - 0x1FF74C05,
21   - _NOT_USED_,
22   - _NOT_USED_,
23   - /* burst read (offset 0x08 in upm ram) */
24   - 0x1f07cc04, 0xeeaeec04, 0x00adcc04, 0x00afcc00,
25   - 0x00afcc00, 0x01afcc00, 0x0fbb8c00, 0x1ff74c47,
26   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
27   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
28   - /* single write (offset 0x18 in upm ram) */
29   - 0x1f27cc04, 0xeeaeac00, 0x01b90c04, 0x1ff74c47,
30   - /* Load moderegister */
31   - 0x1FF74C34, /*Precharge*/
32   - 0xEFEA8C34, /*NOP*/
33   - 0x1FB54C35, /*Load moderegister*/
34   - _NOT_USED_,
35   -
36   - /* burst write (offset 0x20 in upm ram) */
37   - 0x1f07cc04, 0xeeaeac00, 0x00ad4c00, 0x00afcc00,
38   - 0x00afcc00, 0x01bb8c04, 0x1ff74c47, _NOT_USED_,
39   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
40   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
41   - /* refresh (offset 0x30 in upm ram) */
42   - 0x1ff5cc84, 0xffffec04, 0xffffec04, 0xffffec04,
43   - 0xffffec84, 0xffffec07, _NOT_USED_, _NOT_USED_,
44   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
45   - /* exception (offset 0x3C in upm ram) */
46   - 0x7fffec07, _NOT_USED_, _NOT_USED_, _NOT_USED_,
47   -};
48   -
49   -/* GPL5 driven every cycle */
50   -/* the display and the DSP */
51   -const uint dsp_disp_table[] =
52   -{
53   - /* single read (offset 0x00 in upm ram) */
54   - 0xffffc80c, 0xffffc004, 0x0fffc004, 0x0fffd004,
55   - 0x0fffc000, 0x0fffc004, 0x3fffc004, 0xffffcc05,
56   - /* burst read (offset 0x08 in upm ram) */
57   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
58   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
59   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
60   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
61   - /* single write (offset 0x18 in upm ram) */
62   - 0xffffcc0c, 0xffffc004, 0x0fffc004, 0x0fffd004,
63   - 0x0fffc000, 0x0fffc004, 0x7fffc004, 0xfffffc05,
64   - /* burst write (offset 0x20 in upm ram) */
65   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
66   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
67   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
68   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
69   - /* refresh (offset 0x30 in upm ram) */
70   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
71   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
72   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
73   - /* exception (offset 0x3C in upm ram) */
74   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
75   -};
76   -
77   -int checkboard (void)
78   -{
79   - puts ("Board: FlagaDM V3.0\n");
80   - return 0;
81   -}
82   -
83   -phys_size_t initdram (int board_type)
84   -{
85   - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
86   - volatile memctl8xx_t *memctl = &immap->im_memctl;
87   - long int size_b0;
88   -
89   - memctl->memc_or2 = CONFIG_SYS_OR2;
90   - memctl->memc_br2 = CONFIG_SYS_BR2;
91   -
92   - udelay(100);
93   - upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
94   -
95   - memctl->memc_mptpr = MPTPR_PTP_DIV16;
96   - memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_1X;
97   -
98   - /*Do the initialization of the SDRAM*/
99   - /*Start with the precharge cycle*/
100   - memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \
101   - MCR_MLCF(1) | MCR_MAD(0x5));
102   -
103   - /*Then we need two refresh cycles*/
104   - memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_2X;
105   - memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \
106   - MCR_MLCF(2) | MCR_MAD(0x30));
107   -
108   - /*Mode register programming*/
109   - memctl->memc_mar = 0x00000088; /*CAS Latency = 2 and burst length = 4*/
110   - memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \
111   - MCR_MLCF(1) | MCR_MAD(0x1C));
112   -
113   - /* That should do it, just enable the periodic refresh in burst of 4*/
114   - memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_4X;
115   - memctl->memc_mamr |= (MAMR_PTAE | MAMR_GPL_A4DIS);
116   -
117   - size_b0 = 16*1024*1024;
118   -
119   - /*
120   - * No bank 1 or 3
121   - * invalidate bank
122   - */
123   - memctl->memc_br1 = 0;
124   - memctl->memc_br3 = 0;
125   -
126   - upmconfig(UPMB, (uint *)dsp_disp_table, sizeof(dsp_disp_table)/sizeof(uint));
127   -
128   - memctl->memc_mbmr = MBMR_GPL_B4DIS;
129   -
130   - memctl->memc_or4 = CONFIG_SYS_OR4;
131   - memctl->memc_br4 = CONFIG_SYS_BR4;
132   -
133   - return (size_b0);
134   -}
board/flagadm/flash.c
View file @ aec6f8c
1   -/*
2   - * (C) Copyright 2001
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -#include <mpc8xx.h>
10   -#include <flash.h>
11   -
12   -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
13   -
14   -/*-----------------------------------------------------------------------
15   - * Functions
16   - */
17   -ulong flash_recognize (vu_long *base);
18   -int write_word (flash_info_t *info, ulong dest, ulong data);
19   -void flash_get_geometry (vu_long *base, flash_info_t *info);
20   -void flash_unprotect(flash_info_t *info);
21   -int _flash_real_protect(flash_info_t *info, long idx, int on);
22   -
23   -
24   -unsigned long flash_init (void)
25   -{
26   - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
27   - volatile memctl8xx_t *memctl = &immap->im_memctl;
28   - int i;
29   - int rec;
30   -
31   - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
32   - flash_info[i].flash_id = FLASH_UNKNOWN;
33   - }
34   -
35   - *((vu_short*)CONFIG_SYS_FLASH_BASE) = 0xffff;
36   -
37   - flash_get_geometry ((vu_long*)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
38   -
39   - /* Remap FLASH according to real size */
40   - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-flash_info[0].size & 0xFFFF8000);
41   - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
42   - (memctl->memc_br0 & ~(BR_BA_MSK));
43   -
44   - rec = flash_recognize((vu_long*)CONFIG_SYS_FLASH_BASE);
45   -
46   - if (rec == FLASH_UNKNOWN) {
47   - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
48   - flash_info[0].size, flash_info[0].size<<20);
49   - }
50   -
51   -#if CONFIG_SYS_FLASH_PROTECTION
52   - /*Unprotect all the flash memory*/
53   - flash_unprotect(&flash_info[0]);
54   -#endif
55   -
56   - *((vu_short*)CONFIG_SYS_FLASH_BASE) = 0xffff;
57   -
58   - return (flash_info[0].size);
59   -
60   -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
61   - /* monitor protection ON by default */
62   - flash_protect(FLAG_PROTECT_SET,
63   - CONFIG_SYS_MONITOR_BASE,
64   - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
65   - &flash_info[0]);
66   -#endif
67   -
68   -#ifdef CONFIG_ENV_IS_IN_FLASH
69   - /* ENV protection ON by default */
70   - flash_protect(FLAG_PROTECT_SET,
71   - CONFIG_ENV_OFFSET,
72   - CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE-1,
73   - &flash_info[0]);
74   -#endif
75   - return (flash_info[0].size);
76   -}
77   -
78   -
79   -int flash_get_protect_status(flash_info_t * info, long idx)
80   -{
81   - vu_short * base;
82   - ushort res;
83   -
84   -#ifdef DEBUG
85   - printf("\n Attempting to set protection info with %d sectors\n", info->sector_count);
86   -#endif
87   -
88   -
89   - base = (vu_short*)info->start[idx];
90   -
91   - *(base) = 0xffff;
92   -
93   - *(base + 0x55) = 0x0098;
94   - res = base[0x2];
95   -
96   - *(base) = 0xffff;
97   -
98   - if(res != 0)
99   - res = 1;
100   - else
101   - res = 0;
102   -
103   - return res;
104   -}
105   -
106   -void flash_get_geometry (vu_long *base, flash_info_t *info)
107   -{
108   - int i,j;
109   - ulong ner = 0;
110   - vu_short * sb = (vu_short*)base;
111   - ulong offset = (ulong)base;
112   -
113   - /* Read Device geometry */
114   -
115   - *sb = 0xffff;
116   -
117   - *sb = 0x0090;
118   -
119   - info->flash_id = ((ulong)base[0x0]);
120   -#ifdef DEBUG
121   - printf("Id is %x\n", (uint)(ulong)info->flash_id);
122   -#endif
123   -
124   - *sb = 0xffff;
125   -
126   - *(sb+0x55) = 0x0098;
127   -
128   - info->size = 1 << (sb[0x27]); /* Read flash size */
129   -
130   -#ifdef DEBUG
131   - printf("Size is %x\n", (uint)(ulong)info->size);
132   -#endif
133   -
134   - *sb = 0xffff;
135   -
136   - *(sb + 0x55) = 0x0098;
137   - ner = sb[0x2c] ; /*Number of erase regions*/
138   -
139   -#ifdef DEBUG
140   - printf("Number of erase regions %x\n", (uint)ner);
141   -#endif
142   -
143   - info->sector_count = 0;
144   -
145   - for(i = 0; i < ner; i++)
146   - {
147   - uint s;
148   - uint count;
149   - uint t1,t2,t3,t4;
150   -
151   - *sb = 0xffff;
152   -
153   - *(sb + 0x55) = 0x0098;
154   -
155   - t1 = sb[0x2d + i*4];
156   - t2 = sb[0x2e + i*4];
157   - t3 = sb[0x2f + i*4];
158   - t4 = sb[0x30 + i*4];
159   -
160   - count = ((t1 & 0x00ff) | (((t2 & 0x00ff) << 8) & 0xff00) )+ 1; /*sector count*/
161   - s = ((t3 & 0x00ff) | (((t4 & 0x00ff) << 8) & 0xff00)) * 256;; /*Sector size*/
162   -
163   -#ifdef DEBUG
164   - printf("count and size %x, %x\n", count, s);
165   - printf("sector count for erase region %d is %d\n", i, count);
166   -#endif
167   - for(j = 0; j < count; j++)
168   - {
169   -#ifdef DEBUG
170   - printf("%x, ", (uint)offset);
171   -#endif
172   - info->start[ info->sector_count + j] = offset;
173   - offset += s;
174   - }
175   - info->sector_count += count;
176   - }
177   -
178   - if ((offset - (ulong)base) != info->size)
179   - printf("WARNING reported size %x does not match to calculted size %x.\n"
180   - , (uint)info->size, (uint)(offset - (ulong)base) );
181   -
182   - /* Next check if there are any sectors protected.*/
183   -
184   - for(i = 0; i < info->sector_count; i++)
185   - info->protect[i] = flash_get_protect_status(info, i);
186   -
187   - *sb = 0xffff;
188   -}
189   -
190   -/*-----------------------------------------------------------------------
191   - */
192   -void flash_print_info (flash_info_t *info)
193   -{
194   - int i;
195   -
196   - if (info->flash_id == FLASH_UNKNOWN) {
197   - printf ("missing or unknown FLASH type\n");
198   - return ;
199   - }
200   -
201   - switch (info->flash_id & FLASH_VENDMASK) {
202   - case INTEL_MANUFACT & FLASH_VENDMASK:
203   - printf ("Intel ");
204   - break;
205   - default:
206   - printf ("Unknown Vendor ");
207   - break;
208   - }
209   -
210   - switch (info->flash_id & FLASH_TYPEMASK) {
211   - case INTEL_ID_28F320C3B & FLASH_TYPEMASK:
212   - printf ("28F320RC3(4 MB)\n");
213   - break;
214   - case INTEL_ID_28F320J3A:
215   - printf("28F320J3A (4 MB)\n");
216   - break;
217   - default:
218   - printf ("Unknown Chip Type\n");
219   - break;
220   - }
221   -
222   - printf (" Size: %ld MB in %d Sectors\n",
223   - info->size >> 20, info->sector_count);
224   -
225   - printf (" Sector Start Addresses:");
226   - for (i=0; i<info->sector_count; ++i) {
227   - if ((i % 4) == 0)
228   - printf ("\n ");
229   - printf (" %02d %08lX%s",
230   - i, info->start[i],
231   - info->protect[i]!=0 ? " (RO)" : " "
232   - );
233   - }
234   - printf ("\n");
235   - return ;
236   -}
237   -
238   -ulong flash_recognize (vu_long *base)
239   -{
240   - ulong id;
241   - ulong res = FLASH_UNKNOWN;
242   - vu_short * sb = (vu_short*)base;
243   -
244   - *sb = 0xffff;
245   -
246   - *sb = 0x0090;
247   - id = base[0];
248   -
249   - switch (id & 0x00FF0000)
250   - {
251   - case (MT_MANUFACT & 0x00FF0000): /* MT or => Intel */
252   - case (INTEL_ALT_MANU & 0x00FF0000):
253   - res = FLASH_MAN_INTEL;
254   - break;
255   - default:
256   - res = FLASH_UNKNOWN;
257   - }
258   -
259   - *sb = 0xffff;
260   -
261   - return res;
262   -}
263   -
264   -/*-----------------------------------------------------------------------*/
265   -#define INTEL_FLASH_STATUS_BLS 0x02
266   -#define INTEL_FLASH_STATUS_PSS 0x04
267   -#define INTEL_FLASH_STATUS_VPPS 0x08
268   -#define INTEL_FLASH_STATUS_PS 0x10
269   -#define INTEL_FLASH_STATUS_ES 0x20
270   -#define INTEL_FLASH_STATUS_ESS 0x40
271   -#define INTEL_FLASH_STATUS_WSMS 0x80
272   -
273   -int flash_decode_status_bits(char status)
274   -{
275   - int err = 0;
276   -
277   - if(!(status & INTEL_FLASH_STATUS_WSMS)) {
278   - printf("Busy\n");
279   - err = -1;
280   - }
281   -
282   - if(status & INTEL_FLASH_STATUS_ESS) {
283   - printf("Erase suspended\n");
284   - err = -1;
285   - }
286   -
287   - if(status & INTEL_FLASH_STATUS_ES) {
288   - printf("Error in block erase\n");
289   - err = -1;
290   - }
291   -
292   - if(status & INTEL_FLASH_STATUS_PS) {
293   - printf("Error in programming\n");
294   - err = -1;
295   - }
296   -
297   - if(status & INTEL_FLASH_STATUS_VPPS) {
298   - printf("Vpp low, operation aborted\n");
299   - err = -1;
300   - }
301   -
302   - if(status & INTEL_FLASH_STATUS_PSS) {
303   - printf("Program is suspended\n");
304   - err = -1;
305   - }
306   -
307   - if(status & INTEL_FLASH_STATUS_BLS) {
308   - printf("Attempting to program/erase a locked sector\n");
309   - err = -1;
310   - }
311   -
312   - if((status & INTEL_FLASH_STATUS_PS) &&
313   - (status & INTEL_FLASH_STATUS_ES) &&
314   - (status & INTEL_FLASH_STATUS_ESS)) {
315   - printf("A command sequence error\n");
316   - return -1;
317   - }
318   -
319   - return err;
320   -}
321   -
322   -/*-----------------------------------------------------------------------
323   - */
324   -
325   -int flash_erase (flash_info_t *info, int s_first, int s_last)
326   -{
327   - vu_short *addr;
328   - int flag, prot, sect;
329   - ulong start, now;
330   - int rcode = 0;
331   -
332   - if ((s_first < 0) || (s_first > s_last)) {
333   - if (info->flash_id == FLASH_UNKNOWN) {
334   - printf ("- missing\n");
335   - } else {
336   - printf ("- no sectors to erase\n");
337   - }
338   - return 1;
339   - }
340   -
341   - if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) {
342   - printf ("Can't erase unknown flash type %08lx - aborted\n",
343   - info->flash_id);
344   - return 1;
345   - }
346   -
347   - prot = 0;
348   - for (sect=s_first; sect<=s_last; ++sect) {
349   - if (info->protect[sect]) {
350   - prot++;
351   - }
352   - }
353   -
354   - if (prot) {
355   - printf ("- Warning: %d protected sectors will not be erased!\n",
356   - prot);
357   - } else {
358   - printf ("\n");
359   - }
360   -
361   - start = get_timer (0);
362   -
363   - /* Start erase on unprotected sectors */
364   - for (sect = s_first; sect<=s_last; sect++) {
365   - char tmp;
366   -
367   - if (info->protect[sect] == 0) { /* not protected */
368   - addr = (vu_short *)(info->start[sect]);
369   -
370   - /* Disable interrupts which might cause a timeout here */
371   - flag = disable_interrupts();
372   -
373   - /* Single Block Erase Command */
374   - *addr = 0x0020;
375   - /* Confirm */
376   - *addr = 0x00D0;
377   - /* Resume Command, as per errata update */
378   - *addr = 0x00D0;
379   -
380   - /* re-enable interrupts if necessary */
381   - if (flag)
382   - enable_interrupts();
383   -
384   - *addr = 0x70; /*Read status register command*/
385   - tmp = (short)*addr & 0x00FF; /* Read the status */
386   - while (!(tmp & INTEL_FLASH_STATUS_WSMS)) {
387   - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
388   - *addr = 0x0050; /* Reset the status register */
389   - *addr = 0xffff;
390   - printf ("Timeout\n");
391   - return 1;
392   - }
393   - /* show that we're waiting */
394   - if ((now - start) > 1000) { /* every second */
395   - putc ('.');
396   - }
397   - udelay(100000); /* 100 ms */
398   - *addr = 0x0070; /*Read status register command*/
399   - tmp = (short)*addr & 0x00FF; /* Read status */
400   - start = get_timer(0);
401   - }
402   - if( tmp & INTEL_FLASH_STATUS_ES )
403   - flash_decode_status_bits(tmp);
404   -
405   - *addr = 0x0050; /* Reset the status register */
406   - *addr = 0xffff; /* Reset to read mode */
407   - }
408   - }
409   -
410   -
411   - printf (" done\n");
412   - return rcode;
413   -}
414   -
415   -void flash_unprotect (flash_info_t *info)
416   -{
417   - /*We can only unprotect the whole flash at once*/
418   - /*Therefore we must prevent the _flash_real_protect()*/
419   - /*from re-protecting sectors, that ware protected before */
420   - /*we called flash_real_protect();*/
421   -
422   - int i;
423   -
424   - for(i = 0; i < info->sector_count; i++)
425   - info->protect[i] = 0;
426   -
427   -#ifdef CONFIG_SYS_FLASH_PROTECTION
428   - _flash_real_protect(info, 0, 0);
429   -#endif
430   -}
431   -
432   -/*-----------------------------------------------------------------------
433   - * Copy memory to flash, returns:
434   - * 0 - OK
435   - * 1 - write timeout
436   - * 2 - Flash not erased
437   - */
438   -
439   -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
440   -{
441   - ulong cp, wp, data;
442   - int i, l, rc;
443   -
444   - wp = (addr & ~3); /* get lower word aligned address */
445   -
446   - /*
447   - * handle unaligned start bytes
448   - */
449   - if ((l = addr - wp) != 0) {
450   - data = 0;
451   - for (i=0, cp=wp; i<l; ++i, ++cp) {
452   - data = (data << 8) | (*(uchar *)cp);
453   - }
454   - for (; i<4 && cnt>0; ++i) {
455   - data = (data << 8) | *src++;
456   - --cnt;
457   - ++cp;
458   - }
459   - for (; cnt==0 && i<4; ++i, ++cp) {
460   - data = (data << 8) | (*(uchar *)cp);
461   - }
462   -
463   - if ((rc = write_word(info, wp, data)) != 0) {
464   - return (rc);
465   - }
466   - wp += 4;
467   - }
468   -
469   - /*
470   - * handle word aligned part
471   - */
472   - while (cnt >= 4) {
473   - data = 0;
474   - for (i=0; i<4; ++i) {
475   - data = (data << 8) | *src++;
476   - }
477   - if ((rc = write_word(info, wp, data)) != 0) {
478   - return (rc);
479   - }
480   - wp += 4;
481   - cnt -= 4;
482   - }
483   -
484   - if (cnt == 0) {
485   - return (0);
486   - }
487   -
488   - /*
489   - * handle unaligned tail bytes
490   - */
491   - data = 0;
492   - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
493   - data = (data << 8) | *src++;
494   - --cnt;
495   - }
496   - for (; i<4; ++i, ++cp) {
497   - data = (data << 8) | (*(uchar *)cp);
498   - }
499   -
500   - return (write_word(info, wp, data));
501   -}
502   -
503   -/*-----------------------------------------------------------------------
504   - * Write a word to Flash, returns:
505   - * 0 - OK
506   - * 1 - write timeout
507   - * 2 - Flash not erased
508   - */
509   -int write_word (flash_info_t *info, ulong dest, ulong da)
510   -{
511   - vu_short *addr = (vu_short *)dest;
512   - ulong start;
513   - char csr;
514   - int flag;
515   - int i;
516   - union {
517   - u32 data32;
518   - u16 data16[2];
519   - } data;
520   -
521   - data.data32 = da;
522   -
523   - /* Check if Flash is (sufficiently) erased */
524   - if (((*addr & data.data16[0]) != data.data16[0]) ||
525   - ((*(addr+1) & data.data16[1]) != data.data16[1])) {
526   - return (2);
527   - }
528   - /* Disable interrupts which might cause a timeout here */
529   - flag = disable_interrupts();
530   -
531   - for(i = 0; i < 2; i++)
532   - {
533   - /* Write Command */
534   - *addr = 0x0010;
535   -
536   - /* Write Data */
537   - *addr = data.data16[i];
538   -
539   - /* re-enable interrupts if necessary */
540   - if (flag)
541   - enable_interrupts();
542   -
543   - /* data polling for D7 */
544   - start = get_timer (0);
545   - flag = 0;
546   - *addr = 0x0070; /*Read statusregister command */
547   - while (((csr = *addr) & INTEL_FLASH_STATUS_WSMS)!=INTEL_FLASH_STATUS_WSMS) {
548   - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
549   - flag = 1;
550   - break;
551   - }
552   - *addr = 0x0070; /*Read statusregister command */
553   - }
554   - if (csr & INTEL_FLASH_STATUS_PSS) {
555   - printf ("CSR indicates write error (%0x) at %08lx\n",
556   - csr, (ulong)addr);
557   - flag = 1;
558   - }
559   -
560   - /* Clear Status Registers Command */
561   - *addr = 0x0050;
562   - /* Reset to read array mode */
563   - *addr = 0xffff;
564   - addr++;
565   - }
566   -
567   - return (flag);
568   -}
569   -
570   -int flash_real_protect(flash_info_t *info, long offset, int prot)
571   -{
572   - int i, idx;
573   -
574   - for(idx = 0; idx < info->sector_count; idx++)
575   - if(info->start[idx] == offset)
576   - break;
577   -
578   - if(idx==info->sector_count)
579   - return -1;
580   -
581   - if(prot == 0) {
582   - /* Unprotect one sector, which means unprotect all flash
583   - * and reprotect the other protected sectors.
584   - */
585   - _flash_real_protect(info, 0, 0); /* Unprotects the whole flash*/
586   - info->protect[idx] = 0;
587   -
588   - for(i = 0; i < info->sector_count; i++)
589   - if(info->protect[i])
590   - _flash_real_protect(info, i, 1);
591   - }
592   - else {
593   - /* We can protect individual sectors */
594   - _flash_real_protect(info, idx, 1);
595   - }
596   -
597   - for( i = 0; i < info->sector_count; i++)
598   - info->protect[i] = flash_get_protect_status(info, i);
599   -
600   - return 0;
601   -}
602   -
603   -int _flash_real_protect(flash_info_t *info, long idx, int prot)
604   -{
605   - vu_short *addr;
606   - int flag;
607   - ushort cmd;
608   - ushort tmp;
609   - ulong now, start;
610   -
611   - if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) {
612   - printf ("Can't change protection for unknown flash type %08lx - aborted\n",
613   - info->flash_id);
614   - return -1;
615   - }
616   -
617   - if(prot == 0) {
618   - /*Unlock the sector*/
619   - cmd = 0x00D0;
620   - }
621   - else {
622   - /*Lock the sector*/
623   - cmd = 0x0001;
624   - }
625   -
626   - addr = (vu_short *)(info->start[idx]);
627   -
628   - /* If chip is busy, wait for it */
629   - start = get_timer(0);
630   - *addr = 0x0070; /*Read status register command*/
631   - tmp = ((ushort)(*addr))&0x00ff; /*Read the status*/
632   - while(!(tmp & INTEL_FLASH_STATUS_WSMS)) {
633   - /*Write State Machine Busy*/
634   - /*Wait untill done or timeout.*/
635   - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) {
636   - *addr = 0x0050; /* Reset the status register */
637   - *addr = 0xffff; /* Reset the chip */
638   - printf ("TTimeout\n");
639   - return 1;
640   - }
641   - *addr = 0x0070;
642   - tmp = ((ushort)(*addr))&0x00ff; /*Read the status*/
643   - start = get_timer(0);
644   - }
645   -
646   - /* Disable interrupts which might cause a timeout here */
647   - flag = disable_interrupts();
648   -
649   - /* Unlock block*/
650   - *addr = 0x0060;
651   -
652   - *addr = cmd;
653   -
654   - /* re-enable interrupts if necessary */
655   - if (flag)
656   - enable_interrupts();
657   -
658   - start = get_timer(0);
659   - *addr = 0x0070; /*Read status register command*/
660   - tmp = ((ushort)(*addr)) & 0x00FF; /* Read the status */
661   - while (!(tmp & INTEL_FLASH_STATUS_WSMS)) {
662   - /* Write State Machine Busy */
663   - if ((now=get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) {
664   - *addr = 0x0050; /* Reset the status register */
665   - *addr = 0xffff;
666   - printf ("Timeout\n");
667   - return 1;
668   - }
669   - /* show that we're waiting */
670   - if ((now - start) > 1000) { /* every second */
671   - putc ('.');
672   - }
673   - udelay(100000); /* 100 ms */
674   - *addr = 0x70; /*Read status register command*/
675   - tmp = (short)*addr & 0x00FF; /* Read status */
676   - start = get_timer(0);
677   - }
678   - if( tmp & INTEL_FLASH_STATUS_PS )
679   - flash_decode_status_bits(tmp);
680   -
681   - *addr =0x0050; /*Clear status register*/
682   -
683   - /* reset to read mode */
684   - *addr = 0xffff;
685   -
686   - return 0;
687   -}
board/flagadm/u-boot.lds
View file @ aec6f8c
1   -/*
2   - * (C) Copyright 2001-2010
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -OUTPUT_ARCH(powerpc)
9   -
10   -SECTIONS
11   -{
12   - /* Read-only sections, merged into text segment: */
13   - . = + SIZEOF_HEADERS;
14   - .text :
15   - {
16   - arch/powerpc/cpu/mpc8xx/start.o (.text*)
17   - arch/powerpc/cpu/mpc8xx/traps.o (.text*)
18   -
19   - *(.text*)
20   - }
21   - _etext = .;
22   - PROVIDE (etext = .);
23   - .rodata :
24   - {
25   - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
26   - }
27   -
28   - /* Read-write section, merged into data segment: */
29   - . = (. + 0x00FF) & 0xFFFFFF00;
30   - _erotext = .;
31   - PROVIDE (erotext = .);
32   - .reloc :
33   - {
34   - _GOT2_TABLE_ = .;
35   - KEEP(*(.got2))
36   - KEEP(*(.got))
37   - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
38   - _FIXUP_TABLE_ = .;
39   - KEEP(*(.fixup))
40   - }
41   - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
42   - __fixup_entries = (. - _FIXUP_TABLE_)>>2;
43   -
44   - .data :
45   - {
46   - *(.data*)
47   - *(.sdata*)
48   - }
49   - _edata = .;
50   - PROVIDE (edata = .);
51   -
52   - . = .;
53   -
54   - . = ALIGN(4);
55   - .u_boot_list : {
56   - KEEP(*(SORT(.u_boot_list*)));
57   - }
58   -
59   -
60   - . = .;
61   - __start___ex_table = .;
62   - __ex_table : { *(__ex_table) }
63   - __stop___ex_table = .;
64   -
65   - . = ALIGN(256);
66   - __init_begin = .;
67   - .text.init : { *(.text.init) }
68   - .data.init : { *(.data.init) }
69   - . = ALIGN(256);
70   - __init_end = .;
71   -
72   - __bss_start = .;
73   - .bss (NOLOAD) :
74   - {
75   - *(.bss*)
76   - *(.sbss*)
77   - *(COMMON)
78   - . = ALIGN(4);
79   - }
80   - __bss_end = . ;
81   - PROVIDE (end = .);
82   -}
board/flagadm/u-boot.lds.debug
View file @ aec6f8c
1   -/*
2   - * (C) Copyright 2001
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -OUTPUT_ARCH(powerpc)
9   -/* Do we need any of these for elf?
10   - __DYNAMIC = 0; */
11   -SECTIONS
12   -{
13   - /* Read-only sections, merged into text segment: */
14   - . = + SIZEOF_HEADERS;
15   - .interp : { *(.interp) }
16   - .hash : { *(.hash) }
17   - .dynsym : { *(.dynsym) }
18   - .dynstr : { *(.dynstr) }
19   - .rel.text : { *(.rel.text) }
20   - .rela.text : { *(.rela.text) }
21   - .rel.data : { *(.rel.data) }
22   - .rela.data : { *(.rela.data) }
23   - .rel.rodata : { *(.rel.rodata) }
24   - .rela.rodata : { *(.rela.rodata) }
25   - .rel.got : { *(.rel.got) }
26   - .rela.got : { *(.rela.got) }
27   - .rel.ctors : { *(.rel.ctors) }
28   - .rela.ctors : { *(.rela.ctors) }
29   - .rel.dtors : { *(.rel.dtors) }
30   - .rela.dtors : { *(.rela.dtors) }
31   - .rel.bss : { *(.rel.bss) }
32   - .rela.bss : { *(.rela.bss) }
33   - .rel.plt : { *(.rel.plt) }
34   - .rela.plt : { *(.rela.plt) }
35   - .init : { *(.init) }
36   - .plt : { *(.plt) }
37   - .text :
38   - {
39   - /* WARNING - the following is hand-optimized to fit within */
40   - /* the sector layout of our flash chips! XXX FIXME XXX */
41   -
42   - arch/powerpc/cpu/mpc8xx/start.o (.text)
43   - common/dlmalloc.o (.text)
44   - lib/vsprintf.o (.text)
45   - lib/crc32.o (.text)
46   -
47   - . = env_offset;
48   - common/env_embedded.o(.text)
49   -
50   - *(.text)
51   - *(.got1)
52   - }
53   - _etext = .;
54   - PROVIDE (etext = .);
55   - .rodata :
56   - {
57   - *(.rodata)
58   - *(.rodata1)
59   - *(.rodata.str1.4)
60   - *(.eh_frame)
61   - }
62   - .fini : { *(.fini) } =0
63   - .ctors : { *(.ctors) }
64   - .dtors : { *(.dtors) }
65   -
66   - /* Read-write section, merged into data segment: */
67   - . = (. + 0x0FFF) & 0xFFFFF000;
68   - _erotext = .;
69   - PROVIDE (erotext = .);
70   - .reloc :
71   - {
72   - *(.got)
73   - _GOT2_TABLE_ = .;
74   - *(.got2)
75   - _FIXUP_TABLE_ = .;
76   - *(.fixup)
77   - }
78   - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
79   - __fixup_entries = (. - _FIXUP_TABLE_)>>2;
80   -
81   - .data :
82   - {
83   - *(.data)
84   - *(.data1)
85   - *(.sdata)
86   - *(.sdata2)
87   - *(.dynamic)
88   - CONSTRUCTORS
89   - }
90   - _edata = .;
91   - PROVIDE (edata = .);
92   -
93   -
94   - . = ALIGN(4);
95   - .u_boot_list : {
96   - KEEP(*(SORT(.u_boot_list*)));
97   - }
98   -
99   -
100   - __start___ex_table = .;
101   - __ex_table : { *(__ex_table) }
102   - __stop___ex_table = .;
103   -
104   - . = ALIGN(4096);
105   - __init_begin = .;
106   - .text.init : { *(.text.init) }
107   - .data.init : { *(.data.init) }
108   - . = ALIGN(4096);
109   - __init_end = .;
110   -
111   - __bss_start = .;
112   - .bss :
113   - {
114   - *(.sbss) *(.scommon)
115   - *(.dynbss)
116   - *(.bss)
117   - *(COMMON)
118   - }
119   - __bss_end = . ;
120   - PROVIDE (end = .);
121   -}
configs/FLAGADM_defconfig
View file @ aec6f8c
1   -CONFIG_PPC=y
2   -CONFIG_8xx=y
3   -CONFIG_TARGET_FLAGADM=y
doc/README.scrapyard
Diff comments   View file @ aec6f8c
... ... @@ -12,6 +12,7 @@
12 12  
13 13 Board Arch CPU Commit Removed Last known maintainer/contact
14 14 =================================================================================================
  15 +flagadm powerpc mpc8xx - - Kári Davíðsson <kd@flaga.is>
15 16 gen860t powerpc mpc8xx - - Keith Outwater <Keith_Outwater@mvis.com>
16 17 sixnet powerpc mpc8xx - - Dave Ellis <DGE@sixnetio.com>
17 18 svm_sc8xx powerpc mpc8xx - - John Zhan <zhanz@sinovee.com>
... ... @@ -456,27 +456,6 @@
456 456 #define SICR_ENET_CLKRT ((uint)0x00002c00)
457 457 #endif /* CONFIG_BSEIP */
458 458  
459   -/*** BSEIP **********************************************************/
460   -
461   -#ifdef CONFIG_FLAGADM
462   -/* Enet configuration for the FLAGADM */
463   -/* Enet on SCC2 */
464   -
465   -#define PROFF_ENET PROFF_SCC2
466   -#define CPM_CR_ENET CPM_CR_CH_SCC2
467   -#define SCC_ENET 1
468   -#define PA_ENET_RXD ((ushort)0x0004)
469   -#define PA_ENET_TXD ((ushort)0x0008)
470   -#define PA_ENET_TCLK ((ushort)0x0100)
471   -#define PA_ENET_RCLK ((ushort)0x0400)
472   -#define PB_ENET_TENA ((uint)0x00002000)
473   -#define PC_ENET_CLSN ((ushort)0x0040)
474   -#define PC_ENET_RENA ((ushort)0x0080)
475   -
476   -#define SICR_ENET_MASK ((uint)0x0000ff00)
477   -#define SICR_ENET_CLKRT ((uint)0x00003400)
478   -#endif /* CONFIG_FLAGADM */
479   -
480 459 /*** ELPT860 *********************************************************/
481 460  
482 461 #ifdef CONFIG_ELPT860
include/configs/FLAGADM.h
View file @ aec6f8c
1   -/*
2   - * (C) Copyright 2001
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -/*
9   - * board/config.h - configuration options, board specific
10   - */
11   -
12   -#ifndef __CONFIG_H
13   -#define __CONFIG_H
14   -
15   -/*
16   - * High Level Configuration Options
17   - * (easy to change)
18   - */
19   -
20   -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
21   -#define CONFIG_FLAGADM 1 /* ...on a FLAGA DM */
22   -#define CONFIG_8xx_GCLK_FREQ 48000000 /*48MHz*/
23   -
24   -#define CONFIG_SYS_TEXT_BASE 0x40000000
25   -
26   -#undef CONFIG_8xx_CONS_SMC1 /* Console is on SMC1 */
27   -#define CONFIG_8xx_CONS_SMC2 1
28   -#undef CONFIG_8xx_CONS_NONE
29   -
30   -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
31   -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
32   -
33   -#undef CONFIG_CLOCKS_IN_MHZ
34   -
35   -#if 0
36   -#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp"
37   -#define CONFIG_BOOTCOMMAND \
38   - "setenv bootargs root=/dev/ram ip=off panic=1;" \
39   - "bootm 40040000 400e0000"
40   -#else
41   -#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp panic=1"
42   -#define CONFIG_BOOTCOMMAND "bootp 0x400000; bootm 0x400000"
43   -#endif /* 0|1*/
44   -
45   -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
46   -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
47   -
48   -/*#define CONFIG_WATCHDOG*/ /* watchdog enabled */
49   -#undef CONFIG_WATCHDOG /* watchdog disabled */
50   -
51   -/*
52   - * BOOTP options
53   - */
54   -#define CONFIG_BOOTP_SUBNETMASK
55   -#define CONFIG_BOOTP_GATEWAY
56   -#define CONFIG_BOOTP_HOSTNAME
57   -#define CONFIG_BOOTP_BOOTPATH
58   -#define CONFIG_BOOTP_BOOTFILESIZE
59   -
60   -
61   -/*
62   - * Command line configuration.
63   - */
64   -
65   -#define CONFIG_CMD_BDI
66   -#define CONFIG_CMD_IMI
67   -#define CONFIG_CMD_CACHE
68   -#define CONFIG_CMD_MEMORY
69   -#define CONFIG_CMD_FLASH
70   -#define CONFIG_CMD_LOADB
71   -#define CONFIG_CMD_LOADS
72   -#define CONFIG_CMD_SAVEENV
73   -#define CONFIG_CMD_REGINFO
74   -#define CONFIG_CMD_IMMAP
75   -#define CONFIG_CMD_NET
76   -
77   -
78   -/*
79   - * Miscellaneous configurable options
80   - */
81   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
82   -#define CONFIG_SYS_PROMPT "EEG> " /* Monitor Command Prompt */
83   -#if defined(CONFIG_CMD_KGDB)
84   -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
85   -#else
86   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
87   -#endif
88   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
89   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
90   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
91   -
92   -#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
93   -#define CONFIG_SYS_MEMTEST_END 0x0f00000 /* 1 ... 15 MB in DRAM */
94   -
95   -#define CONFIG_SYS_LOAD_ADDR 0x40040000 /* default load address */
96   -
97   -/*
98   - * Low Level Configuration Settings
99   - * (address mappings, register initial values, etc.)
100   - * You should know what you are doing if you make changes here.
101   - */
102   -/*-----------------------------------------------------------------------
103   - * Internal Memory Mapped Register
104   - */
105   -#define CONFIG_SYS_IMMR 0xFF000000
106   -
107   -/*-----------------------------------------------------------------------
108   - * Definitions for initial stack pointer and data area (in DPRAM)
109   - */
110   -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
111   -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
112   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
113   -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
114   -
115   -/*-----------------------------------------------------------------------
116   - * Start addresses for the final memory configuration
117   - * (Set up by the startup code)
118   - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
119   - */
120   -#define CONFIG_SYS_SDRAM_BASE 0x00000000
121   -#define CONFIG_SYS_FLASH_BASE 0x40000000
122   -#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
123   -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
124   -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
125   -
126   -/*
127   - * For booting Linux, the board info and command line data
128   - * have to be in the first 8 MB of memory, since this is
129   - * the maximum mapped by the Linux kernel during initialization.
130   - */
131   -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
132   -
133   -/*-----------------------------------------------------------------------
134   - * FLASH organization
135   - */
136   -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
137   -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
138   -
139   -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
140   -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
141   -
142   -#define CONFIG_ENV_IS_IN_FLASH 1
143   -/* This is a litlebit wasteful, but one sector is 128kb and we have to
144   - * assigne a whole sector for the environment, so that we can safely
145   - * erase and write it without disturbing the boot sector
146   - */
147   -#define CONFIG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */
148   -#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
149   -
150   -/*-----------------------------------------------------------------------
151   - * Cache Configuration
152   - */
153   -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
154   -#if defined(CONFIG_CMD_KGDB)
155   -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
156   -#endif
157   -#define CONFIG_SYS_DELAYED_ICACHE 1 /* enable ICache not before
158   - * running in RAM.
159   - */
160   -
161   -/*-----------------------------------------------------------------------
162   - * SYPCR - System Protection Control 11-9
163   - * SYPCR can only be written once after reset!
164   - *-----------------------------------------------------------------------
165   - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
166   - */
167   -#ifdef CONFIG_WATCHDOG
168   -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
169   -#else
170   -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
171   -#endif
172   -
173   -/*-----------------------------------------------------------------------
174   - * SIUMCR - SIU Module Configuration 11-6
175   - *-----------------------------------------------------------------------
176   - * PCMCIA config., multi-function pin tri-state
177   - */
178   -#define CONFIG_SYS_PRE_SIUMCR (SIUMCR_DBGC11 | SIUMCR_MPRE | \
179   - SIUMCR_MLRC01 | SIUMCR_GB5E)
180   -#define CONFIG_SYS_SIUMCR (CONFIG_SYS_PRE_SIUMCR | SIUMCR_DLK)
181   -
182   -/*-----------------------------------------------------------------------
183   - * TBSCR - Time Base Status and Control 11-26
184   - *-----------------------------------------------------------------------
185   - * Clear Reference Interrupt Status, Timebase freezing enabled
186   - */
187   -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
188   -
189   -/*-----------------------------------------------------------------------
190   - * RTCSC - Real-Time Clock Status and Control Register 11-27
191   - *-----------------------------------------------------------------------
192   - */
193   -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
194   -
195   -/*-----------------------------------------------------------------------
196   - * PISCR - Periodic Interrupt Status and Control 11-31
197   - *-----------------------------------------------------------------------
198   - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
199   - */
200   -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
201   -
202   -/*-----------------------------------------------------------------------
203   - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
204   - *-----------------------------------------------------------------------
205   - * Reset PLL lock status sticky bit, timer expired status bit and timer
206   - * interrupt status bit miltiplier of 0x00b i.e. operation clock is
207   - * 4MHz * (0x00b+1) = 4MHz * 12 = 48MHz
208   - */
209   -#define CONFIG_SYS_PLPRCR (0x00b00000 | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
210   -
211   -/*-----------------------------------------------------------------------
212   - * SCCR - System Clock and reset Control Register 15-27
213   - *-----------------------------------------------------------------------
214   - * Set clock output, timebase and RTC source and divider,
215   - * power management and some other internal clocks
216   - */
217   -#define SCCR_MASK SCCR_EBDF11
218   -#define CONFIG_SYS_SCCR ( SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
219   - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
220   - SCCR_DFALCD00)
221   -
222   -#define CONFIG_SYS_DER 0
223   -
224   -/*
225   - * In the Flaga DM we have:
226   - * Flash on BR0/OR0/CS0a at 0x40000000
227   - * Display on BR1/OR1/CS1 at 0x20000000
228   - * SDRAM on BR2/OR2/CS2 at 0x00000000
229   - * Free BR3/OR3/CS3
230   - * DSP1 on BR4/OR4/CS4 at 0x80000000
231   - * DSP2 on BR5/OR5/CS5 at 0xa0000000
232   - *
233   - * For now we just configure the Flash and the SDRAM and leave the others
234   - * untouched.
235   -*/
236   -
237   -#define CONFIG_SYS_FLASH_PROTECTION 0
238   -
239   -#define FLASH_BASE0 0x40000000 /* FLASH bank #0 */
240   -
241   -/* used to re-map FLASH both when starting from SRAM or FLASH:
242   - * restrict access enough to keep SRAM working (if any)
243   - * but not too much to meddle with FLASH accesses
244   - */
245   -#define CONFIG_SYS_OR_AM 0xff000000 /* OR addr mask */
246   -#define CONFIG_SYS_OR_ATM 0x00006000
247   -
248   -/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
249   -#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | \
250   - OR_SCY_3_CLK | OR_TRLX | OR_EHTR )
251   -
252   -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_OR_AM | CONFIG_SYS_OR_ATM | CONFIG_SYS_OR_TIMING_FLASH)
253   -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0 & BR_BA_MSK) | BR_PS_16 | BR_V )
254   -
255   -/*
256   - * BR2 and OR2 (SDRAM)
257   - *
258   - */
259   -#define SDRAM_BASE2 0x00000000 /* SDRAM bank #0 */
260   -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
261   -
262   -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
263   -#define CONFIG_SYS_OR_TIMING_SDRAM ( 0x00000800 )
264   -
265   -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM)
266   -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2 & BR_BA_MSK) | BR_MS_UPMA | BR_V )
267   -
268   -#define CONFIG_SYS_BR2 CONFIG_SYS_BR2_PRELIM
269   -#define CONFIG_SYS_OR2 CONFIG_SYS_OR2_PRELIM
270   -
271   -/*
272   - * MAMR settings for SDRAM
273   - */
274   -#define CONFIG_SYS_MAMR_48_SDR (CONFIG_SYS_MAMR_PTA | MAMR_WLFA_1X | MAMR_RLFA_1X \
275   - | MAMR_G0CLA_A11)
276   -
277   -/*
278   - * Memory Periodic Timer Prescaler
279   - */
280   -
281   -/* periodic timer for refresh */
282   -#define CONFIG_SYS_MAMR_PTA 0x0F000000
283   -
284   -/*
285   - * BR4 and OR4 (DSP1)
286   - *
287   - * We do not wan't preliminary setup of the DSP, anyway we need the
288   - * UPMB setup correctly before we can access the DSP.
289   - *
290   -*/
291   -#define DSP_BASE 0x80000000
292   -
293   -#define CONFIG_SYS_OR4 ( OR_AM_MSK | OR_CSNT_SAM | OR_BI | OR_G5LS)
294   -#define CONFIG_SYS_BR4 ( (DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_UPMB | BR_V )
295   -
296   -#endif /* __CONFIG_H */