mvebu: Support Synology DS414

This adds support for the MV78230 based DS414 NAS by Synology. The relevant bits have been extracted from the 'synogpl-5004-armadaxp' package Synology kindly published, garnished with a fair amount of trial-and-error. Sadly, support is far from perfect. The major parts I have failed in are SATA and XHCI support. Details about these and some other things follow: Device Tree ----------- The device tree file armada-xp-synology-ds414.dts has been copied from Linux and enhanced by recent U-Boot specific changes to armada-xp-gp.dts. SATA Support ------------ There is a Marvell 88SX7042 controller attached to PCIe which is supported by Linux's sata_mv driver but sadly not U-Boot's sata_mv. I'm not sure if extending the latter to support PCI devices is worth the effort at all. Porting sata_mv from Linux exceeded my brain's capacities. :( XHCI Support ------------ There is an EtronTech EJ168A XHCI controller attached to PCIe which drives the two rear USB3 ports. After a bit of playing around I managed to get it recognized by xhci-pci, but never was able to access any devices attached to it. Enabling it in ds414 board config shows that it does not respond to commands for whatever reason. The (somewhat) bright side to it is that it is not even supported in Synology's customized U-Boot, but that also means nowhere to steal the relevant bits from. EHCI Support ------------ This seems functional after issuing 'usb start'. At least it detects USB storage devices, and IIRC reading from them was OK. OTOH Linux fails to register the controller if 'usb start' wasn't given before in U-Boot. According to Synology sources, this board seems to support USB device (gadget?) mode. Though I didn't play around with it. PCIe Support ------------ This is fine, but trying to gate the clocks of unused lanes will hang PCI enum. In addition to that, pci_mvebu seems not to support DM_PCI. DDR3 Training ------------- Marvell/Synology uses eight PUPs instead of four. Does not look like this is meant to be customized in mainline U-Boot at all. OTOH I have no idea what a "PUP" actually is. PEX Init -------- Synology uses different values than mainline U-Boot with this patch: pex_max_unit_get returns 2, pex_max_if_get returns 7 and max_serdes_lines is set to 7. Not changing this seems to not have an impact, although I'm not entirely sure it does not cause issues I am not aware of. Static Environment ------------------ This allows to boot stock Synology firmware at least. In order to be a little more flexible when it comes to booting custom kernels, do not only load zImage partition, but also rd.gz into memory. This way it is possible to use about 7MB for kernel with piggyback initramfs. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>

mvebu: Support Synology DS414
This adds support for the MV78230 based DS414 NAS by Synology. The relevant bits have been extracted from the 'synogpl-5004-armadaxp' package Synology kindly published, garnished with a fair amount of trial-and-error. Sadly, support is far from perfect. The major parts I have failed in are SATA and XHCI support. Details about these and some other things follow: Device Tree ----------- The device tree file armada-xp-synology-ds414.dts has been copied from Linux and enhanced by recent U-Boot specific changes to armada-xp-gp.dts. SATA Support ------------ There is a Marvell 88SX7042 controller attached to PCIe which is supported by Linux's sata_mv driver but sadly not U-Boot's sata_mv. I'm not sure if extending the latter to support PCI devices is worth the effort at all. Porting sata_mv from Linux exceeded my brain's capacities. :( XHCI Support ------------ There is an EtronTech EJ168A XHCI controller attached to PCIe which drives the two rear USB3 ports. After a bit of playing around I managed to get it recognized by xhci-pci, but never was able to access any devices attached to it. Enabling it in ds414 board config shows that it does not respond to commands for whatever reason. The (somewhat) bright side to it is that it is not even supported in Synology's customized U-Boot, but that also means nowhere to steal the relevant bits from. EHCI Support ------------ This seems functional after issuing 'usb start'. At least it detects USB storage devices, and IIRC reading from them was OK. OTOH Linux fails to register the controller if 'usb start' wasn't given before in U-Boot. According to Synology sources, this board seems to support USB device (gadget?) mode. Though I didn't play around with it. PCIe Support ------------ This is fine, but trying to gate the clocks of unused lanes will hang PCI enum. In addition to that, pci_mvebu seems not to support DM_PCI. DDR3 Training ------------- Marvell/Synology uses eight PUPs instead of four. Does not look like this is meant to be customized in mainline U-Boot at all. OTOH I have no idea what a "PUP" actually is. PEX Init -------- Synology uses different values than mainline U-Boot with this patch: pex_max_unit_get returns 2, pex_max_if_get returns 7 and max_serdes_lines is set to 7. Not changing this seems to not have an impact, although I'm not entirely sure it does not cause issues I am not aware of. Static Environment ------------------ This allows to boot stock Synology firmware at least. In order to be a little more flexible when it comes to booting custom kernels, do not only load zImage partition, but also rd.gz into memory. This way it is possible to use about 7MB for kernel with piggyback initramfs. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
Phil Sutter · Stefan Roese
1 parent 6202953df4
Showing 9 changed files with 731 additions and 2 deletions Side-by-side Diff
arch/arm/dts/Makefile
arch/arm/dts/armada-xp-synology-ds414.dts
arch/arm/mach-mvebu/Kconfig
arch/arm/mach-mvebu/serdes/axp/board_env_spec.h
board/Synology/ds414/Makefile
board/Synology/ds414/ds414.c
board/Synology/ds414/kwbimage.cfg
configs/ds414_defconfig
include/configs/ds414.h
@@ -51,7 +51,8 @@
 	armada-388-clearfog.dtb			\
 	armada-388-gp.dtb			\
 	armada-xp-gp.dtb			\
-	armada-xp-maxbcm.dtb
+	armada-xp-maxbcm.dtb			\
+	armada-xp-synology-ds414.dtb
  
 dtb-$(CONFIG_ARCH_UNIPHIER) += \
 	uniphier-ph1-ld4-ref.dtb \
+/*
+ * Device Tree file for Synology DS414
+ *
+ * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf1000000 (instead of the old 0xd0000000).
+ * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
+ * bootloaders provided by Marvell. It is used in recent versions of
+ * DSM software provided by Synology. Nonetheless, some earlier boards
+ * were delivered with an older version of u-boot that left internal
+ * registers mapped at 0xd0000000. If you have such a device you will
+ * not be able to directly boot a kernel based on this Device Tree. In
+ * that case, the preferred solution is to update your bootloader (e.g.
+ * by upgrading to latest version of DSM, or building a new one and
+ * installing it from u-boot prompt) or adjust the Devive Tree
+ * (s/0xf1000000/0xd0000000/ in 'ranges' below).
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-xp-mv78230.dtsi"
+
+/ {
+	model = "Synology DS414";
+	compatible = "synology,ds414", "marvell,armadaxp-mv78230",
+		     "marvell,armadaxp", "marvell,armada-370-xp";
+
+	chosen {
+		bootargs = "console=ttyS0,115200 earlyprintk";
+		stdout-path = &uart0;
+	};
+
+	aliases {
+		spi0 = &spi0;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0 0x00000000 0 0x40000000>; /* 1GB */
+	};
+
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
+			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
+
+		pcie-controller {
+			status = "okay";
+
+			/*
+			 * Connected to Marvell 88SX7042 SATA-II controller
+			 * handling the four disks.
+			 */
+			pcie@1,0 {
+				/* Port 0, Lane 0 */
+				status = "okay";
+			};
+
+			/*
+			 * Connected to EtronTech EJ168A XHCI controller
+			 * providing the two rear USB 3.0 ports.
+			 */
+			pcie@5,0 {
+				/* Port 1, Lane 0 */
+				status = "okay";
+			};
+		};
+
+		internal-regs {
+
+			/* RTC is provided by Seiko S-35390A below */
+			rtc@10300 {
+				status = "disabled";
+			};
+
+			spi0: spi@10600 {
+				status = "okay";
+				u-boot,dm-pre-reloc;
+
+				spi-flash@0 {
+					u-boot,dm-pre-reloc;
+					#address-cells = <1>;
+					#size-cells = <1>;
+					compatible = "micron,n25q064";
+					reg = <0>; /* Chip select 0 */
+					spi-max-frequency = <20000000>;
+
+					/*
+					 * Warning!
+					 *
+					 * Synology u-boot uses its compiled-in environment
+					 * and it seems Synology did not care to change u-boot
+					 * default configuration in order to allow saving a
+					 * modified environment at a sensible location. So,
+					 * if you do a 'saveenv' under u-boot, your modified
+					 * environment will be saved at 1MB after the start
+					 * of the flash, i.e. in the middle of the uImage.
+					 * For that reason, it is strongly advised not to
+					 * change the default environment, unless you know
+					 * what you are doing.
+					 */
+					partition@00000000 { /* u-boot */
+						label = "RedBoot";
+						reg = <0x00000000 0x000d0000>; /* 832KB */
+					};
+
+					partition@000c0000 { /* uImage */
+						label = "zImage";
+						reg = <0x000d0000 0x002d0000>; /* 2880KB */
+					};
+
+					partition@003a0000 { /* uInitramfs */
+						label = "rd.gz";
+						reg = <0x003a0000 0x00430000>; /* 4250KB */
+					};
+
+					partition@007d0000 { /* MAC address and serial number */
+						label = "vendor";
+						reg = <0x007d0000 0x00010000>; /* 64KB */
+					};
+
+					partition@007e0000 {
+						label = "RedBoot config";
+						reg = <0x007e0000 0x00010000>; /* 64KB */
+					};
+
+					partition@007f0000 {
+						label = "FIS directory";
+						reg = <0x007f0000 0x00010000>; /* 64KB */
+					};
+				};
+			};
+
+			i2c@11000 {
+				clock-frequency = <400000>;
+				status = "okay";
+
+				s35390a: s35390a@30 {
+					 compatible = "sii,s35390a";
+					 reg = <0x30>;
+				};
+			};
+
+			/* Connected to a header on device's PCB. This
+			 * provides the main console for the device.
+			 *
+			 * Warning: the device may not boot with a 3.3V
+			 * USB-serial converter connected when the power
+			 * button is pressed. The converter needs to be
+			 * connected a few seconds after pressing the
+			 * power button. This is possibly due to UART0_TXD
+			 * pin being sampled at reset (bit 0 of SAR).
+			 */
+			serial@12000 {
+				status = "okay";
+				u-boot,dm-pre-reloc;
+			};
+
+			/* Connected to a Microchip PIC16F883 for power control */
+			serial@12100 {
+				status = "okay";
+			};
+
+			poweroff@12100 {
+				compatible = "synology,power-off";
+				reg = <0x12100 0x100>;
+				clocks = <&coreclk 0>;
+			};
+
+			/* Front USB 2.0 port */
+			usb@50000 {
+				status = "okay";
+			};
+
+			mdio {
+				phy0: ethernet-phy@0 { /* Marvell 88E1512 */
+					reg = <0>;
+				};
+
+				phy1: ethernet-phy@1 { /* Marvell 88E1512 */
+					reg = <1>;
+				};
+			};
+
+			ethernet@70000 {
+				status = "okay";
+				pinctrl-0 = <&ge0_rgmii_pins>;
+				pinctrl-names = "default";
+				phy = <&phy1>;
+				phy-mode = "rgmii-id";
+			};
+
+			ethernet@74000 {
+				pinctrl-0 = <&ge1_rgmii_pins>;
+				pinctrl-names = "default";
+				status = "okay";
+				phy = <&phy0>;
+				phy-mode = "rgmii-id";
+			};
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin
+			     &sata3_pwr_pin &sata4_pwr_pin>;
+		pinctrl-names = "default";
+
+		sata1_regulator: sata1-regulator {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "SATA1 Power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			startup-delay-us = <2000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+		};
+
+		sata2_regulator: sata2-regulator {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			regulator-name = "SATA2 Power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			startup-delay-us = <4000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+		};
+
+		sata3_regulator: sata3-regulator {
+			compatible = "regulator-fixed";
+			reg = <3>;
+			regulator-name = "SATA3 Power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			startup-delay-us = <6000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+		};
+
+		sata4_regulator: sata4-regulator {
+			compatible = "regulator-fixed";
+			reg = <4>;
+			regulator-name = "SATA4 Power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			startup-delay-us = <8000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&pinctrl {
+	sata1_pwr_pin: sata1-pwr-pin {
+		marvell,pins = "mpp42";
+		marvell,function = "gpio";
+	};
+
+	sata2_pwr_pin: sata2-pwr-pin {
+		marvell,pins = "mpp44";
+		marvell,function = "gpio";
+	};
+
+	sata3_pwr_pin: sata3-pwr-pin {
+		marvell,pins = "mpp45";
+		marvell,function = "gpio";
+	};
+
+	sata4_pwr_pin: sata4-pwr-pin {
+		marvell,pins = "mpp46";
+		marvell,function = "gpio";
+	};
+
+	sata1_pres_pin: sata1-pres-pin {
+		marvell,pins = "mpp34";
+		marvell,function = "gpio";
+	};
+
+	sata2_pres_pin: sata2-pres-pin {
+		marvell,pins = "mpp35";
+		marvell,function = "gpio";
+	};
+
+	sata3_pres_pin: sata3-pres-pin {
+		marvell,pins = "mpp40";
+		marvell,function = "gpio";
+	};
+
+	sata4_pres_pin: sata4-pres-pin {
+		marvell,pins = "mpp41";
+		marvell,function = "gpio";
+	};
+
+	syno_id_bit0_pin: syno-id-bit0-pin {
+		marvell,pins = "mpp26";
+		marvell,function = "gpio";
+	};
+
+	syno_id_bit1_pin: syno-id-bit1-pin {
+		marvell,pins = "mpp28";
+		marvell,function = "gpio";
+	};
+
+	syno_id_bit2_pin: syno-id-bit2-pin {
+		marvell,pins = "mpp29";
+		marvell,function = "gpio";
+	};
+
+	fan1_alarm_pin: fan1-alarm-pin {
+		marvell,pins = "mpp33";
+		marvell,function = "gpio";
+	};
+
+	fan2_alarm_pin: fan2-alarm-pin {
+		marvell,pins = "mpp32";
+		marvell,function = "gpio";
+	};
+};
@@ -38,6 +38,10 @@
 	bool "Support db-mv784mp-gp"
 	select MV78460
  
+config TARGET_DS414
+	bool "Support Synology DS414"
+	select MV78230
+
 config TARGET_MAXBCM
 	bool "Support maxbcm"
 	select MV78460
  
  
@@ -48,18 +52,21 @@
 	default "clearfog" if TARGET_CLEARFOG
 	default "db-88f6820-gp" if TARGET_DB_88F6820_GP
 	default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
+	default "ds414" if TARGET_DS414
 	default "maxbcm" if TARGET_MAXBCM
  
 config SYS_CONFIG_NAME
 	default "clearfog" if TARGET_CLEARFOG
 	default "db-88f6820-gp" if TARGET_DB_88F6820_GP
 	default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
+	default "ds414" if TARGET_DS414
 	default "maxbcm" if TARGET_MAXBCM
  
 config SYS_VENDOR
 	default "Marvell" if TARGET_DB_MV784MP_GP
 	default "Marvell" if TARGET_DB_88F6820_GP
 	default "solidrun" if TARGET_CLEARFOG
+	default "Synology" if TARGET_DS414
  
 config SYS_SOC
 	default "mvebu"
@@ -44,7 +44,7 @@
 #define DB_784MP_GP_ID			(RD_78460_SERVER_REV2_ID + 1)
 #define RD_78460_CUSTOMER_ID		(DB_784MP_GP_ID + 1)
 #define MV_MAX_BOARD_ID			(RD_78460_CUSTOMER_ID + 1)
-#define INVALID_BAORD_ID		0xFFFFFFFF
+#define INVALID_BOARD_ID		0xFFFFFFFF
  
 /* Sample at Reset */
 #define MPP_SAMPLE_AT_RESET(id)		(0x18230 + (id * 4))
+#
+# Copyright (C) 2015 Phil Sutter <phil@nwl.cc>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y :=	ds414.o
+/*
+ *
+ * Copyright (C) 2015 Phil Sutter <phil@nwl.cc>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <linux/mbus.h>
+
+#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
+#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
+#include "../arch/arm/mach-mvebu/serdes/axp/board_env_spec.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* GPP and MPP settings as found in mvBoardEnvSpec.c of Synology's U-Boot */
+
+#define DS414_GPP_OUT_VAL_LOW		(BIT(25) | BIT(30))
+#define DS414_GPP_OUT_VAL_MID		(BIT(10) | BIT(15))
+#define DS414_GPP_OUT_VAL_HIGH		(0)
+
+#define DS414_GPP_OUT_POL_LOW		(0)
+#define DS414_GPP_OUT_POL_MID		(0)
+#define DS414_GPP_OUT_POL_HIGH		(0)
+
+#define DS414_GPP_OUT_ENA_LOW		(~(BIT(25) | BIT(30)))
+#define DS414_GPP_OUT_ENA_MID		(~(BIT(10) | BIT(12) | \
+					   BIT(13) | BIT(14) | BIT(15)))
+#define DS414_GPP_OUT_ENA_HIGH		(~0)
+
+static const u32 ds414_mpp_control[] = {
+	0x11111111,
+	0x22221111,
+	0x22222222,
+	0x00000000,
+	0x11110000,
+	0x00004000,
+	0x00000000,
+	0x00000000,
+	0x00000000
+};
+
+/* DDR3 static MC configuration */
+
+/* 1G_v1 (4x2Gbits) adapted by DS414 */
+MV_DRAM_MC_INIT syno_ddr3_b0_667_1g_v1[MV_MAX_DDR3_STATIC_SIZE] = {
+	{0x00001400, 0x73014A28},	/*DDR SDRAM Configuration Register */
+	{0x00001404, 0x30000800},	/*Dunit Control Low Register */
+	{0x00001408, 0x44148887},	/*DDR SDRAM Timing (Low) Register */
+	{0x0000140C, 0x3AD83FEA},	/*DDR SDRAM Timing (High) Register */
+
+	{0x00001410, 0x14000000},	/*DDR SDRAM Address Control Register */
+
+	{0x00001414, 0x00000000},	/*DDR SDRAM Open Pages Control Register */
+	{0x00001418, 0x00000e00},	/*DDR SDRAM Operation Register */
+	{0x00001420, 0x00000004},	/*DDR SDRAM Extended Mode Register */
+	{0x00001424, 0x0000F3FF},	/*Dunit Control High Register */
+	{0x00001428, 0x000F8830},	/*Dunit Control High Register */
+	{0x0000142C, 0x054C36F4},	/*Dunit Control High Register */
+	{0x0000147C, 0x0000C671},
+
+	{0x000014a0, 0x00000001},
+	{0x000014a8, 0x00000100},	/*2:1 */
+	{0x00020220, 0x00000006},
+
+	{0x00001494, 0x00010000},	/*DDR SDRAM ODT Control (Low) Register */
+	{0x00001498, 0x00000000},	/*DDR SDRAM ODT Control (High) Register */
+	{0x0000149C, 0x00000001},	/*DDR Dunit ODT Control Register */
+
+	{0x000014C0, 0x192424C9},	/* DRAM address and Control Driving Strenght  */
+	{0x000014C4, 0x0AAA24C9},	/* DRAM Data and DQS Driving Strenght  */
+
+	{0x000200e8, 0x3FFF0E01},	/* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence*/
+	{0x00020184, 0x3FFFFFE0},	/* DO NOT Modify - Close fast path Window to - 2G */
+
+	{0x0001504, 0x3FFFFFE1},	/* CS0 Size */
+	{0x000150C, 0x00000000},	/* CS1 Size */
+	{0x0001514, 0x00000000},	/* CS2 Size */
+	{0x000151C, 0x00000000},	/* CS3 Size */
+
+	{0x00001538, 0x00000009},	/*Read Data Sample Delays Register */
+	{0x0000153C, 0x00000009},	/*Read Data Ready Delay Register */
+
+	{0x000015D0, 0x00000650},	/*MR0 */
+	{0x000015D4, 0x00000044},	/*MR1 */
+	{0x000015D8, 0x00000010},	/*MR2 */
+	{0x000015DC, 0x00000000},	/*MR3 */
+
+	{0x000015E4, 0x00203c18},	/*ZQC Configuration Register */
+	{0x000015EC, 0xF800A225},	/*DDR PHY */
+
+	{0x0, 0x0}
+};
+
+MV_DRAM_MODES ds414_ddr_modes[MV_DDR3_MODES_NUMBER] = {
+	{"ds414_1333-667",   0x3, 0x5, 0x0, A0, syno_ddr3_b0_667_1g_v1,  NULL},
+};
+
+extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
+
+MV_BIN_SERDES_CFG ds414_serdes_cfg[] = {
+	{ MV_PEX_ROOT_COMPLEX, 0x02011111, 0x00000000,
+	  { PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_DISABLED,
+	    PEX_BUS_DISABLED },
+	  0x0040, serdes_change_m_phy
+	}
+};
+
+MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
+{
+	return &ds414_ddr_modes[0];
+}
+
+MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
+{
+	return &ds414_serdes_cfg[0];
+}
+
+u8 board_sat_r_get(u8 dev_num, u8 reg)
+{
+	return (0x1 << 1 | 1);
+}
+
+int board_early_init_f(void)
+{
+	int i;
+
+	/* Set GPP Out value */
+	reg_write(GPP_DATA_OUT_REG(0), DS414_GPP_OUT_VAL_LOW);
+	reg_write(GPP_DATA_OUT_REG(1), DS414_GPP_OUT_VAL_MID);
+	reg_write(GPP_DATA_OUT_REG(2), DS414_GPP_OUT_VAL_HIGH);
+
+	/* set GPP polarity */
+	reg_write(GPP_DATA_IN_POL_REG(0), DS414_GPP_OUT_POL_LOW);
+	reg_write(GPP_DATA_IN_POL_REG(1), DS414_GPP_OUT_POL_MID);
+	reg_write(GPP_DATA_IN_POL_REG(2), DS414_GPP_OUT_POL_HIGH);
+
+	/* Set GPP Out Enable */
+	reg_write(GPP_DATA_OUT_EN_REG(0), DS414_GPP_OUT_ENA_LOW);
+	reg_write(GPP_DATA_OUT_EN_REG(1), DS414_GPP_OUT_ENA_MID);
+	reg_write(GPP_DATA_OUT_EN_REG(2), DS414_GPP_OUT_ENA_HIGH);
+
+	for (i = 0; i < ARRAY_SIZE(ds414_mpp_control); i++)
+		reg_write(MPP_CONTROL_REG(i), ds414_mpp_control[i]);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	u32 pwr_mng_ctrl_reg;
+
+	/* Adress of boot parameters */
+	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+	/* Gate unused clocks
+	 *
+	 * Note: Disabling unused PCIe lanes will hang PCI bus scan.
+	 *       Once this is resolved, bits 10-12, 26 and 27 can be
+	 *       unset here as well.
+	 */
+	pwr_mng_ctrl_reg = reg_read(POWER_MNG_CTRL_REG);
+	pwr_mng_ctrl_reg &= ~(BIT(0));				/* Audio */
+	pwr_mng_ctrl_reg &= ~(BIT(1) | BIT(2));			/* GE3, GE2 */
+	pwr_mng_ctrl_reg &= ~(BIT(14) | BIT(15));		/* SATA0 link and core */
+	pwr_mng_ctrl_reg &= ~(BIT(16));				/* LCD */
+	pwr_mng_ctrl_reg &= ~(BIT(17));				/* SDIO */
+	pwr_mng_ctrl_reg &= ~(BIT(19) | BIT(20));		/* USB1 and USB2 */
+	pwr_mng_ctrl_reg &= ~(BIT(29) | BIT(30));		/* SATA1 link and core */
+	reg_write(POWER_MNG_CTRL_REG, pwr_mng_ctrl_reg);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: DS414\n");
+
+	return 0;
+}
+#
+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
+#
+
+# Armada XP uses version 1 image format
+VERSION		1
+
+# Boot Media configurations
+BOOT_FROM	spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
+CONFIG_ARM=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_DS414=y
+CONFIG_DEFAULT_DEVICE_TREE="armada-xp-synology-ds414"
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CONFIG_SYNOLOGY_DS414_H
+#define _CONFIG_SYNOLOGY_DS414_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/*
+ * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
+ * for DDR ECC byte filling in the SPL before loading the main
+ * U-Boot into it.
+ */
+#define	CONFIG_SYS_TEXT_BASE	0x00800000
+#define CONFIG_SYS_TCLK		250000000	/* 250MHz */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_TFTPPUT
+#define CONFIG_CMD_TIME
+#define CONFIG_CMD_USB
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
+#define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
+#define CONFIG_SYS_I2C_SLAVE		0x0
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* SPI NOR flash default params, used by sf commands */
+#define CONFIG_SF_DEFAULT_SPEED		1000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET		0x7E0000   /* RedBoot config partition in DTS */
+#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE		(64 << 10) /* 64KiB sectors */
+
+#define CONFIG_PHY_MARVELL		/* there is a marvell phy */
+#define CONFIG_PHY_ADDR			{ 0x1, 0x0 }
+#define CONFIG_SYS_NETA_INTERFACE_TYPE	PHY_INTERFACE_MODE_RGMII
+
+#define CONFIG_SYS_ALT_MEMTEST
+
+/* PCIe support */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PCI_ENUM
+#define CONFIG_PCI_MVEBU
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
+/* USB/EHCI/XHCI configuration */
+
+#define CONFIG_DM_USB
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+/* FIXME: broken XHCI support
+ * Below defines should enable support for the two rear USB3 ports. Sadly, this
+ * does not work because:
+ * - xhci-pci seems to not support DM_USB, so with that enabled it is not
+ *   found.
+ * - USB init fails, controller does not respond in time */
+#if 0
+#undef CONFIG_DM_USB
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_PCI
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#endif
+
+#if !defined(CONFIG_USB_XHCI)
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MARVELL
+#define CONFIG_EHCI_IS_TDI
+#endif
+
+/* why is this only defined in mv-common.h if CONFIG_DM is undefined? */
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+#define CONFIG_SUPPORT_VFAT
+#define CONFIG_SYS_MVFS
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * Memory layout while starting into the bin_hdr via the
+ * BootROM:
+ *
+ * 0x4000.4000 - 0x4003.4000	headers space (192KiB)
+ * 0x4000.4030			bin_hdr start address
+ * 0x4003.4000 - 0x4004.7c00	BootROM memory allocations (15KiB)
+ * 0x4007.fffc			BootROM stack top
+ *
+ * The address space between 0x4007.fffc and 0x400f.fff is not locked in
+ * L2 cache thus cannot be used.
+ */
+
+/* SPL */
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE		0x40004030
+#define CONFIG_SPL_MAX_SIZE		((128 << 10) - 0x4030)
+
+#define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + (128 << 10))
+#define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+
+/* SPL related SPI defines */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS		0
+#define CONFIG_SPL_SPI_CS		0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x24000
+
+/* DS414 bus width is 32bits */
+#define CONFIG_DDR_32BIT
+
+/* Use random ethernet address if not configured */
+#define CONFIG_LIB_RAND
+#define CONFIG_NET_RANDOM_ETHADDR
+
+/* Default Environment */
+#define CONFIG_BOOTCOMMAND	"sf read ${loadaddr} 0xd0000 0x700000; bootm"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200"
+#define CONFIG_LOADADDR		0x80000
+#undef CONFIG_PREBOOT		/* override preboot for USB and SPI flash init */
+#define CONFIG_PREBOOT		"usb start; sf probe"
+
+#endif /* _CONFIG_SYNOLOGY_DS414_H */
...	...	@@ -51,7 +51,8 @@
51	51	armada-388-clearfog.dtb \
52	52	armada-388-gp.dtb \
53	53	armada-xp-gp.dtb \
54		- armada-xp-maxbcm.dtb
	54	+ armada-xp-maxbcm.dtb \
	55	+ armada-xp-synology-ds414.dtb
55	56
56	57	dtb-$(CONFIG_ARCH_UNIPHIER) += \
57	58	uniphier-ph1-ld4-ref.dtb \
	1	+/*
	2	+ * Device Tree file for Synology DS414
	3	+ *
	4	+ * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
	5	+ *
	6	+ * This program is free software; you can redistribute it and/or
	7	+ * modify it under the terms of the GNU General Public License
	8	+ * as published by the Free Software Foundation; either version
	9	+ * 2 of the License, or (at your option) any later version.
	10	+ *
	11	+ * Note: this Device Tree assumes that the bootloader has remapped the
	12	+ * internal registers to 0xf1000000 (instead of the old 0xd0000000).
	13	+ * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
	14	+ * bootloaders provided by Marvell. It is used in recent versions of
	15	+ * DSM software provided by Synology. Nonetheless, some earlier boards
	16	+ * were delivered with an older version of u-boot that left internal
	17	+ * registers mapped at 0xd0000000. If you have such a device you will
	18	+ * not be able to directly boot a kernel based on this Device Tree. In
	19	+ * that case, the preferred solution is to update your bootloader (e.g.
	20	+ * by upgrading to latest version of DSM, or building a new one and
	21	+ * installing it from u-boot prompt) or adjust the Devive Tree
	22	+ * (s/0xf1000000/0xd0000000/ in 'ranges' below).
	23	+ */
	24	+
	25	+/dts-v1/;
	26	+
	27	+#include <dt-bindings/input/input.h>
	28	+#include <dt-bindings/gpio/gpio.h>
	29	+#include "armada-xp-mv78230.dtsi"
	30	+
	31	+/ {
	32	+ model = "Synology DS414";
	33	+ compatible = "synology,ds414", "marvell,armadaxp-mv78230",
	34	+ "marvell,armadaxp", "marvell,armada-370-xp";
	35	+
	36	+ chosen {
	37	+ bootargs = "console=ttyS0,115200 earlyprintk";
	38	+ stdout-path = &uart0;
	39	+ };
	40	+
	41	+ aliases {
	42	+ spi0 = &spi0;
	43	+ };
	44	+
	45	+ memory {
	46	+ device_type = "memory";
	47	+ reg = <0 0x00000000 0 0x40000000>; /* 1GB */
	48	+ };
	49	+
	50	+ soc {
	51	+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
	52	+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
	53	+
	54	+ pcie-controller {
	55	+ status = "okay";
	56	+
	57	+ /*
	58	+ * Connected to Marvell 88SX7042 SATA-II controller
	59	+ * handling the four disks.
	60	+ */
	61	+ pcie@1,0 {
	62	+ /* Port 0, Lane 0 */
	63	+ status = "okay";
	64	+ };
	65	+
	66	+ /*
	67	+ * Connected to EtronTech EJ168A XHCI controller
	68	+ * providing the two rear USB 3.0 ports.
	69	+ */
	70	+ pcie@5,0 {
	71	+ /* Port 1, Lane 0 */
	72	+ status = "okay";
	73	+ };
	74	+ };
	75	+
	76	+ internal-regs {
	77	+
	78	+ /* RTC is provided by Seiko S-35390A below */
	79	+ rtc@10300 {
	80	+ status = "disabled";
	81	+ };
	82	+
	83	+ spi0: spi@10600 {
	84	+ status = "okay";
	85	+ u-boot,dm-pre-reloc;
	86	+
	87	+ spi-flash@0 {
	88	+ u-boot,dm-pre-reloc;
	89	+ #address-cells = <1>;
	90	+ #size-cells = <1>;
	91	+ compatible = "micron,n25q064";
	92	+ reg = <0>; /* Chip select 0 */
	93	+ spi-max-frequency = <20000000>;
	94	+
	95	+ /*
	96	+ * Warning!
	97	+ *
	98	+ * Synology u-boot uses its compiled-in environment
	99	+ * and it seems Synology did not care to change u-boot
	100	+ * default configuration in order to allow saving a
	101	+ * modified environment at a sensible location. So,
	102	+ * if you do a 'saveenv' under u-boot, your modified
	103	+ * environment will be saved at 1MB after the start
	104	+ * of the flash, i.e. in the middle of the uImage.
	105	+ * For that reason, it is strongly advised not to
	106	+ * change the default environment, unless you know
	107	+ * what you are doing.
	108	+ */
	109	+ partition@00000000 { /* u-boot */
	110	+ label = "RedBoot";
	111	+ reg = <0x00000000 0x000d0000>; /* 832KB */
	112	+ };
	113	+
	114	+ partition@000c0000 { /* uImage */
	115	+ label = "zImage";
	116	+ reg = <0x000d0000 0x002d0000>; /* 2880KB */
	117	+ };
	118	+
	119	+ partition@003a0000 { /* uInitramfs */
	120	+ label = "rd.gz";
	121	+ reg = <0x003a0000 0x00430000>; /* 4250KB */
	122	+ };
	123	+
	124	+ partition@007d0000 { /* MAC address and serial number */
	125	+ label = "vendor";
	126	+ reg = <0x007d0000 0x00010000>; /* 64KB */
	127	+ };
	128	+
	129	+ partition@007e0000 {
	130	+ label = "RedBoot config";
	131	+ reg = <0x007e0000 0x00010000>; /* 64KB */
	132	+ };
	133	+
	134	+ partition@007f0000 {
	135	+ label = "FIS directory";
	136	+ reg = <0x007f0000 0x00010000>; /* 64KB */
	137	+ };
	138	+ };
	139	+ };
	140	+
	141	+ i2c@11000 {
	142	+ clock-frequency = <400000>;
	143	+ status = "okay";
	144	+
	145	+ s35390a: s35390a@30 {
	146	+ compatible = "sii,s35390a";
	147	+ reg = <0x30>;
	148	+ };
	149	+ };
	150	+
	151	+ /* Connected to a header on device's PCB. This
	152	+ * provides the main console for the device.
	153	+ *
	154	+ * Warning: the device may not boot with a 3.3V
	155	+ * USB-serial converter connected when the power
	156	+ * button is pressed. The converter needs to be
	157	+ * connected a few seconds after pressing the
	158	+ * power button. This is possibly due to UART0_TXD
	159	+ * pin being sampled at reset (bit 0 of SAR).
	160	+ */
	161	+ serial@12000 {
	162	+ status = "okay";
	163	+ u-boot,dm-pre-reloc;
	164	+ };
	165	+
	166	+ /* Connected to a Microchip PIC16F883 for power control */
	167	+ serial@12100 {
	168	+ status = "okay";
	169	+ };
	170	+
	171	+ poweroff@12100 {
	172	+ compatible = "synology,power-off";
	173	+ reg = <0x12100 0x100>;
	174	+ clocks = <&coreclk 0>;
	175	+ };
	176	+
	177	+ /* Front USB 2.0 port */
	178	+ usb@50000 {
	179	+ status = "okay";
	180	+ };
	181	+
	182	+ mdio {
	183	+ phy0: ethernet-phy@0 { /* Marvell 88E1512 */
	184	+ reg = <0>;
	185	+ };
	186	+
	187	+ phy1: ethernet-phy@1 { /* Marvell 88E1512 */
	188	+ reg = <1>;
	189	+ };
	190	+ };
	191	+
	192	+ ethernet@70000 {
	193	+ status = "okay";
	194	+ pinctrl-0 = <&ge0_rgmii_pins>;
	195	+ pinctrl-names = "default";
	196	+ phy = <&phy1>;
	197	+ phy-mode = "rgmii-id";
	198	+ };
	199	+
	200	+ ethernet@74000 {
	201	+ pinctrl-0 = <&ge1_rgmii_pins>;
	202	+ pinctrl-names = "default";
	203	+ status = "okay";
	204	+ phy = <&phy0>;
	205	+ phy-mode = "rgmii-id";
	206	+ };
	207	+ };
	208	+ };
	209	+
	210	+ regulators {
	211	+ compatible = "simple-bus";
	212	+ #address-cells = <1>;
	213	+ #size-cells = <0>;
	214	+ pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin
	215	+ &sata3_pwr_pin &sata4_pwr_pin>;
	216	+ pinctrl-names = "default";
	217	+
	218	+ sata1_regulator: sata1-regulator {
	219	+ compatible = "regulator-fixed";
	220	+ reg = <1>;
	221	+ regulator-name = "SATA1 Power";
	222	+ regulator-min-microvolt = <5000000>;
	223	+ regulator-max-microvolt = <5000000>;
	224	+ startup-delay-us = <2000000>;
	225	+ enable-active-high;
	226	+ regulator-always-on;
	227	+ regulator-boot-on;
	228	+ gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
	229	+ };
	230	+
	231	+ sata2_regulator: sata2-regulator {
	232	+ compatible = "regulator-fixed";
	233	+ reg = <2>;
	234	+ regulator-name = "SATA2 Power";
	235	+ regulator-min-microvolt = <5000000>;
	236	+ regulator-max-microvolt = <5000000>;
	237	+ startup-delay-us = <4000000>;
	238	+ enable-active-high;
	239	+ regulator-always-on;
	240	+ regulator-boot-on;
	241	+ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
	242	+ };
	243	+
	244	+ sata3_regulator: sata3-regulator {
	245	+ compatible = "regulator-fixed";
	246	+ reg = <3>;
	247	+ regulator-name = "SATA3 Power";
	248	+ regulator-min-microvolt = <5000000>;
	249	+ regulator-max-microvolt = <5000000>;
	250	+ startup-delay-us = <6000000>;
	251	+ enable-active-high;
	252	+ regulator-always-on;
	253	+ regulator-boot-on;
	254	+ gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
	255	+ };
	256	+
	257	+ sata4_regulator: sata4-regulator {
	258	+ compatible = "regulator-fixed";
	259	+ reg = <4>;
	260	+ regulator-name = "SATA4 Power";
	261	+ regulator-min-microvolt = <5000000>;
	262	+ regulator-max-microvolt = <5000000>;
	263	+ startup-delay-us = <8000000>;
	264	+ enable-active-high;
	265	+ regulator-always-on;
	266	+ regulator-boot-on;
	267	+ gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
	268	+ };
	269	+ };
	270	+};
	271	+
	272	+&pinctrl {
	273	+ sata1_pwr_pin: sata1-pwr-pin {
	274	+ marvell,pins = "mpp42";
	275	+ marvell,function = "gpio";
	276	+ };
	277	+
	278	+ sata2_pwr_pin: sata2-pwr-pin {
	279	+ marvell,pins = "mpp44";
	280	+ marvell,function = "gpio";
	281	+ };
	282	+
	283	+ sata3_pwr_pin: sata3-pwr-pin {
	284	+ marvell,pins = "mpp45";
	285	+ marvell,function = "gpio";
	286	+ };
	287	+
	288	+ sata4_pwr_pin: sata4-pwr-pin {
	289	+ marvell,pins = "mpp46";
	290	+ marvell,function = "gpio";
	291	+ };
	292	+
	293	+ sata1_pres_pin: sata1-pres-pin {
	294	+ marvell,pins = "mpp34";
	295	+ marvell,function = "gpio";
	296	+ };
	297	+
	298	+ sata2_pres_pin: sata2-pres-pin {
	299	+ marvell,pins = "mpp35";
	300	+ marvell,function = "gpio";
	301	+ };
	302	+
	303	+ sata3_pres_pin: sata3-pres-pin {
	304	+ marvell,pins = "mpp40";
	305	+ marvell,function = "gpio";
	306	+ };
	307	+
	308	+ sata4_pres_pin: sata4-pres-pin {
	309	+ marvell,pins = "mpp41";
	310	+ marvell,function = "gpio";
	311	+ };
	312	+
	313	+ syno_id_bit0_pin: syno-id-bit0-pin {
	314	+ marvell,pins = "mpp26";
	315	+ marvell,function = "gpio";
	316	+ };
	317	+
	318	+ syno_id_bit1_pin: syno-id-bit1-pin {
	319	+ marvell,pins = "mpp28";
	320	+ marvell,function = "gpio";
	321	+ };
	322	+
	323	+ syno_id_bit2_pin: syno-id-bit2-pin {
	324	+ marvell,pins = "mpp29";
	325	+ marvell,function = "gpio";
	326	+ };
	327	+
	328	+ fan1_alarm_pin: fan1-alarm-pin {
	329	+ marvell,pins = "mpp33";
	330	+ marvell,function = "gpio";
	331	+ };
	332	+
	333	+ fan2_alarm_pin: fan2-alarm-pin {
	334	+ marvell,pins = "mpp32";
	335	+ marvell,function = "gpio";
	336	+ };
	337	+};
...	...	@@ -38,6 +38,10 @@
38	38	bool "Support db-mv784mp-gp"
39	39	select MV78460
40	40
	41	+config TARGET_DS414
	42	+ bool "Support Synology DS414"
	43	+ select MV78230
	44	+
41	45	config TARGET_MAXBCM
42	46	bool "Support maxbcm"
43	47	select MV78460
44	48
45	49
...	...	@@ -48,18 +52,21 @@
48	52	default "clearfog" if TARGET_CLEARFOG
49	53	default "db-88f6820-gp" if TARGET_DB_88F6820_GP
50	54	default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
	55	+ default "ds414" if TARGET_DS414
51	56	default "maxbcm" if TARGET_MAXBCM
52	57
53	58	config SYS_CONFIG_NAME
54	59	default "clearfog" if TARGET_CLEARFOG
55	60	default "db-88f6820-gp" if TARGET_DB_88F6820_GP
56	61	default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
	62	+ default "ds414" if TARGET_DS414
57	63	default "maxbcm" if TARGET_MAXBCM
58	64
59	65	config SYS_VENDOR
60	66	default "Marvell" if TARGET_DB_MV784MP_GP
61	67	default "Marvell" if TARGET_DB_88F6820_GP
62	68	default "solidrun" if TARGET_CLEARFOG
	69	+ default "Synology" if TARGET_DS414
63	70
64	71	config SYS_SOC
65	72	default "mvebu"
...	...	@@ -44,7 +44,7 @@
44	44	#define DB_784MP_GP_ID (RD_78460_SERVER_REV2_ID + 1)
45	45	#define RD_78460_CUSTOMER_ID (DB_784MP_GP_ID + 1)
46	46	#define MV_MAX_BOARD_ID (RD_78460_CUSTOMER_ID + 1)
47		-#define INVALID_BAORD_ID 0xFFFFFFFF
	47	+#define INVALID_BOARD_ID 0xFFFFFFFF
48	48
49	49	/* Sample at Reset */
50	50	#define MPP_SAMPLE_AT_RESET(id) (0x18230 + (id * 4))
	1	+#
	2	+# Copyright (C) 2015 Phil Sutter <phil@nwl.cc>
	3	+#
	4	+# SPDX-License-Identifier: GPL-2.0+
	5	+#
	6	+
	7	+obj-y := ds414.o
	1	+/*
	2	+ *
	3	+ * Copyright (C) 2015 Phil Sutter <phil@nwl.cc>
	4	+ *
	5	+ * SPDX-License-Identifier: GPL-2.0+
	6	+ */
	7	+
	8	+#include <common.h>
	9	+#include <miiphy.h>
	10	+#include <asm/io.h>
	11	+#include <asm/arch/cpu.h>
	12	+#include <asm/arch/soc.h>
	13	+#include <linux/mbus.h>
	14	+
	15	+#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
	16	+#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
	17	+#include "../arch/arm/mach-mvebu/serdes/axp/board_env_spec.h"
	18	+
	19	+DECLARE_GLOBAL_DATA_PTR;
	20	+
	21	+/* GPP and MPP settings as found in mvBoardEnvSpec.c of Synology's U-Boot */
	22	+
	23	+#define DS414_GPP_OUT_VAL_LOW (BIT(25) \| BIT(30))
	24	+#define DS414_GPP_OUT_VAL_MID (BIT(10) \| BIT(15))
	25	+#define DS414_GPP_OUT_VAL_HIGH (0)
	26	+
	27	+#define DS414_GPP_OUT_POL_LOW (0)
	28	+#define DS414_GPP_OUT_POL_MID (0)
	29	+#define DS414_GPP_OUT_POL_HIGH (0)
	30	+
	31	+#define DS414_GPP_OUT_ENA_LOW (~(BIT(25) \| BIT(30)))
	32	+#define DS414_GPP_OUT_ENA_MID (~(BIT(10) \| BIT(12) \| \
	33	+ BIT(13) \| BIT(14) \| BIT(15)))
	34	+#define DS414_GPP_OUT_ENA_HIGH (~0)
	35	+
	36	+static const u32 ds414_mpp_control[] = {
	37	+ 0x11111111,
	38	+ 0x22221111,
	39	+ 0x22222222,
	40	+ 0x00000000,
	41	+ 0x11110000,
	42	+ 0x00004000,
	43	+ 0x00000000,
	44	+ 0x00000000,
	45	+ 0x00000000
	46	+};
	47	+
	48	+/* DDR3 static MC configuration */
	49	+
	50	+/* 1G_v1 (4x2Gbits) adapted by DS414 */
	51	+MV_DRAM_MC_INIT syno_ddr3_b0_667_1g_v1[MV_MAX_DDR3_STATIC_SIZE] = {
	52	+ {0x00001400, 0x73014A28}, /DDR SDRAM Configuration Register /
	53	+ {0x00001404, 0x30000800}, /Dunit Control Low Register /
	54	+ {0x00001408, 0x44148887}, /DDR SDRAM Timing (Low) Register /
	55	+ {0x0000140C, 0x3AD83FEA}, /DDR SDRAM Timing (High) Register /
	56	+
	57	+ {0x00001410, 0x14000000}, /DDR SDRAM Address Control Register /
	58	+
	59	+ {0x00001414, 0x00000000}, /DDR SDRAM Open Pages Control Register /
	60	+ {0x00001418, 0x00000e00}, /DDR SDRAM Operation Register /
	61	+ {0x00001420, 0x00000004}, /DDR SDRAM Extended Mode Register /
	62	+ {0x00001424, 0x0000F3FF}, /Dunit Control High Register /
	63	+ {0x00001428, 0x000F8830}, /Dunit Control High Register /
	64	+ {0x0000142C, 0x054C36F4}, /Dunit Control High Register /
	65	+ {0x0000147C, 0x0000C671},
	66	+
	67	+ {0x000014a0, 0x00000001},
	68	+ {0x000014a8, 0x00000100}, /2:1 /
	69	+ {0x00020220, 0x00000006},
	70	+
	71	+ {0x00001494, 0x00010000}, /DDR SDRAM ODT Control (Low) Register /
	72	+ {0x00001498, 0x00000000}, /DDR SDRAM ODT Control (High) Register /
	73	+ {0x0000149C, 0x00000001}, /DDR Dunit ODT Control Register /
	74	+
	75	+ {0x000014C0, 0x192424C9}, /* DRAM address and Control Driving Strenght */
	76	+ {0x000014C4, 0x0AAA24C9}, /* DRAM Data and DQS Driving Strenght */
	77	+
	78	+ {0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence*/
	79	+ {0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */
	80	+
	81	+ {0x0001504, 0x3FFFFFE1}, /* CS0 Size */
	82	+ {0x000150C, 0x00000000}, /* CS1 Size */
	83	+ {0x0001514, 0x00000000}, /* CS2 Size */
	84	+ {0x000151C, 0x00000000}, /* CS3 Size */
	85	+
	86	+ {0x00001538, 0x00000009}, /Read Data Sample Delays Register /
	87	+ {0x0000153C, 0x00000009}, /Read Data Ready Delay Register /
	88	+
	89	+ {0x000015D0, 0x00000650}, /MR0 /
	90	+ {0x000015D4, 0x00000044}, /MR1 /
	91	+ {0x000015D8, 0x00000010}, /MR2 /
	92	+ {0x000015DC, 0x00000000}, /MR3 /
	93	+
	94	+ {0x000015E4, 0x00203c18}, /ZQC Configuration Register /
	95	+ {0x000015EC, 0xF800A225}, /DDR PHY /
	96	+
	97	+ {0x0, 0x0}
	98	+};
	99	+
	100	+MV_DRAM_MODES ds414_ddr_modes[MV_DDR3_MODES_NUMBER] = {
	101	+ {"ds414_1333-667", 0x3, 0x5, 0x0, A0, syno_ddr3_b0_667_1g_v1, NULL},
	102	+};
	103	+
	104	+extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
	105	+
	106	+MV_BIN_SERDES_CFG ds414_serdes_cfg[] = {
	107	+ { MV_PEX_ROOT_COMPLEX, 0x02011111, 0x00000000,
	108	+ { PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_DISABLED,
	109	+ PEX_BUS_DISABLED },
	110	+ 0x0040, serdes_change_m_phy
	111	+ }
	112	+};
	113	+
	114	+MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
	115	+{
	116	+ return &ds414_ddr_modes[0];
	117	+}
	118	+
	119	+MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
	120	+{
	121	+ return &ds414_serdes_cfg[0];
	122	+}
	123	+
	124	+u8 board_sat_r_get(u8 dev_num, u8 reg)
	125	+{
	126	+ return (0x1 << 1 \| 1);
	127	+}
	128	+
	129	+int board_early_init_f(void)
	130	+{
	131	+ int i;
	132	+
	133	+ /* Set GPP Out value */
	134	+ reg_write(GPP_DATA_OUT_REG(0), DS414_GPP_OUT_VAL_LOW);
	135	+ reg_write(GPP_DATA_OUT_REG(1), DS414_GPP_OUT_VAL_MID);
	136	+ reg_write(GPP_DATA_OUT_REG(2), DS414_GPP_OUT_VAL_HIGH);
	137	+
	138	+ /* set GPP polarity */
	139	+ reg_write(GPP_DATA_IN_POL_REG(0), DS414_GPP_OUT_POL_LOW);
	140	+ reg_write(GPP_DATA_IN_POL_REG(1), DS414_GPP_OUT_POL_MID);
	141	+ reg_write(GPP_DATA_IN_POL_REG(2), DS414_GPP_OUT_POL_HIGH);
	142	+
	143	+ /* Set GPP Out Enable */
	144	+ reg_write(GPP_DATA_OUT_EN_REG(0), DS414_GPP_OUT_ENA_LOW);
	145	+ reg_write(GPP_DATA_OUT_EN_REG(1), DS414_GPP_OUT_ENA_MID);
	146	+ reg_write(GPP_DATA_OUT_EN_REG(2), DS414_GPP_OUT_ENA_HIGH);
	147	+
	148	+ for (i = 0; i < ARRAY_SIZE(ds414_mpp_control); i++)
	149	+ reg_write(MPP_CONTROL_REG(i), ds414_mpp_control[i]);
	150	+
	151	+ return 0;
	152	+}
	153	+
	154	+int board_init(void)
	155	+{
	156	+ u32 pwr_mng_ctrl_reg;
	157	+
	158	+ /* Adress of boot parameters */
	159	+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
	160	+
	161	+ /* Gate unused clocks
	162	+ *
	163	+ * Note: Disabling unused PCIe lanes will hang PCI bus scan.
	164	+ * Once this is resolved, bits 10-12, 26 and 27 can be
	165	+ * unset here as well.
	166	+ */
	167	+ pwr_mng_ctrl_reg = reg_read(POWER_MNG_CTRL_REG);
	168	+ pwr_mng_ctrl_reg &= ~(BIT(0)); /* Audio */
	169	+ pwr_mng_ctrl_reg &= ~(BIT(1) \| BIT(2)); /* GE3, GE2 */
	170	+ pwr_mng_ctrl_reg &= ~(BIT(14) \| BIT(15)); /* SATA0 link and core */
	171	+ pwr_mng_ctrl_reg &= ~(BIT(16)); /* LCD */
	172	+ pwr_mng_ctrl_reg &= ~(BIT(17)); /* SDIO */
	173	+ pwr_mng_ctrl_reg &= ~(BIT(19) \| BIT(20)); /* USB1 and USB2 */
	174	+ pwr_mng_ctrl_reg &= ~(BIT(29) \| BIT(30)); /* SATA1 link and core */
	175	+ reg_write(POWER_MNG_CTRL_REG, pwr_mng_ctrl_reg);
	176	+
	177	+ return 0;
	178	+}
	179	+
	180	+int checkboard(void)
	181	+{
	182	+ puts("Board: DS414\n");
	183	+
	184	+ return 0;
	185	+}
	1	+#
	2	+# Copyright (C) 2014 Stefan Roese <sr@denx.de>
	3	+#
	4	+
	5	+# Armada XP uses version 1 image format
	6	+VERSION 1
	7	+
	8	+# Boot Media configurations
	9	+BOOT_FROM spi
	10	+
	11	+# Binary Header (bin_hdr) with DDR3 training code
	12	+BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
	1	+CONFIG_ARM=y
	2	+CONFIG_ARCH_MVEBU=y
	3	+CONFIG_SYS_MALLOC_F_LEN=0x2000
	4	+CONFIG_TARGET_DS414=y
	5	+CONFIG_DEFAULT_DEVICE_TREE="armada-xp-synology-ds414"
	6	+CONFIG_SPL=y
	7	+# CONFIG_CMD_IMLS is not set
	8	+# CONFIG_CMD_FLASH is not set
	9	+# CONFIG_CMD_SETEXPR is not set
	10	+CONFIG_SPL_OF_TRANSLATE=y
	11	+CONFIG_SPI_FLASH=y
	12	+CONFIG_SPI_FLASH_BAR=y
	13	+CONFIG_SPI_FLASH_STMICRO=y
	14	+CONFIG_DEBUG_UART=y
	15	+CONFIG_DEBUG_UART_BASE=0xd0012000
	16	+CONFIG_DEBUG_UART_CLOCK=250000000
	17	+CONFIG_DEBUG_UART_SHIFT=2
	18	+CONFIG_SYS_NS16550=y
	1	+/*
	2	+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
	3	+ *
	4	+ * SPDX-License-Identifier: GPL-2.0+
	5	+ */
	6	+
	7	+#ifndef _CONFIG_SYNOLOGY_DS414_H
	8	+#define _CONFIG_SYNOLOGY_DS414_H
	9	+
	10	+/*
	11	+ * High Level Configuration Options (easy to change)
	12	+ */
	13	+#define CONFIG_DISPLAY_BOARDINFO_LATE
	14	+
	15	+/*
	16	+ * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
	17	+ * for DDR ECC byte filling in the SPL before loading the main
	18	+ * U-Boot into it.
	19	+ */
	20	+#define CONFIG_SYS_TEXT_BASE 0x00800000
	21	+#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
	22	+
	23	+/*
	24	+ * Commands configuration
	25	+ */
	26	+#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
	27	+#define CONFIG_CMD_DHCP
	28	+#define CONFIG_CMD_ENV
	29	+#define CONFIG_CMD_I2C
	30	+#define CONFIG_CMD_PING
	31	+#define CONFIG_CMD_SF
	32	+#define CONFIG_CMD_SPI
	33	+#define CONFIG_CMD_TFTPPUT
	34	+#define CONFIG_CMD_TIME
	35	+#define CONFIG_CMD_USB
	36	+
	37	+/* I2C */
	38	+#define CONFIG_SYS_I2C
	39	+#define CONFIG_SYS_I2C_MVTWSI
	40	+#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
	41	+#define CONFIG_SYS_I2C_SLAVE 0x0
	42	+#define CONFIG_SYS_I2C_SPEED 100000
	43	+
	44	+/* SPI NOR flash default params, used by sf commands */
	45	+#define CONFIG_SF_DEFAULT_SPEED 1000000
	46	+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
	47	+
	48	+/* Environment in SPI NOR flash */
	49	+#define CONFIG_ENV_IS_IN_SPI_FLASH
	50	+#define CONFIG_ENV_OFFSET 0x7E0000 /* RedBoot config partition in DTS */
	51	+#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
	52	+#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
	53	+
	54	+#define CONFIG_PHY_MARVELL /* there is a marvell phy */
	55	+#define CONFIG_PHY_ADDR { 0x1, 0x0 }
	56	+#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII
	57	+
	58	+#define CONFIG_SYS_ALT_MEMTEST
	59	+
	60	+/* PCIe support */
	61	+#ifndef CONFIG_SPL_BUILD
	62	+#define CONFIG_PCI
	63	+#define CONFIG_CMD_PCI
	64	+#define CONFIG_CMD_PCI_ENUM
	65	+#define CONFIG_PCI_MVEBU
	66	+#define CONFIG_PCI_SCAN_SHOW
	67	+#endif
	68	+
	69	+/* USB/EHCI/XHCI configuration */
	70	+
	71	+#define CONFIG_DM_USB
	72	+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
	73	+
	74	+/* FIXME: broken XHCI support
	75	+ * Below defines should enable support for the two rear USB3 ports. Sadly, this
	76	+ * does not work because:
	77	+ * - xhci-pci seems to not support DM_USB, so with that enabled it is not
	78	+ * found.
	79	+ * - USB init fails, controller does not respond in time */
	80	+#if 0
	81	+#undef CONFIG_DM_USB
	82	+#define CONFIG_USB_XHCI
	83	+#define CONFIG_USB_XHCI_PCI
	84	+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
	85	+#endif
	86	+
	87	+#if !defined(CONFIG_USB_XHCI)
	88	+#define CONFIG_USB_EHCI
	89	+#define CONFIG_USB_EHCI_MARVELL
	90	+#define CONFIG_EHCI_IS_TDI
	91	+#endif
	92	+
	93	+/* why is this only defined in mv-common.h if CONFIG_DM is undefined? */
	94	+#define CONFIG_USB_STORAGE
	95	+#define CONFIG_DOS_PARTITION
	96	+#define CONFIG_ISO_PARTITION
	97	+#define CONFIG_SUPPORT_VFAT
	98	+#define CONFIG_SYS_MVFS
	99	+
	100	+/*
	101	+ * mv-common.h should be defined after CMD configs since it used them
	102	+ * to enable certain macros
	103	+ */
	104	+#include "mv-common.h"
	105	+
	106	+/*
	107	+ * Memory layout while starting into the bin_hdr via the
	108	+ * BootROM:
	109	+ *
	110	+ * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
	111	+ * 0x4000.4030 bin_hdr start address
	112	+ * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
	113	+ * 0x4007.fffc BootROM stack top
	114	+ *
	115	+ * The address space between 0x4007.fffc and 0x400f.fff is not locked in
	116	+ * L2 cache thus cannot be used.
	117	+ */
	118	+
	119	+/* SPL */
	120	+/* Defines for SPL */
	121	+#define CONFIG_SPL_FRAMEWORK
	122	+#define CONFIG_SPL_TEXT_BASE 0x40004030
	123	+#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
	124	+
	125	+#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
	126	+#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
	127	+
	128	+#ifdef CONFIG_SPL_BUILD
	129	+#define CONFIG_SYS_MALLOC_SIMPLE
	130	+#endif
	131	+
	132	+#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
	133	+#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
	134	+
	135	+#define CONFIG_SPL_LIBCOMMON_SUPPORT
	136	+#define CONFIG_SPL_LIBGENERIC_SUPPORT
	137	+#define CONFIG_SPL_SERIAL_SUPPORT
	138	+#define CONFIG_SPL_I2C_SUPPORT
	139	+
	140	+/* SPL related SPI defines */
	141	+#define CONFIG_SPL_SPI_SUPPORT
	142	+#define CONFIG_SPL_SPI_FLASH_SUPPORT
	143	+#define CONFIG_SPL_SPI_LOAD
	144	+#define CONFIG_SPL_SPI_BUS 0
	145	+#define CONFIG_SPL_SPI_CS 0
	146	+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000
	147	+
	148	+/* DS414 bus width is 32bits */
	149	+#define CONFIG_DDR_32BIT
	150	+
	151	+/* Use random ethernet address if not configured */
	152	+#define CONFIG_LIB_RAND
	153	+#define CONFIG_NET_RANDOM_ETHADDR
	154	+
	155	+/* Default Environment */
	156	+#define CONFIG_BOOTCOMMAND "sf read ${loadaddr} 0xd0000 0x700000; bootm"
	157	+#define CONFIG_BOOTARGS "console=ttyS0,115200"
	158	+#define CONFIG_LOADADDR 0x80000
	159	+#undef CONFIG_PREBOOT /* override preboot for USB and SPI flash init */
	160	+#define CONFIG_PREBOOT "usb start; sf probe"
	161	+
	162	+#endif /* _CONFIG_SYNOLOGY_DS414_H */