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Commit af0e35149b4063bbc7453fbc1d7d623360bc91c8

Authored by Masahiro Yamada
Committed by Tom Rini
1 parent 5ec71100dc
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

mpc8xx: remove ESTEEM192E board support 

This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Conn Clark <clark@esteem.com>

Showing 11 changed files with 1 additions and 1784 deletions Side-by-side Diff

arch/powerpc/cpu/mpc8xx/Kconfig
Diff comments   View file @ af0e351
... ... @@ -10,9 +10,6 @@
10 10 config TARGET_COGENT_MPC8XX
11 11 bool "Support cogent_mpc8xx"
12 12  
13   -config TARGET_ESTEEM192E
14   - bool "Support ESTEEM192E"
15   -
16 13 config TARGET_TQM823L
17 14 bool "Support TQM823L"
18 15  
... ... @@ -52,7 +49,6 @@
52 49 endchoice
53 50  
54 51 source "board/cogent/Kconfig"
55   -source "board/esteem192e/Kconfig"
56 52 source "board/tqc/tqm8xx/Kconfig"
57 53  
58 54 endmenu
board/esteem192e/Kconfig
View file @ af0e351
1   -if TARGET_ESTEEM192E
2   -
3   -config SYS_BOARD
4   - default "esteem192e"
5   -
6   -config SYS_CONFIG_NAME
7   - default "ESTEEM192E"
8   -
9   -endif
board/esteem192e/MAINTAINERS
View file @ af0e351
1   -ESTEEM192E BOARD
2   -M: Conn Clark <clark@esteem.com>
3   -S: Maintained
4   -F: board/esteem192e/
5   -F: include/configs/ESTEEM192E.h
6   -F: configs/ESTEEM192E_defconfig
board/esteem192e/Makefile
View file @ af0e351
1   -#
2   -# (C) Copyright 2000-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -obj-y = esteem192e.o flash.o
board/esteem192e/esteem192e.c
View file @ af0e351
1   -/*
2   - * (C) Copyright 2000
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - *
7   - * Modified By Conn Clark to work with Esteem 192E 7/31/00
8   - */
9   -
10   -#include <common.h>
11   -#include <mpc8xx.h>
12   -
13   -/* ------------------------------------------------------------------------- */
14   -
15   -#define _NOT_USED_ 0xFFFFFFFF
16   -
17   -const uint sdram_table[] = {
18   - /*
19   - * Single Read. (Offset 0 in UPMA RAM)
20   - *
21   - * active, NOP, read, precharge, NOP */
22   - 0x0F27CC04, 0x0EAECC04, 0x00B98C04, 0x00F74C00,
23   - 0x11FFCC05, /* last */
24   - /*
25   - * SDRAM Initialization (offset 5 in UPMA RAM)
26   - *
27   - * This is no UPM entry point. The following definition uses
28   - * the remaining space to establish an initialization
29   - * sequence, which is executed by a RUN command.
30   - * NOP, Program
31   - */
32   - 0x0F0A8C34, 0x1F354C37, /* last */
33   -
34   - _NOT_USED_, /* Not used */
35   -
36   - /*
37   - * Burst Read. (Offset 8 in UPMA RAM)
38   - * active, NOP, read, NOP, NOP, NOP, NOP, NOP */
39   - 0x0F37CC04, 0x0EFECC04, 0x00FDCC04, 0x00FFCC00,
40   - 0x00FFCC00, 0x01FFCC00, 0x0FFFCC00, 0x1FFFCC05, /* last */
41   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
42   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
43   - /*
44   - * Single Write. (Offset 18 in UPMA RAM)
45   - * active, NOP, write, NOP, precharge, NOP */
46   - 0x0F27CC04, 0x0EAE8C00, 0x01BD4C04, 0x0FFB8C04,
47   - 0x0FF74C04, 0x1FFFCC05, /* last */
48   - _NOT_USED_, _NOT_USED_,
49   - /*
50   - * Burst Write. (Offset 20 in UPMA RAM)
51   - * active, NOP, write, NOP, NOP, NOP, NOP, NOP */
52   - 0x0F37CC04, 0x0EFE8C00, 0x00FD4C00, 0x00FFCC00,
53   - 0x00FFCC00, 0x01FFCC04, 0x0FFFCC04, 0x1FFFCC05, /* last */
54   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
55   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
56   - /*
57   - * Refresh (Offset 30 in UPMA RAM)
58   - * precharge, NOP, auto_ref, NOP, NOP, NOP */
59   - 0x0FF74C34, 0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34,
60   - 0x0FFFCCB4, 0x1FFFCC35, /* last */
61   - _NOT_USED_, _NOT_USED_,
62   - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
63   - /*
64   - * Exception. (Offset 3c in UPMA RAM)
65   - */
66   - 0x0FFB8C00, 0x1FF74C03, /* last */
67   - _NOT_USED_, _NOT_USED_
68   -};
69   -
70   -/* ------------------------------------------------------------------------- */
71   -
72   -
73   -/*
74   - * Check Board Identity:
75   - */
76   -
77   -int checkboard (void)
78   -{
79   - puts ("Board: Esteem 192E\n");
80   - return (0);
81   -}
82   -
83   -/* ------------------------------------------------------------------------- */
84   -
85   -
86   -phys_size_t initdram (int board_type)
87   -{
88   - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
89   - volatile memctl8xx_t *memctl = &immap->im_memctl;
90   - long int size_b0, size_b1;
91   -
92   - /*
93   - * Explain frequency of refresh here
94   - */
95   -
96   - memctl->memc_mptpr = 0x0200; /* divide by 32 */
97   -
98   - memctl->memc_mamr = 0x18003112; /*CONFIG_SYS_MAMR_8COL; */ /* 0x18005112 TODO: explain here */
99   -
100   - upmconfig (UPMA, (uint *) sdram_table,
101   - sizeof (sdram_table) / sizeof (uint));
102   -
103   - /*
104   - * Map cs 2 and 3 to the SDRAM banks 0 and 1 at
105   - * preliminary addresses - these have to be modified after the
106   - * SDRAM size has been determined.
107   - */
108   -
109   - memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; /* not defined yet */
110   - memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
111   -
112   - memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
113   - memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
114   -
115   -
116   - /* perform SDRAM initializsation sequence */
117   - memctl->memc_mar = 0x00000088;
118   - memctl->memc_mcr = 0x80004830; /* SDRAM bank 0 execute 8 refresh */
119   - memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
120   -
121   - memctl->memc_mcr = 0x80006830; /* SDRAM bank 1 execute 8 refresh */
122   - memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
123   -
124   - memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; /* 0x18803112 start refresh timer TODO: explain here */
125   -
126   -/* printf ("banks 0 and 1 are programed\n"); */
127   -
128   - /*
129   - * Check Bank 0 Memory Size for re-configuration
130   - *
131   - */
132   - size_b0 = get_ram_size ( (long *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
133   - size_b1 = get_ram_size ( (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
134   -
135   - printf ("\nbank 0 size %lu\nbank 1 size %lu\n", size_b0, size_b1);
136   -
137   -/* printf ("bank 1 size %u\n",size_b1); */
138   -
139   - if (size_b1 == 0) {
140   - /*
141   - * Adjust refresh rate if bank 0 isn't stuffed
142   - */
143   - memctl->memc_mptpr = 0x0400; /* divide by 64 */
144   - memctl->memc_br3 &= 0x0FFFFFFFE;
145   -
146   - /*
147   - * Adjust OR2 for size of bank 0
148   - */
149   - memctl->memc_or2 |= 7 * size_b0;
150   - } else {
151   - if (size_b0 < size_b1) {
152   - memctl->memc_br2 &= 0x00007FFE;
153   - memctl->memc_br3 &= 0x00007FFF;
154   -
155   - /*
156   - * Adjust OR3 for size of bank 1
157   - */
158   - memctl->memc_or3 |= 15 * size_b1;
159   -
160   - /*
161   - * Adjust OR2 for size of bank 0
162   - */
163   - memctl->memc_or2 |= 15 * size_b0;
164   - memctl->memc_br2 += (size_b1 + 1);
165   - } else {
166   - memctl->memc_br3 &= 0x00007FFE;
167   -
168   - /*
169   - * Adjust OR2 for size of bank 0
170   - */
171   - memctl->memc_or2 |= 15 * size_b0;
172   -
173   - /*
174   - * Adjust OR3 for size of bank 1
175   - */
176   - memctl->memc_or3 |= 15 * size_b1;
177   - memctl->memc_br3 += (size_b0 + 1);
178   - }
179   - }
180   -
181   - /* before leaving set all unused i/o pins to outputs */
182   -
183   - /*
184   - * --*Unused Pin List*--
185   - *
186   - * group/port bit number
187   - * IP_B 0,1,3,4,5 Taken care of in pcmcia-cs-x.x.xx
188   - * PA 5,7,8,9,14,15
189   - * PB 22,23,31
190   - * PC 4,5,6,7,10,11,12,13,14,15
191   - * PD 5,6,7
192   - *
193   - */
194   -
195   - /*
196   - * --*Pin Used for I/O List*--
197   - *
198   - * port input bit number output bit number either
199   - * PB 18,26,27
200   - * PD 3,4 8,9,10,11,12,13,14,15
201   - *
202   - */
203   -
204   - immap->im_ioport.iop_papar &= ~0x05C3; /* set pins as io */
205   - immap->im_ioport.iop_padir |= 0x05C3; /* set pins as output */
206   - immap->im_ioport.iop_paodr &= 0x0008; /* config pins 9 & 14 as normal outputs */
207   - immap->im_ioport.iop_padat |= 0x05C3; /* set unused pins as high */
208   -
209   - immap->im_cpm.cp_pbpar &= ~0x00001331; /* set unused port b pins as io */
210   - immap->im_cpm.cp_pbdir |= 0x00001331; /* set unused port b pins as output */
211   - immap->im_cpm.cp_pbodr &= ~0x00001331; /* config bits 18,22,23,26,27 & 31 as normal outputs */
212   - immap->im_cpm.cp_pbdat |= 0x00001331; /* set T/E LED, /NV_CS, & /POWER_ADJ_CS and the rest to a high */
213   -
214   - immap->im_ioport.iop_pcpar &= ~0x0F3F; /* set unused port c pins as io */
215   - immap->im_ioport.iop_pcdir |= 0x0F3F; /* set unused port c pins as output */
216   - immap->im_ioport.iop_pcso &= ~0x0F3F; /* clear special purpose bit for unused port c pins for clarity */
217   - immap->im_ioport.iop_pcdat |= 0x0F3F; /* set unused port c pins high */
218   -
219   - immap->im_ioport.iop_pdpar &= 0xE000; /* set pins as io */
220   - immap->im_ioport.iop_pddir &= 0xE000; /* set bit 3 & 4 as inputs */
221   - immap->im_ioport.iop_pddir |= 0x07FF; /* set bits 5 - 15 as outputs */
222   - immap->im_ioport.iop_pddat = 0x0055; /* set alternating pattern on test port */
223   -
224   - return (size_b0 + size_b1);
225   -}
board/esteem192e/flash.c
View file @ af0e351
Changes suppressed. Click to show
1   -/*
2   - * (C) Copyright 2000
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -#include <mpc8xx.h>
10   -
11   -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
12   -
13   -#ifdef CONFIG_FLASH_16BIT
14   -#define FLASH_WORD_SIZE unsigned short
15   -#define FLASH_ID_MASK 0xFFFF
16   -#else
17   -#define FLASH_WORD_SIZE unsigned long
18   -#define FLASH_ID_MASK 0xFFFFFFFF
19   -#endif
20   -
21   -/*-----------------------------------------------------------------------
22   - * Functions
23   - */
24   -
25   -ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info);
26   -
27   -#ifndef CONFIG_FLASH_16BIT
28   -static int write_word (flash_info_t * info, ulong dest, ulong data);
29   -#else
30   -static int write_short (flash_info_t * info, ulong dest, ushort data);
31   -#endif
32   -/*int flash_write (uchar *, ulong, ulong); */
33   -/*flash_info_t *addr2info (ulong); */
34   -
35   -static void flash_get_offsets (ulong base, flash_info_t * info);
36   -
37   -/*-----------------------------------------------------------------------
38   - */
39   -unsigned long flash_init (void)
40   -{
41   - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
42   - volatile memctl8xx_t *memctl = &immap->im_memctl;
43   - unsigned long size_b0, size_b1;
44   - int i;
45   -
46   - /* Init: no FLASHes known */
47   - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
48   - flash_info[i].flash_id = FLASH_UNKNOWN;
49   - }
50   -
51   - /* Static FLASH Bank configuration here - FIXME XXX */
52   -
53   - size_b0 =
54   - flash_get_size ((volatile FLASH_WORD_SIZE *)
55   - FLASH_BASE0_PRELIM, &flash_info[0]);
56   - if (flash_info[0].flash_id == FLASH_UNKNOWN) {
57   - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size_b0, size_b0 << 20);
58   - }
59   -
60   - size_b1 =
61   - flash_get_size ((volatile FLASH_WORD_SIZE *)
62   - FLASH_BASE1_PRELIM, &flash_info[1]);
63   -
64   - if (size_b1 > size_b0) {
65   - printf ("## ERROR: "
66   - "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
67   - size_b1, size_b1 << 20, size_b0, size_b0 << 20);
68   - flash_info[0].flash_id = FLASH_UNKNOWN;
69   - flash_info[1].flash_id = FLASH_UNKNOWN;
70   - flash_info[0].sector_count = -1;
71   - flash_info[1].sector_count = -1;
72   - flash_info[0].size = 0;
73   - flash_info[1].size = 0;
74   - return (0);
75   - }
76   -
77   - /* Remap FLASH according to real size */
78   - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
79   - memctl->memc_br0 = CONFIG_SYS_FLASH_BASE | 0x00000801; /* (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; */
80   -
81   - /* Re-do sizing to get full correct info */
82   -
83   - size_b0 = flash_get_size ((volatile FLASH_WORD_SIZE *) CONFIG_SYS_FLASH_BASE,
84   - &flash_info[0]);
85   - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
86   -
87   -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
88   - /* monitor protection ON by default */
89   - (void) flash_protect (FLAG_PROTECT_SET,
90   - CONFIG_SYS_MONITOR_BASE,
91   - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
92   - &flash_info[0]);
93   -#endif
94   -
95   - if (size_b1) {
96   - memctl->memc_or1 =
97   - CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
98   - memctl->memc_br1 =
99   - (CONFIG_SYS_FLASH_BASE | 0x00000801) + (size_b0 & BR_BA_MSK);
100   - /*((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
101   - BR_MS_GPCM | BR_V; */
102   -
103   - /* Re-do sizing to get full correct info */
104   - size_b1 =
105   - flash_get_size ((volatile FLASH_WORD_SIZE
106   - *) (CONFIG_SYS_FLASH_BASE + size_b0),
107   - &flash_info[1]);
108   -
109   - flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
110   -
111   -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
112   - /* monitor protection ON by default */
113   - (void) flash_protect (FLAG_PROTECT_SET,
114   - CONFIG_SYS_MONITOR_BASE,
115   - CONFIG_SYS_MONITOR_BASE + monitor_flash_len -
116   - 1, &flash_info[1]);
117   -#endif
118   - } else {
119   - memctl->memc_br1 = 0; /* invalidate bank */
120   -
121   - flash_info[1].flash_id = FLASH_UNKNOWN;
122   - flash_info[1].sector_count = -1;
123   - }
124   -
125   - flash_info[0].size = size_b0;
126   - flash_info[1].size = size_b1;
127   -
128   - return (size_b0 + size_b1);
129   -}
130   -
131   -/*-----------------------------------------------------------------------
132   - */
133   -static void flash_get_offsets (ulong base, flash_info_t * info)
134   -{
135   - int i;
136   -
137   - /* set up sector start adress table */
138   - if (info->flash_id & FLASH_BTYPE) {
139   - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
140   -
141   -#ifndef CONFIG_FLASH_16BIT
142   - /* set sector offsets for bottom boot block type */
143   - info->start[0] = base + 0x00000000;
144   - info->start[1] = base + 0x00004000;
145   - info->start[2] = base + 0x00008000;
146   - info->start[3] = base + 0x0000C000;
147   - info->start[4] = base + 0x00010000;
148   - info->start[5] = base + 0x00014000;
149   - info->start[6] = base + 0x00018000;
150   - info->start[7] = base + 0x0001C000;
151   - for (i = 8; i < info->sector_count; i++) {
152   - info->start[i] =
153   - base + (i * 0x00020000) - 0x000E0000;
154   - }
155   - } else {
156   - /* set sector offsets for bottom boot block type */
157   - info->start[0] = base + 0x00000000;
158   - info->start[1] = base + 0x00008000;
159   - info->start[2] = base + 0x0000C000;
160   - info->start[3] = base + 0x00010000;
161   - for (i = 4; i < info->sector_count; i++) {
162   - info->start[i] =
163   - base + (i * 0x00020000) - 0x00060000;
164   - }
165   - }
166   -#else
167   - /* set sector offsets for bottom boot block type */
168   - info->start[0] = base + 0x00000000;
169   - info->start[1] = base + 0x00002000;
170   - info->start[2] = base + 0x00004000;
171   - info->start[3] = base + 0x00006000;
172   - info->start[4] = base + 0x00008000;
173   - info->start[5] = base + 0x0000A000;
174   - info->start[6] = base + 0x0000C000;
175   - info->start[7] = base + 0x0000E000;
176   - for (i = 8; i < info->sector_count; i++) {
177   - info->start[i] =
178   - base + (i * 0x00010000) - 0x00070000;
179   - }
180   - } else {
181   - /* set sector offsets for bottom boot block type */
182   - info->start[0] = base + 0x00000000;
183   - info->start[1] = base + 0x00004000;
184   - info->start[2] = base + 0x00006000;
185   - info->start[3] = base + 0x00008000;
186   - for (i = 4; i < info->sector_count; i++) {
187   - info->start[i] =
188   - base + (i * 0x00010000) - 0x00030000;
189   - }
190   - }
191   -#endif
192   - } else {
193   - /* set sector offsets for top boot block type */
194   - i = info->sector_count - 1;
195   - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
196   -
197   -#ifndef CONFIG_FLASH_16BIT
198   - info->start[i--] = base + info->size - 0x00004000;
199   - info->start[i--] = base + info->size - 0x00008000;
200   - info->start[i--] = base + info->size - 0x0000C000;
201   - info->start[i--] = base + info->size - 0x00010000;
202   - info->start[i--] = base + info->size - 0x00014000;
203   - info->start[i--] = base + info->size - 0x00018000;
204   - info->start[i--] = base + info->size - 0x0001C000;
205   - for (; i >= 0; i--) {
206   - info->start[i] = base + i * 0x00020000;
207   - }
208   -
209   - } else {
210   -
211   - info->start[i--] = base + info->size - 0x00008000;
212   - info->start[i--] = base + info->size - 0x0000C000;
213   - info->start[i--] = base + info->size - 0x00010000;
214   - for (; i >= 0; i--) {
215   - info->start[i] = base + i * 0x00020000;
216   - }
217   - }
218   -#else
219   - info->start[i--] = base + info->size - 0x00002000;
220   - info->start[i--] = base + info->size - 0x00004000;
221   - info->start[i--] = base + info->size - 0x00006000;
222   - info->start[i--] = base + info->size - 0x00008000;
223   - info->start[i--] = base + info->size - 0x0000A000;
224   - info->start[i--] = base + info->size - 0x0000C000;
225   - info->start[i--] = base + info->size - 0x0000E000;
226   - for (; i >= 0; i--) {
227   - info->start[i] = base + i * 0x00010000;
228   - }
229   -
230   - } else {
231   -
232   - info->start[i--] = base + info->size - 0x00004000;
233   - info->start[i--] = base + info->size - 0x00006000;
234   - info->start[i--] = base + info->size - 0x00008000;
235   - for (; i >= 0; i--) {
236   - info->start[i] = base + i * 0x00010000;
237   - }
238   - }
239   -#endif
240   - }
241   -
242   -
243   -}
244   -
245   -/*-----------------------------------------------------------------------
246   - */
247   -void flash_print_info (flash_info_t * info)
248   -{
249   - int i;
250   - uchar *boottype;
251   - uchar botboot[] = ", bottom boot sect)\n";
252   - uchar topboot[] = ", top boot sector)\n";
253   -
254   - if (info->flash_id == FLASH_UNKNOWN) {
255   - printf ("missing or unknown FLASH type\n");
256   - return;
257   - }
258   -
259   - switch (info->flash_id & FLASH_VENDMASK) {
260   - case FLASH_MAN_AMD:
261   - printf ("AMD ");
262   - break;
263   - case FLASH_MAN_FUJ:
264   - printf ("FUJITSU ");
265   - break;
266   - case FLASH_MAN_SST:
267   - printf ("SST ");
268   - break;
269   - case FLASH_MAN_STM:
270   - printf ("STM ");
271   - break;
272   - case FLASH_MAN_INTEL:
273   - printf ("INTEL ");
274   - break;
275   - default:
276   - printf ("Unknown Vendor ");
277   - break;
278   - }
279   -
280   - if (info->flash_id & 0x0001) {
281   - boottype = botboot;
282   - } else {
283   - boottype = topboot;
284   - }
285   -
286   - switch (info->flash_id & FLASH_TYPEMASK) {
287   - case FLASH_AM400B:
288   - printf ("AM29LV400B (4 Mbit%s", boottype);
289   - break;
290   - case FLASH_AM400T:
291   - printf ("AM29LV400T (4 Mbit%s", boottype);
292   - break;
293   - case FLASH_AM800B:
294   - printf ("AM29LV800B (8 Mbit%s", boottype);
295   - break;
296   - case FLASH_AM800T:
297   - printf ("AM29LV800T (8 Mbit%s", boottype);
298   - break;
299   - case FLASH_AM160B:
300   - printf ("AM29LV160B (16 Mbit%s", boottype);
301   - break;
302   - case FLASH_AM160T:
303   - printf ("AM29LV160T (16 Mbit%s", boottype);
304   - break;
305   - case FLASH_AM320B:
306   - printf ("AM29LV320B (32 Mbit%s", boottype);
307   - break;
308   - case FLASH_AM320T:
309   - printf ("AM29LV320T (32 Mbit%s", boottype);
310   - break;
311   - case FLASH_INTEL800B:
312   - printf ("INTEL28F800B (8 Mbit%s", boottype);
313   - break;
314   - case FLASH_INTEL800T:
315   - printf ("INTEL28F800T (8 Mbit%s", boottype);
316   - break;
317   - case FLASH_INTEL160B:
318   - printf ("INTEL28F160B (16 Mbit%s", boottype);
319   - break;
320   - case FLASH_INTEL160T:
321   - printf ("INTEL28F160T (16 Mbit%s", boottype);
322   - break;
323   - case FLASH_INTEL320B:
324   - printf ("INTEL28F320B (32 Mbit%s", boottype);
325   - break;
326   - case FLASH_INTEL320T:
327   - printf ("INTEL28F320T (32 Mbit%s", boottype);
328   - break;
329   -
330   -#if 0 /* enable when devices are available */
331   -
332   - case FLASH_INTEL640B:
333   - printf ("INTEL28F640B (64 Mbit%s", boottype);
334   - break;
335   - case FLASH_INTEL640T:
336   - printf ("INTEL28F640T (64 Mbit%s", boottype);
337   - break;
338   -#endif
339   -
340   - default:
341   - printf ("Unknown Chip Type\n");
342   - break;
343   - }
344   -
345   - printf (" Size: %ld MB in %d Sectors\n",
346   - info->size >> 20, info->sector_count);
347   -
348   - printf (" Sector Start Addresses:");
349   - for (i = 0; i < info->sector_count; ++i) {
350   - if ((i % 5) == 0)
351   - printf ("\n ");
352   - printf (" %08lX%s",
353   - info->start[i], info->protect[i] ? " (RO)" : " ");
354   - }
355   - printf ("\n");
356   - return;
357   -}
358   -
359   -/*-----------------------------------------------------------------------
360   - */
361   -
362   -
363   -/*-----------------------------------------------------------------------
364   - */
365   -
366   -/*
367   - * The following code cannot be run from FLASH!
368   - */
369   -ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info)
370   -{
371   - short i;
372   - ulong base = (ulong) addr;
373   - FLASH_WORD_SIZE value;
374   -
375   - /* Write auto select command: read Manufacturer ID */
376   -
377   -
378   -#ifndef CONFIG_FLASH_16BIT
379   -
380   - /*
381   - * Note: if it is an AMD flash and the word at addr[0000]
382   - * is 0x00890089 this routine will think it is an Intel
383   - * flash device and may(most likely) cause trouble.
384   - */
385   -
386   - addr[0x0000] = 0x00900090;
387   - if (addr[0x0000] != 0x00890089) {
388   - addr[0x0555] = 0x00AA00AA;
389   - addr[0x02AA] = 0x00550055;
390   - addr[0x0555] = 0x00900090;
391   -#else
392   -
393   - /*
394   - * Note: if it is an AMD flash and the word at addr[0000]
395   - * is 0x0089 this routine will think it is an Intel
396   - * flash device and may(most likely) cause trouble.
397   - */
398   -
399   - addr[0x0000] = 0x0090;
400   -
401   - if (addr[0x0000] != 0x0089) {
402   - addr[0x0555] = 0x00AA;
403   - addr[0x02AA] = 0x0055;
404   - addr[0x0555] = 0x0090;
405   -#endif
406   - }
407   - value = addr[0];
408   -
409   - switch (value) {
410   - case (AMD_MANUFACT & FLASH_ID_MASK):
411   - info->flash_id = FLASH_MAN_AMD;
412   - break;
413   - case (FUJ_MANUFACT & FLASH_ID_MASK):
414   - info->flash_id = FLASH_MAN_FUJ;
415   - break;
416   - case (STM_MANUFACT & FLASH_ID_MASK):
417   - info->flash_id = FLASH_MAN_STM;
418   - break;
419   - case (SST_MANUFACT & FLASH_ID_MASK):
420   - info->flash_id = FLASH_MAN_SST;
421   - break;
422   - case (INTEL_MANUFACT & FLASH_ID_MASK):
423   - info->flash_id = FLASH_MAN_INTEL;
424   - break;
425   - default:
426   - info->flash_id = FLASH_UNKNOWN;
427   - info->sector_count = 0;
428   - info->size = 0;
429   - return (0); /* no or unknown flash */
430   -
431   - }
432   -
433   - value = addr[1]; /* device ID */
434   -
435   - switch (value) {
436   -
437   - case (AMD_ID_LV400T & FLASH_ID_MASK):
438   - info->flash_id += FLASH_AM400T;
439   - info->sector_count = 11;
440   - info->size = 0x00100000;
441   - break; /* => 1 MB */
442   -
443   - case (AMD_ID_LV400B & FLASH_ID_MASK):
444   - info->flash_id += FLASH_AM400B;
445   - info->sector_count = 11;
446   - info->size = 0x00100000;
447   - break; /* => 1 MB */
448   -
449   - case (AMD_ID_LV800T & FLASH_ID_MASK):
450   - info->flash_id += FLASH_AM800T;
451   - info->sector_count = 19;
452   - info->size = 0x00200000;
453   - break; /* => 2 MB */
454   -
455   - case (AMD_ID_LV800B & FLASH_ID_MASK):
456   - info->flash_id += FLASH_AM800B;
457   - info->sector_count = 19;
458   - info->size = 0x00200000;
459   - break; /* => 2 MB */
460   -
461   - case (AMD_ID_LV160T & FLASH_ID_MASK):
462   - info->flash_id += FLASH_AM160T;
463   - info->sector_count = 35;
464   - info->size = 0x00400000;
465   - break; /* => 4 MB */
466   -
467   - case (AMD_ID_LV160B & FLASH_ID_MASK):
468   - info->flash_id += FLASH_AM160B;
469   - info->sector_count = 35;
470   - info->size = 0x00400000;
471   - break; /* => 4 MB */
472   -#if 0 /* enable when device IDs are available */
473   - case (AMD_ID_LV320T & FLASH_ID_MASK):
474   - info->flash_id += FLASH_AM320T;
475   - info->sector_count = 67;
476   - info->size = 0x00800000;
477   - break; /* => 8 MB */
478   -
479   - case (AMD_ID_LV320B & FLASH_ID_MASK):
480   - info->flash_id += FLASH_AM320B;
481   - info->sector_count = 67;
482   - info->size = 0x00800000;
483   - break; /* => 8 MB */
484   -#endif
485   -
486   - case (INTEL_ID_28F800B3T & FLASH_ID_MASK):
487   - info->flash_id += FLASH_INTEL800T;
488   - info->sector_count = 23;
489   - info->size = 0x00200000;
490   - break; /* => 2 MB */
491   -
492   - case (INTEL_ID_28F800B3B & FLASH_ID_MASK):
493   - info->flash_id += FLASH_INTEL800B;
494   - info->sector_count = 23;
495   - info->size = 0x00200000;
496   - break; /* => 2 MB */
497   -
498   - case (INTEL_ID_28F160B3T & FLASH_ID_MASK):
499   - info->flash_id += FLASH_INTEL160T;
500   - info->sector_count = 39;
501   - info->size = 0x00400000;
502   - break; /* => 4 MB */
503   -
504   - case (INTEL_ID_28F160B3B & FLASH_ID_MASK):
505   - info->flash_id += FLASH_INTEL160B;
506   - info->sector_count = 39;
507   - info->size = 0x00400000;
508   - break; /* => 4 MB */
509   -
510   - case (INTEL_ID_28F320B3T & FLASH_ID_MASK):
511   - info->flash_id += FLASH_INTEL320T;
512   - info->sector_count = 71;
513   - info->size = 0x00800000;
514   - break; /* => 8 MB */
515   -
516   - case (INTEL_ID_28F320B3B & FLASH_ID_MASK):
517   - info->flash_id += FLASH_AM320B;
518   - info->sector_count = 71;
519   - info->size = 0x00800000;
520   - break; /* => 8 MB */
521   -
522   -#if 0 /* enable when devices are available */
523   - case (INTEL_ID_28F320B3T & FLASH_ID_MASK):
524   - info->flash_id += FLASH_INTEL320T;
525   - info->sector_count = 135;
526   - info->size = 0x01000000;
527   - break; /* => 16 MB */
528   -
529   - case (INTEL_ID_28F320B3B & FLASH_ID_MASK):
530   - info->flash_id += FLASH_AM320B;
531   - info->sector_count = 135;
532   - info->size = 0x01000000;
533   - break; /* => 16 MB */
534   -#endif
535   - default:
536   - info->flash_id = FLASH_UNKNOWN;
537   - return (0); /* => no or unknown flash */
538   -
539   - }
540   -
541   - /* set up sector start adress table */
542   - if (info->flash_id & FLASH_BTYPE) {
543   - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
544   -
545   -#ifndef CONFIG_FLASH_16BIT
546   - /* set sector offsets for bottom boot block type */
547   - info->start[0] = base + 0x00000000;
548   - info->start[1] = base + 0x00004000;
549   - info->start[2] = base + 0x00008000;
550   - info->start[3] = base + 0x0000C000;
551   - info->start[4] = base + 0x00010000;
552   - info->start[5] = base + 0x00014000;
553   - info->start[6] = base + 0x00018000;
554   - info->start[7] = base + 0x0001C000;
555   - for (i = 8; i < info->sector_count; i++) {
556   - info->start[i] =
557   - base + (i * 0x00020000) - 0x000E0000;
558   - }
559   - } else {
560   - /* set sector offsets for bottom boot block type */
561   - info->start[0] = base + 0x00000000;
562   - info->start[1] = base + 0x00008000;
563   - info->start[2] = base + 0x0000C000;
564   - info->start[3] = base + 0x00010000;
565   - for (i = 4; i < info->sector_count; i++) {
566   - info->start[i] =
567   - base + (i * 0x00020000) - 0x00060000;
568   - }
569   - }
570   -#else
571   - /* set sector offsets for bottom boot block type */
572   - info->start[0] = base + 0x00000000;
573   - info->start[1] = base + 0x00002000;
574   - info->start[2] = base + 0x00004000;
575   - info->start[3] = base + 0x00006000;
576   - info->start[4] = base + 0x00008000;
577   - info->start[5] = base + 0x0000A000;
578   - info->start[6] = base + 0x0000C000;
579   - info->start[7] = base + 0x0000E000;
580   - for (i = 8; i < info->sector_count; i++) {
581   - info->start[i] =
582   - base + (i * 0x00010000) - 0x00070000;
583   - }
584   - } else {
585   - /* set sector offsets for bottom boot block type */
586   - info->start[0] = base + 0x00000000;
587   - info->start[1] = base + 0x00004000;
588   - info->start[2] = base + 0x00006000;
589   - info->start[3] = base + 0x00008000;
590   - for (i = 4; i < info->sector_count; i++) {
591   - info->start[i] =
592   - base + (i * 0x00010000) - 0x00030000;
593   - }
594   - }
595   -#endif
596   - } else {
597   - /* set sector offsets for top boot block type */
598   - i = info->sector_count - 1;
599   - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
600   -
601   -#ifndef CONFIG_FLASH_16BIT
602   - info->start[i--] = base + info->size - 0x00004000;
603   - info->start[i--] = base + info->size - 0x00008000;
604   - info->start[i--] = base + info->size - 0x0000C000;
605   - info->start[i--] = base + info->size - 0x00010000;
606   - info->start[i--] = base + info->size - 0x00014000;
607   - info->start[i--] = base + info->size - 0x00018000;
608   - info->start[i--] = base + info->size - 0x0001C000;
609   - for (; i >= 0; i--) {
610   - info->start[i] = base + i * 0x00020000;
611   - }
612   -
613   - } else {
614   -
615   - info->start[i--] = base + info->size - 0x00008000;
616   - info->start[i--] = base + info->size - 0x0000C000;
617   - info->start[i--] = base + info->size - 0x00010000;
618   - for (; i >= 0; i--) {
619   - info->start[i] = base + i * 0x00020000;
620   - }
621   - }
622   -#else
623   - info->start[i--] = base + info->size - 0x00002000;
624   - info->start[i--] = base + info->size - 0x00004000;
625   - info->start[i--] = base + info->size - 0x00006000;
626   - info->start[i--] = base + info->size - 0x00008000;
627   - info->start[i--] = base + info->size - 0x0000A000;
628   - info->start[i--] = base + info->size - 0x0000C000;
629   - info->start[i--] = base + info->size - 0x0000E000;
630   - for (; i >= 0; i--) {
631   - info->start[i] = base + i * 0x00010000;
632   - }
633   -
634   - } else {
635   -
636   - info->start[i--] = base + info->size - 0x00004000;
637   - info->start[i--] = base + info->size - 0x00006000;
638   - info->start[i--] = base + info->size - 0x00008000;
639   - for (; i >= 0; i--) {
640   - info->start[i] = base + i * 0x00010000;
641   - }
642   - }
643   -#endif
644   - }
645   -
646   - /* check for protected sectors */
647   - for (i = 0; i < info->sector_count; i++) {
648   - /* read sector protection at sector address, (A7 .. A0) = 0x02 */
649   - /* D0 = 1 if protected */
650   - addr = (volatile FLASH_WORD_SIZE *) (info->start[i]);
651   - info->protect[i] = addr[2] & 1;
652   - }
653   -
654   - /*
655   - * Prevent writes to uninitialized FLASH.
656   - */
657   - if (info->flash_id != FLASH_UNKNOWN) {
658   - addr = (volatile FLASH_WORD_SIZE *) info->start[0];
659   - if ((info->flash_id & 0xFF00) == FLASH_MAN_INTEL) {
660   - *addr = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */
661   - } else {
662   - *addr = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */
663   - }
664   - }
665   -
666   - return (info->size);
667   -}
668   -
669   -
670   -/*-----------------------------------------------------------------------
671   - */
672   -
673   -int flash_erase (flash_info_t * info, int s_first, int s_last)
674   -{
675   -
676   - volatile FLASH_WORD_SIZE *addr =
677   - (volatile FLASH_WORD_SIZE *) (info->start[0]);
678   - int flag, prot, sect, l_sect, barf;
679   - ulong start, now, last;
680   - int rcode = 0;
681   -
682   - if ((s_first < 0) || (s_first > s_last)) {
683   - if (info->flash_id == FLASH_UNKNOWN) {
684   - printf ("- missing\n");
685   - } else {
686   - printf ("- no sectors to erase\n");
687   - }
688   - return 1;
689   - }
690   -
691   - if ((info->flash_id == FLASH_UNKNOWN) ||
692   - ((info->flash_id > FLASH_AMD_COMP) &&
693   - ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL))) {
694   - printf ("Can't erase unknown flash type - aborted\n");
695   - return 1;
696   - }
697   -
698   - prot = 0;
699   - for (sect = s_first; sect <= s_last; ++sect) {
700   - if (info->protect[sect]) {
701   - prot++;
702   - }
703   - }
704   -
705   - if (prot) {
706   - printf ("- Warning: %d protected sectors will not be erased!\n", prot);
707   - } else {
708   - printf ("\n");
709   - }
710   -
711   - l_sect = -1;
712   -
713   - /* Disable interrupts which might cause a timeout here */
714   - flag = disable_interrupts ();
715   - if (info->flash_id < FLASH_AMD_COMP) {
716   -#ifndef CONFIG_FLASH_16BIT
717   - addr[0x0555] = 0x00AA00AA;
718   - addr[0x02AA] = 0x00550055;
719   - addr[0x0555] = 0x00800080;
720   - addr[0x0555] = 0x00AA00AA;
721   - addr[0x02AA] = 0x00550055;
722   -#else
723   - addr[0x0555] = 0x00AA;
724   - addr[0x02AA] = 0x0055;
725   - addr[0x0555] = 0x0080;
726   - addr[0x0555] = 0x00AA;
727   - addr[0x02AA] = 0x0055;
728   -#endif
729   - /* Start erase on unprotected sectors */
730   - for (sect = s_first; sect <= s_last; sect++) {
731   - if (info->protect[sect] == 0) { /* not protected */
732   - addr = (volatile FLASH_WORD_SIZE *) (info->start[sect]);
733   - addr[0] = (0x00300030 & FLASH_ID_MASK);
734   - l_sect = sect;
735   - }
736   - }
737   -
738   - /* re-enable interrupts if necessary */
739   - if (flag)
740   - enable_interrupts ();
741   -
742   - /* wait at least 80us - let's wait 1 ms */
743   - udelay (1000);
744   -
745   - /*
746   - * We wait for the last triggered sector
747   - */
748   - if (l_sect < 0)
749   - goto DONE;
750   -
751   - start = get_timer (0);
752   - last = start;
753   - addr = (volatile FLASH_WORD_SIZE *) (info->start[l_sect]);
754   - while ((addr[0] & (0x00800080 & FLASH_ID_MASK)) !=
755   - (0x00800080 & FLASH_ID_MASK)) {
756   - if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
757   - printf ("Timeout\n");
758   - return 1;
759   - }
760   - /* show that we're waiting */
761   - if ((now - last) > 1000) { /* every second */
762   - serial_putc ('.');
763   - last = now;
764   - }
765   - }
766   -
767   - DONE:
768   - /* reset to read mode */
769   - addr = (volatile FLASH_WORD_SIZE *) info->start[0];
770   - addr[0] = (0x00F000F0 & FLASH_ID_MASK); /* reset bank */
771   - } else {
772   -
773   -
774   - for (sect = s_first; sect <= s_last; sect++) {
775   - if (info->protect[sect] == 0) { /* not protected */
776   - barf = 0;
777   -#ifndef CONFIG_FLASH_16BIT
778   - addr = (vu_long *) (info->start[sect]);
779   - addr[0] = 0x00200020;
780   - addr[0] = 0x00D000D0;
781   - while (!(addr[0] & 0x00800080)); /* wait for error or finish */
782   - if (addr[0] & 0x003A003A) { /* check for error */
783   - barf = addr[0] & 0x003A0000;
784   - if (barf) {
785   - barf >>= 16;
786   - } else {
787   - barf = addr[0] & 0x0000003A;
788   - }
789   - }
790   -#else
791   - addr = (vu_short *) (info->start[sect]);
792   - addr[0] = 0x0020;
793   - addr[0] = 0x00D0;
794   - while (!(addr[0] & 0x0080)); /* wait for error or finish */
795   - if (addr[0] & 0x003A) /* check for error */
796   - barf = addr[0] & 0x003A;
797   -#endif
798   - if (barf) {
799   - printf ("\nFlash error in sector at %lx\n", (unsigned long) addr);
800   - if (barf & 0x0002)
801   - printf ("Block locked, not erased.\n");
802   - if ((barf & 0x0030) == 0x0030)
803   - printf ("Command Sequence error.\n");
804   - if ((barf & 0x0030) == 0x0020)
805   - printf ("Block Erase error.\n");
806   - if (barf & 0x0008)
807   - printf ("Vpp Low error.\n");
808   - rcode = 1;
809   - } else
810   - printf (".");
811   - l_sect = sect;
812   - }
813   - addr = (volatile FLASH_WORD_SIZE *) info->start[0];
814   - addr[0] = (0x00FF00FF & FLASH_ID_MASK); /* reset bank */
815   -
816   - }
817   -
818   - }
819   - printf (" done\n");
820   - return rcode;
821   -}
822   -
823   -/*-----------------------------------------------------------------------
824   - */
825   -
826   -/*-----------------------------------------------------------------------
827   - * Copy memory to flash, returns:
828   - * 0 - OK
829   - * 1 - write timeout
830   - * 2 - Flash not erased
831   - */
832   -
833   -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
834   -{
835   -#ifndef CONFIG_FLASH_16BIT
836   - ulong cp, wp, data;
837   - int l;
838   -#else
839   - ulong cp, wp;
840   - ushort data;
841   -#endif
842   - int i, rc;
843   -
844   -#ifndef CONFIG_FLASH_16BIT
845   -
846   -
847   - wp = (addr & ~3); /* get lower word aligned address */
848   -
849   - /*
850   - * handle unaligned start bytes
851   - */
852   - if ((l = addr - wp) != 0) {
853   - data = 0;
854   - for (i = 0, cp = wp; i < l; ++i, ++cp) {
855   - data = (data << 8) | (*(uchar *) cp);
856   - }
857   - for (; i < 4 && cnt > 0; ++i) {
858   - data = (data << 8) | *src++;
859   - --cnt;
860   - ++cp;
861   - }
862   - for (; cnt == 0 && i < 4; ++i, ++cp) {
863   - data = (data << 8) | (*(uchar *) cp);
864   - }
865   -
866   - if ((rc = write_word (info, wp, data)) != 0) {
867   - return (rc);
868   - }
869   - wp += 4;
870   - }
871   -
872   - /*
873   - * handle word aligned part
874   - */
875   - while (cnt >= 4) {
876   - data = 0;
877   - for (i = 0; i < 4; ++i) {
878   - data = (data << 8) | *src++;
879   - }
880   - if ((rc = write_word (info, wp, data)) != 0) {
881   - return (rc);
882   - }
883   - wp += 4;
884   - cnt -= 4;
885   - }
886   -
887   - if (cnt == 0) {
888   - return (0);
889   - }
890   -
891   - /*
892   - * handle unaligned tail bytes
893   - */
894   - data = 0;
895   - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
896   - data = (data << 8) | *src++;
897   - --cnt;
898   - }
899   - for (; i < 4; ++i, ++cp) {
900   - data = (data << 8) | (*(uchar *) cp);
901   - }
902   -
903   - return (write_word (info, wp, data));
904   -
905   -#else
906   - wp = (addr & ~1); /* get lower word aligned address */
907   -
908   - /*
909   - * handle unaligned start byte
910   - */
911   - if (addr - wp) {
912   - data = 0;
913   - data = (data << 8) | *src++;
914   - --cnt;
915   - if ((rc = write_short (info, wp, data)) != 0) {
916   - return (rc);
917   - }
918   - wp += 2;
919   - }
920   -
921   - /*
922   - * handle word aligned part
923   - */
924   -/* l = 0; used for debuging */
925   - while (cnt >= 2) {
926   - data = 0;
927   - for (i = 0; i < 2; ++i) {
928   - data = (data << 8) | *src++;
929   - }
930   -
931   -/* if(!l){
932   - printf("%x",data);
933   - l = 1;
934   - } used for debuging */
935   -
936   - if ((rc = write_short (info, wp, data)) != 0) {
937   - return (rc);
938   - }
939   - wp += 2;
940   - cnt -= 2;
941   - }
942   -
943   - if (cnt == 0) {
944   - return (0);
945   - }
946   -
947   - /*
948   - * handle unaligned tail bytes
949   - */
950   - data = 0;
951   - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
952   - data = (data << 8) | *src++;
953   - --cnt;
954   - }
955   - for (; i < 2; ++i, ++cp) {
956   - data = (data << 8) | (*(uchar *) cp);
957   - }
958   -
959   - return (write_short (info, wp, data));
960   -
961   -
962   -#endif
963   -}
964   -
965   -/*-----------------------------------------------------------------------
966   - * Write a word to Flash, returns:
967   - * 0 - OK
968   - * 1 - write timeout
969   - * 2 - Flash not erased
970   - */
971   -#ifndef CONFIG_FLASH_16BIT
972   -static int write_word (flash_info_t * info, ulong dest, ulong data)
973   -{
974   - vu_long *addr = (vu_long *) (info->start[0]);
975   - ulong start, barf;
976   - int flag;
977   -
978   -
979   - /* Check if Flash is (sufficiently) erased */
980   - if ((*((vu_long *) dest) & data) != data) {
981   - return (2);
982   - }
983   -
984   - /* Disable interrupts which might cause a timeout here */
985   - flag = disable_interrupts ();
986   -
987   - if (info->flash_id > FLASH_AMD_COMP) {
988   - /* AMD stuff */
989   - addr[0x0555] = 0x00AA00AA;
990   - addr[0x02AA] = 0x00550055;
991   - addr[0x0555] = 0x00A000A0;
992   - } else {
993   - /* intel stuff */
994   - *addr = 0x00400040;
995   - }
996   - *((vu_long *) dest) = data;
997   -
998   - /* re-enable interrupts if necessary */
999   - if (flag)
1000   - enable_interrupts ();
1001   -
1002   - /* data polling for D7 */
1003   - start = get_timer (0);
1004   -
1005   - if (info->flash_id > FLASH_AMD_COMP) {
1006   -
1007   - while ((*((vu_long *) dest) & 0x00800080) !=
1008   - (data & 0x00800080)) {
1009   - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
1010   - return (1);
1011   - }
1012   - }
1013   -
1014   - } else {
1015   -
1016   - while (!(addr[0] & 0x00800080)) { /* wait for error or finish */
1017   - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
1018   - return (1);
1019   - }
1020   -
1021   - if (addr[0] & 0x003A003A) { /* check for error */
1022   - barf = addr[0] & 0x003A0000;
1023   - if (barf) {
1024   - barf >>= 16;
1025   - } else {
1026   - barf = addr[0] & 0x0000003A;
1027   - }
1028   - printf ("\nFlash write error at address %lx\n", (unsigned long) dest);
1029   - if (barf & 0x0002)
1030   - printf ("Block locked, not erased.\n");
1031   - if (barf & 0x0010)
1032   - printf ("Programming error.\n");
1033   - if (barf & 0x0008)
1034   - printf ("Vpp Low error.\n");
1035   - return (2);
1036   - }
1037   -
1038   -
1039   - }
1040   -
1041   - return (0);
1042   -
1043   - }
1044   -
1045   -#else
1046   -
1047   -static int write_short (flash_info_t * info, ulong dest, ushort data)
1048   -{
1049   - vu_short *addr = (vu_short *) (info->start[0]);
1050   - ulong start, barf;
1051   - int flag;
1052   -
1053   - /* Check if Flash is (sufficiently) erased */
1054   - if ((*((vu_short *) dest) & data) != data) {
1055   - return (2);
1056   - }
1057   -
1058   - /* Disable interrupts which might cause a timeout here */
1059   - flag = disable_interrupts ();
1060   -
1061   - if (info->flash_id < FLASH_AMD_COMP) {
1062   - /* AMD stuff */
1063   - addr[0x0555] = 0x00AA;
1064   - addr[0x02AA] = 0x0055;
1065   - addr[0x0555] = 0x00A0;
1066   - } else {
1067   - /* intel stuff */
1068   - *addr = 0x00D0;
1069   - *addr = 0x0040;
1070   - }
1071   - *((vu_short *) dest) = data;
1072   -
1073   - /* re-enable interrupts if necessary */
1074   - if (flag)
1075   - enable_interrupts ();
1076   -
1077   - /* data polling for D7 */
1078   - start = get_timer (0);
1079   -
1080   - if (info->flash_id < FLASH_AMD_COMP) {
1081   - /* AMD stuff */
1082   - while ((*((vu_short *) dest) & 0x0080) != (data & 0x0080)) {
1083   - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
1084   - return (1);
1085   - }
1086   - }
1087   -
1088   - } else {
1089   - /* intel stuff */
1090   - while (!(addr[0] & 0x0080)) { /* wait for error or finish */
1091   - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT)
1092   - return (1);
1093   - }
1094   -
1095   - if (addr[0] & 0x003A) { /* check for error */
1096   - barf = addr[0] & 0x003A;
1097   - printf ("\nFlash write error at address %lx\n",
1098   - (unsigned long) dest);
1099   - if (barf & 0x0002)
1100   - printf ("Block locked, not erased.\n");
1101   - if (barf & 0x0010)
1102   - printf ("Programming error.\n");
1103   - if (barf & 0x0008)
1104   - printf ("Vpp Low error.\n");
1105   - return (2);
1106   - }
1107   - *addr = 0x00B0;
1108   - *addr = 0x0070;
1109   - while (!(addr[0] & 0x0080)) { /* wait for error or finish */
1110   - if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT)
1111   - return (1);
1112   - }
1113   - *addr = 0x00FF;
1114   - }
1115   - return (0);
1116   -}
1117   -
1118   -#endif
1119   -/*-----------------------------------------------------------------------*/
board/esteem192e/u-boot.lds
View file @ af0e351
1   -/*
2   - * (C) Copyright 2000-2010
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -OUTPUT_ARCH(powerpc)
9   -
10   -SECTIONS
11   -{
12   - /* Read-only sections, merged into text segment: */
13   - . = + SIZEOF_HEADERS;
14   - .text :
15   - {
16   - /* WARNING - the following is hand-optimized to fit within */
17   - /* the sector layout of our flash chips! XXX FIXME XXX */
18   -
19   - arch/powerpc/cpu/mpc8xx/start.o (.text*)
20   - arch/powerpc/cpu/mpc8xx/traps.o (.text*)
21   - net/built-in.o (.text*)
22   - board/esteem192e/built-in.o (.text*)
23   -
24   - . = env_offset;
25   - common/env_embedded.o (.text*)
26   -
27   - *(.text*)
28   - }
29   - _etext = .;
30   - PROVIDE (etext = .);
31   - .rodata :
32   - {
33   - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
34   - }
35   -
36   - /* Read-write section, merged into data segment: */
37   - . = (. + 0x00FF) & 0xFFFFFF00;
38   - _erotext = .;
39   - PROVIDE (erotext = .);
40   - .reloc :
41   - {
42   - _GOT2_TABLE_ = .;
43   - KEEP(*(.got2))
44   - KEEP(*(.got))
45   - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
46   - _FIXUP_TABLE_ = .;
47   - KEEP(*(.fixup))
48   - }
49   - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
50   - __fixup_entries = (. - _FIXUP_TABLE_)>>2;
51   -
52   - .data :
53   - {
54   - *(.data*)
55   - *(.sdata*)
56   - }
57   - _edata = .;
58   - PROVIDE (edata = .);
59   -
60   - . = .;
61   -
62   - . = ALIGN(4);
63   - .u_boot_list : {
64   - KEEP(*(SORT(.u_boot_list*)));
65   - }
66   -
67   -
68   - . = .;
69   - __start___ex_table = .;
70   - __ex_table : { *(__ex_table) }
71   - __stop___ex_table = .;
72   -
73   - . = ALIGN(256);
74   - __init_begin = .;
75   - .text.init : { *(.text.init) }
76   - .data.init : { *(.data.init) }
77   - . = ALIGN(256);
78   - __init_end = .;
79   -
80   - __bss_start = .;
81   - .bss (NOLOAD) :
82   - {
83   - *(.bss*)
84   - *(.sbss*)
85   - *(COMMON)
86   - . = ALIGN(4);
87   - }
88   - __bss_end = . ;
89   - PROVIDE (end = .);
90   -}
configs/ESTEEM192E_defconfig
View file @ af0e351
1   -CONFIG_PPC=y
2   -CONFIG_8xx=y
3   -CONFIG_TARGET_ESTEEM192E=y
doc/README.scrapyard
Diff comments   View file @ af0e351
... ... @@ -12,6 +12,7 @@
12 12  
13 13 Board Arch CPU Commit Removed Last known maintainer/contact
14 14 =================================================================================================
  15 +ESTEEM192E powerpc mpc8xx - - Conn Clark <clark@esteem.com>
15 16 IP860 powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
16 17 IVML24 powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
17 18 IVMS8 powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
... ... @@ -456,34 +456,6 @@
456 456 #define SICR_ENET_CLKRT ((uint)0x00002c00)
457 457 #endif /* CONFIG_BSEIP */
458 458  
459   -/*** ESTEEM 192E **************************************************/
460   -#ifdef CONFIG_ESTEEM192E
461   -/* ESTEEM192E
462   - * This ENET stuff is for the MPC850 with ethernet on SCC2. This
463   - * is very similar to the RPX-Lite configuration.
464   - * Note TENA , LOOPBACK , FDPLEX_DIS on Port B.
465   - */
466   -
467   -#define PROFF_ENET PROFF_SCC2
468   -#define CPM_CR_ENET CPM_CR_CH_SCC2
469   -#define SCC_ENET 1
470   -
471   -#define PA_ENET_RXD ((ushort)0x0004)
472   -#define PA_ENET_TXD ((ushort)0x0008)
473   -#define PA_ENET_TCLK ((ushort)0x0200)
474   -#define PA_ENET_RCLK ((ushort)0x0800)
475   -#define PB_ENET_TENA ((uint)0x00002000)
476   -#define PC_ENET_CLSN ((ushort)0x0040)
477   -#define PC_ENET_RENA ((ushort)0x0080)
478   -
479   -#define SICR_ENET_MASK ((uint)0x0000ff00)
480   -#define SICR_ENET_CLKRT ((uint)0x00003d00)
481   -
482   -#define PB_ENET_LOOPBACK ((uint)0x00004000)
483   -#define PB_ENET_FDPLEX_DIS ((uint)0x00008000)
484   -
485   -#endif
486   -
487 459 /*** KM8XX *********************************************************/
488 460  
489 461 /* The KM8XX Service Module uses SCC3 for Ethernet */
include/configs/ESTEEM192E.h
View file @ af0e351
1   -/*
2   - * (C) Copyright 2000
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -/*
9   - * board/config.h - configuration options, board specific
10   - */
11   -
12   -#ifndef __CONFIG_H
13   -#define __CONFIG_H
14   -
15   -/*
16   - * High Level Configuration Options
17   - * (easy to change)
18   - */
19   -
20   -#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
21   -#define CONFIG_ESTEEM192E 1 /* ...on a EST ESTEEM192E */
22   -
23   -#define CONFIG_SYS_TEXT_BASE 0x40000000
24   -
25   -#define CONFIG_FLASH_16BIT 1 /* Rom 16 bit data bus */
26   -
27   -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
28   -#undef CONFIG_8xx_CONS_SMC2
29   -#undef CONFIG_8xx_CONS_NONE
30   -
31   -#define MPC8XX_FACT 10 /* Multiply by 10 */
32   -#define MPC8XX_XIN 4915200 /* 4.915200 MHz in - ??? - XXX */
33   -#define CONFIG_SYS_PLPRCR_MF ((MPC8XX_FACT-1) << 20)
34   -#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) /* 49,152,000 Hz */
35   -
36   -#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */
37   -
38   -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
39   -
40   -#define CONFIG_BAUDRATE 9600
41   -#if 0
42   -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
43   -#else
44   -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
45   -#endif
46   -#define CONFIG_BOOTCOMMAND "bootm 40030000" /* autoboot command */
47   -
48   -#define CONFIG_BOOTARGS "root=/dev/ram rw ramdisk=8192 " \
49   - "ip=100.100.100.21:100.100.100.14:100.100.100.1:255.0.0.0 "
50   -/*
51   - * Miscellaneous configurable options
52   - */
53   -
54   -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
55   -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
56   -
57   -#undef CONFIG_WATCHDOG /* watchdog disabled */
58   -
59   -/*
60   - * BOOTP options
61   - */
62   -#define CONFIG_BOOTP_SUBNETMASK
63   -#define CONFIG_BOOTP_GATEWAY
64   -#define CONFIG_BOOTP_HOSTNAME
65   -#define CONFIG_BOOTP_BOOTPATH
66   -#define CONFIG_BOOTP_BOOTFILESIZE
67   -
68   -
69   -/*
70   - * Command line configuration.
71   - */
72   -#include <config_cmd_default.h>
73   -
74   -
75   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
76   -#define CONFIG_SYS_PROMPT "BOOT: " /* Monitor Command Prompt */
77   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
78   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
79   -#define CONFIG_SYS_MAXARGS 8 /* max number of command args */
80   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
81   -
82   -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
83   -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
84   -
85   -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
86   -
87   -/*
88   - * Low Level Configuration Settings
89   - * (address mappings, register initial values, etc.)
90   - * You should know what you are doing if you make changes here.
91   - */
92   -/*-----------------------------------------------------------------------
93   - * Internal Memory Mapped Register
94   - */
95   -#define CONFIG_SYS_IMMR 0xFF000000
96   -
97   - /*-----------------------------------------------------------------------
98   - * Definitions for initial stack pointer and data area (in DPRAM)
99   - */
100   -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
101   -#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
102   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
103   -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
104   -
105   -
106   -/*-----------------------------------------------------------------------
107   - * Start addresses for the final memory configuration
108   - * (Set up by the startup code)
109   - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
110   - */
111   -#define CONFIG_SYS_SDRAM_BASE 0x00000000
112   -#define CONFIG_SYS_FLASH_BASE 0x40000000
113   -#ifdef DEBUG
114   -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
115   -#else
116   -#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
117   -#endif
118   -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
119   -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
120   -
121   -/*
122   - * For booting Linux, the board info and command line data
123   - * have to be in the first 8 MB of memory, since this is
124   - * the maximum mapped by the Linux kernel during initialization.
125   - */
126   -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
127   -/*-----------------------------------------------------------------------
128   - * FLASH organization
129   - */
130   -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
131   -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
132   -
133   -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
134   -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
135   -
136   -#define CONFIG_ENV_IS_IN_FLASH 1
137   -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
138   -#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
139   -/*-----------------------------------------------------------------------
140   - * Cache Configuration
141   - */
142   -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
143   -
144   -/*-----------------------------------------------------------------------
145   - * SYPCR - System Protection Control 11-9
146   - * SYPCR can only be written once after reset!
147   - *-----------------------------------------------------------------------
148   - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
149   - */
150   -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
151   -
152   -/*-----------------------------------------------------------------------
153   - * SUMCR - SIU Module Configuration 11-6
154   - *-----------------------------------------------------------------------
155   - * PCMCIA config., multi-function pin tri-state
156   - */
157   -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) /* DBGC00 */
158   -
159   -/*-----------------------------------------------------------------------
160   - * TBSCR - Time Base Status and Control 11-26
161   - *-----------------------------------------------------------------------
162   - * Clear Reference Interrupt Status, Timebase freezing enabled
163   - */
164   -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
165   -
166   -/* (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) */
167   -
168   -
169   -/*-----------------------------------------------------------------------
170   - * PISCR - Periodic Interrupt Status and Control 11-31
171   - *-----------------------------------------------------------------------
172   - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
173   - */
174   -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
175   -
176   -/*-----------------------------------------------------------------------
177   - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
178   - *-----------------------------------------------------------------------
179   - * Reset PLL lock status sticky bit, timer expired status bit and timer
180   - * interrupt status bit - leave PLL multiplication factor unchanged !
181   - */
182   -#define CONFIG_SYS_PLPRCR (CONFIG_SYS_PLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
183   -
184   -/*-----------------------------------------------------------------------
185   - * SCCR - System Clock and reset Control Register 15-27
186   - *-----------------------------------------------------------------------
187   - * Set clock output, timebase and RTC source and divider,
188   - * power management and some other internal clocks
189   - */
190   -#define SCCR_MASK SCCR_EBDF11
191   -#define CONFIG_SYS_SCCR (SCCR_TBS | \
192   - SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
193   - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
194   - SCCR_DFALCD00)
195   -
196   -/*-----------------------------------------------------------------------
197   - * PCMCIA stuff
198   - *-----------------------------------------------------------------------
199   - *
200   - */
201   -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
202   -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
203   -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
204   -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
205   -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
206   -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
207   -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
208   -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
209   -
210   -#define CONFIG_SYS_PCMCIA_INTERRUPT SIU_LEVEL6
211   -
212   -/*-----------------------------------------------------------------------
213   - *
214   - *-----------------------------------------------------------------------
215   - *
216   - */
217   -/*#define CONFIG_SYS_DER 0x2002000F*/
218   -#define CONFIG_SYS_DER 0
219   -/*#define CONFIG_SYS_DER 0x02002000 */
220   -
221   -
222   -/*
223   - * Init Memory Controller:
224   - *
225   - * BR0/1 and OR0/1 (FLASH)
226   - */
227   -
228   -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
229   -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
230   -
231   -/* used to re-map FLASH both when starting from SRAM or FLASH:
232   - * restrict access enough to keep SRAM working (if any)
233   - * but not too much to meddle with FLASH accesses
234   - */
235   -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
236   -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
237   -
238   -/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
239   -#define CONFIG_SYS_OR_TIMING_FLASH 0x00000160
240   - /*(OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
241   - OR_SCY_5_CLK | OR_EHTR) */
242   -
243   -#define CONFIG_SYS_OR0_REMAP 0x80000160 /*(CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)*/
244   -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
245   -#define CONFIG_SYS_BR0_PRELIM ( FLASH_BASE0_PRELIM | 0x00000801 )
246   -
247   -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
248   -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
249   -#define CONFIG_SYS_BR1_PRELIM ( FLASH_BASE1_PRELIM | 0x00000801 )
250   -
251   -/*
252   - * BR2/3 and OR2/3 (SDRAM)
253   - *
254   - */
255   -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
256   -#define SDRAM_BASE3_PRELIM 0x04000000 /* SDRAM bank #1 */
257   -#define SDRAM_MAX_SIZE 0x02000000 /* max 32 MB per bank */
258   -
259   -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
260   -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
261   -
262   -#define CONFIG_SYS_OR2_PRELIM 0xFC000E00
263   -#define CONFIG_SYS_BR2_PRELIM (SDRAM_BASE2_PRELIM | 0x00000081)
264   -
265   -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
266   -#define CONFIG_SYS_BR3_PRELIM (SDRAM_BASE3_PRELIM | 0x00000081)
267   -
268   -
269   -/*
270   - * Memory Periodic Timer Prescaler
271   - */
272   -
273   -/* periodic timer for refresh */
274   -#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
275   -
276   -/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
277   -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
278   -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
279   -
280   -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
281   -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
282   -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
283   -
284   -/*
285   - * MAMR settings for SDRAM
286   - */
287   -
288   -/* 8 column SDRAM */
289   -#define CONFIG_SYS_MAMR_8COL 0x18803112
290   -#define CONFIG_SYS_MAMR_9COL 0x18803112 /* same as 8 column because its just easier to port with*/
291   -
292   -#endif /* __CONFIG_H */