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Commit af55e35d33894295cf0f2f94c050f67d05b50944

Authored by Masahiro Yamada
Committed by Tom Rini
1 parent e7a565638a
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

powerpc: mpc5xxx: remove board support for MVBC_P and MVSMR 

These boards have been orphaned for more than 6 months.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Showing 26 changed files with 2 additions and 1848 deletions Side-by-side Diff

arch/powerpc/cpu/mpc5xxx/Kconfig
Diff comments   View file @ af55e35
... ... @@ -97,12 +97,6 @@
97 97 config TARGET_UC101
98 98 bool "Support uc101"
99 99  
100   -config TARGET_MVBC_P
101   - bool "Support MVBC_P"
102   -
103   -config TARGET_MVSMR
104   - bool "Support MVSMR"
105   -
106 100 config TARGET_PCM030
107 101 bool "Support pcm030"
108 102  
... ... @@ -139,8 +133,6 @@
139 133 source "board/manroland/hmi1001/Kconfig"
140 134 source "board/manroland/mucmc52/Kconfig"
141 135 source "board/manroland/uc101/Kconfig"
142   -source "board/matrix_vision/mvbc_p/Kconfig"
143   -source "board/matrix_vision/mvsmr/Kconfig"
144 136 source "board/mcc200/Kconfig"
145 137 source "board/motionpro/Kconfig"
146 138 source "board/munices/Kconfig"
board/matrix_vision/mvbc_p/Kconfig
View file @ af55e35
1   -if TARGET_MVBC_P
2   -
3   -config SYS_BOARD
4   - default "mvbc_p"
5   -
6   -config SYS_VENDOR
7   - default "matrix_vision"
8   -
9   -config SYS_CONFIG_NAME
10   - default "MVBC_P"
11   -
12   -endif
board/matrix_vision/mvbc_p/MAINTAINERS
View file @ af55e35
1   -MVBC_P BOARD
2   -#M: Andre Schwarz <andre.schwarz@matrix-vision.de>
3   -S: Orphan (since 2014-03)
4   -F: board/matrix_vision/mvbc_p/
5   -F: include/configs/MVBC_P.h
6   -F: configs/MVBC_P_defconfig
board/matrix_vision/mvbc_p/Makefile
View file @ af55e35
1   -#
2   -# (C) Copyright 2003
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# (C) Copyright 2004-2008
6   -# Matrix-Vision GmbH, info@matrix-vision.de
7   -#
8   -# SPDX-License-Identifier: GPL-2.0+
9   -#
10   -
11   -obj-y := mvbc_p.o fpga.o
board/matrix_vision/mvbc_p/README.mvbc_p
View file @ af55e35
1   -Matrix Vision mvBlueCOUGAR-P (mvBC-P)
2   --------------------------------------
3   -
4   -1. Board Description
5   -
6   - The mvBC-P is a 70x40x40mm multi board gigabit ethernet network camera
7   - with main focus on GigEVision protocol in combination with local image
8   - preprocessing.
9   -
10   - Power Supply is either VDC 48V or Pover over Ethernet (PoE).
11   -
12   -2 System Components
13   -
14   -2.1 CPU
15   - Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB.
16   - 64MB SDRAM @ 133MHz.
17   - 8 MByte Nor Flash on local bus.
18   - 1 serial ports. Console running on ttyS0 @ 115200 8N1.
19   -
20   -2.2 PCI
21   - PCI clock fixed at 66MHz. Arbitration inside FPGA.
22   - Intel GD82541ER network MAC/PHY and FPGA connected.
23   -
24   -2.3 FPGA
25   - Altera Cyclone-II EP2C8 with PCI DMA engine.
26   - Connects to Matrix Vision specific CCD/CMOS sensor interface.
27   - Utilizes 64MB Nand Flash.
28   -
29   -2.3.1 I/O @ FPGA
30   - 2 Outputs : photo coupler
31   - 2 Inputs : photo coupler
32   -
33   -2.4 I2C
34   - LM75 @ 0x90 for temperature monitoring.
35   - EEPROM @ 0xA0 for vendor specifics.
36   - image sensor interface (slave addresses depend on sensor)
37   -
38   -3 Flash layout.
39   -
40   - reset vector is 0x00000100, i.e. "LOWBOOT".
41   -
42   - FF800000 u-boot
43   - FF840000 u-boot script image
44   - FF850000 redundant u-boot script image
45   - FF860000 FPGA raw bit file
46   - FF8A0000 tbd.
47   - FF900000 root FS
48   - FFC00000 kernel
49   - FFFC0000 device tree blob
50   - FFFD0000 redundant device tree blob
51   - FFFE0000 environment
52   - FFFF0000 redundant environment
53   -
54   - mtd partitions are propagated to linux kernel via device tree blob.
55   -
56   -4 Booting
57   -
58   - On startup the bootscript @ FF840000 is executed. This script can be
59   - exchanged easily. Default boot mode is "boot from flash", i.e. system
60   - works stand-alone.
61   -
62   - This behaviour depends on some environment variables :
63   -
64   - "netboot" : yes ->try dhcp/bootp and boot from network.
65   - A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
66   - DHCP server configuration, e.g. to provide different images to
67   - different devices.
68   -
69   - During netboot the system tries to get 3 image files:
70   - 1. Kernel - name + data is given during BOOTP.
71   - 2. Initrd - name is stored in "initrd_name"
72   - 3. device tree blob - name is stored in "dtb_name"
73   - Fallback files are the flash versions.
board/matrix_vision/mvbc_p/fpga.c
View file @ af55e35
1   -/*
2   - * (C) Copyright 2002
3   - * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4   - * Keith Outwater, keith_outwater@mvis.com.
5   - *
6   - * (C) Copyright 2008
7   - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
8   - *
9   - * SPDX-License-Identifier: GPL-2.0+
10   - */
11   -
12   -#include <common.h>
13   -#include <ACEX1K.h>
14   -#include <command.h>
15   -#include "fpga.h"
16   -#include "mvbc_p.h"
17   -
18   -#ifdef FPGA_DEBUG
19   -#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args)
20   -#else
21   -#define fpga_debug(fmt, args...)
22   -#endif
23   -
24   -Altera_CYC2_Passive_Serial_fns altera_fns = {
25   - fpga_null_fn,
26   - fpga_config_fn,
27   - fpga_status_fn,
28   - fpga_done_fn,
29   - fpga_wr_fn,
30   - fpga_null_fn,
31   - fpga_null_fn,
32   -};
33   -
34   -Altera_desc cyclone2 = {
35   - Altera_CYC2,
36   - passive_serial,
37   - Altera_EP2C8_SIZE,
38   - (void *) &altera_fns,
39   - NULL,
40   -};
41   -
42   -DECLARE_GLOBAL_DATA_PTR;
43   -
44   -int mvbc_p_init_fpga(void)
45   -{
46   - fpga_debug("Initialize FPGA interface\n");
47   - fpga_init();
48   - fpga_add(fpga_altera, &cyclone2);
49   - fpga_config_fn(0, 1, 0);
50   - udelay(60);
51   -
52   - return 1;
53   -}
54   -
55   -int fpga_null_fn(int cookie)
56   -{
57   - return 0;
58   -}
59   -
60   -int fpga_config_fn(int assert, int flush, int cookie)
61   -{
62   - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
63   - u32 dvo = gpio->simple_dvo;
64   -
65   - fpga_debug("SET config : %s\n", assert ? "low" : "high");
66   - if (assert)
67   - dvo |= FPGA_CONFIG;
68   - else
69   - dvo &= ~FPGA_CONFIG;
70   -
71   - if (flush)
72   - gpio->simple_dvo = dvo;
73   -
74   - return assert;
75   -}
76   -
77   -int fpga_done_fn(int cookie)
78   -{
79   - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
80   - int result = 0;
81   -
82   - udelay(10);
83   - fpga_debug("CONF_DONE check ... ");
84   - if (gpio->simple_ival & FPGA_CONF_DONE) {
85   - fpga_debug("high\n");
86   - result = 1;
87   - } else
88   - fpga_debug("low\n");
89   -
90   - return result;
91   -}
92   -
93   -int fpga_status_fn(int cookie)
94   -{
95   - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
96   - int result = 0;
97   -
98   - fpga_debug("STATUS check ... ");
99   - if (gpio->sint_ival & FPGA_STATUS) {
100   - fpga_debug("high\n");
101   - result = 1;
102   - } else
103   - fpga_debug("low\n");
104   -
105   - return result;
106   -}
107   -
108   -int fpga_clk_fn(int assert_clk, int flush, int cookie)
109   -{
110   - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
111   - u32 dvo = gpio->simple_dvo;
112   -
113   - fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low");
114   - if (assert_clk)
115   - dvo |= FPGA_CCLK;
116   - else
117   - dvo &= ~FPGA_CCLK;
118   -
119   - if (flush)
120   - gpio->simple_dvo = dvo;
121   -
122   - return assert_clk;
123   -}
124   -
125   -static inline int _write_fpga(u8 val)
126   -{
127   - int i;
128   - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
129   - u32 dvo = gpio->simple_dvo;
130   -
131   - for (i=0; i<8; i++) {
132   - dvo &= ~FPGA_CCLK;
133   - gpio->simple_dvo = dvo;
134   - dvo &= ~FPGA_DIN;
135   - if (val & 1)
136   - dvo |= FPGA_DIN;
137   - gpio->simple_dvo = dvo;
138   - dvo |= FPGA_CCLK;
139   - gpio->simple_dvo = dvo;
140   - val >>= 1;
141   - }
142   -
143   - return 0;
144   -}
145   -
146   -int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
147   -{
148   - unsigned char *data = (unsigned char *) buf;
149   - int i;
150   -
151   - fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
152   - for (i = 0; i < len; i++)
153   - _write_fpga(data[i]);
154   - fpga_debug("\n");
155   -
156   - return FPGA_SUCCESS;
157   -}
board/matrix_vision/mvbc_p/fpga.h
View file @ af55e35
1   -/*
2   - * (C) Copyright 2002
3   - * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4   - * Keith Outwater, keith_outwater@mvis.com.
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -extern int mvbc_p_init_fpga(void);
10   -
11   -extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
12   -extern int fpga_status_fn(int cookie);
13   -extern int fpga_config_fn(int assert, int flush, int cookie);
14   -extern int fpga_done_fn(int cookie);
15   -extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
16   -extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
17   -extern int fpga_null_fn(int cookie);
board/matrix_vision/mvbc_p/mvbc_p.c
View file @ af55e35
1   -/*
2   - * (C) Copyright 2003
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * (C) Copyright 2004
6   - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7   - *
8   - * (C) Copyright 2005-2007
9   - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
10   - *
11   - * SPDX-License-Identifier: GPL-2.0+
12   - */
13   -
14   -#include <common.h>
15   -#include <mpc5xxx.h>
16   -#include <malloc.h>
17   -#include <pci.h>
18   -#include <i2c.h>
19   -#include <fpga.h>
20   -#include <environment.h>
21   -#include <fdt_support.h>
22   -#include <netdev.h>
23   -#include <asm/io.h>
24   -#include "fpga.h"
25   -#include "mvbc_p.h"
26   -#include "../common/mv_common.h"
27   -
28   -#define SDRAM_MODE 0x00CD0000
29   -#define SDRAM_CONTROL 0x504F0000
30   -#define SDRAM_CONFIG1 0xD2322800
31   -#define SDRAM_CONFIG2 0x8AD70000
32   -
33   -DECLARE_GLOBAL_DATA_PTR;
34   -
35   -static void sdram_start (int hi_addr)
36   -{
37   - long hi_bit = hi_addr ? 0x01000000 : 0;
38   -
39   - /* unlock mode register */
40   - out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 | hi_bit);
41   -
42   - /* precharge all banks */
43   - out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit);
44   -
45   - /* precharge all banks */
46   - out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit);
47   -
48   - /* auto refresh */
49   - out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 | hi_bit);
50   -
51   - /* set mode register */
52   - out_be32((u32*)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
53   -
54   - /* normal operation */
55   - out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit);
56   -}
57   -
58   -phys_addr_t initdram (int board_type)
59   -{
60   - ulong dramsize = 0;
61   - ulong test1,
62   - test2;
63   -
64   - /* setup SDRAM chip selects */
65   - out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);
66   -
67   - /* setup config registers */
68   - out_be32((u32*)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
69   - out_be32((u32*)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
70   -
71   - /* find RAM size using SDRAM CS0 only */
72   - sdram_start(0);
73   - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
74   - sdram_start(1);
75   - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
76   - if (test1 > test2) {
77   - sdram_start(0);
78   - dramsize = test1;
79   - } else
80   - dramsize = test2;
81   -
82   - if (dramsize < (1 << 20))
83   - dramsize = 0;
84   -
85   - if (dramsize > 0)
86   - out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x13 +
87   - __builtin_ffs(dramsize >> 20) - 1);
88   - else
89   - out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0);
90   -
91   - return dramsize;
92   -}
93   -
94   -void mvbc_init_gpio(void)
95   -{
96   - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
97   -
98   - printf("Ports : 0x%08x\n", gpio->port_config);
99   - printf("PORCFG: 0x%08lx\n", *(vu_long*)MPC5XXX_CDM_PORCFG);
100   -
101   - out_be32(&gpio->simple_ddr, SIMPLE_DDR);
102   - out_be32(&gpio->simple_dvo, SIMPLE_DVO);
103   - out_be32(&gpio->simple_ode, SIMPLE_ODE);
104   - out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
105   -
106   - out_8(&gpio->sint_ode, SINT_ODE);
107   - out_8(&gpio->sint_ddr, SINT_DDR);
108   - out_8(&gpio->sint_dvo, SINT_DVO);
109   - out_8(&gpio->sint_inten, SINT_INTEN);
110   - out_be16(&gpio->sint_itype, SINT_ITYPE);
111   - out_8(&gpio->sint_gpioe, SINT_GPIOEN);
112   -
113   - out_8((u8*)MPC5XXX_WU_GPIO_ODE, WKUP_ODE);
114   - out_8((u8*)MPC5XXX_WU_GPIO_DIR, WKUP_DIR);
115   - out_8((u8*)MPC5XXX_WU_GPIO_DATA_O, WKUP_DO);
116   - out_8((u8*)MPC5XXX_WU_GPIO_ENABLE, WKUP_EN);
117   -
118   - printf("simple_gpioe: 0x%08x\n", gpio->simple_gpioe);
119   - printf("sint_gpioe : 0x%08x\n", gpio->sint_gpioe);
120   -}
121   -
122   -int misc_init_r(void)
123   -{
124   - char *s = getenv("reset_env");
125   -
126   - if (!s) {
127   - if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
128   - return 0;
129   - udelay(50000);
130   - if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
131   - return 0;
132   - udelay(50000);
133   - if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
134   - return 0;
135   - }
136   - printf(" === FACTORY RESET ===\n");
137   - mv_reset_environment();
138   - saveenv();
139   -
140   - return -1;
141   -}
142   -
143   -int checkboard(void)
144   -{
145   - mvbc_init_gpio();
146   - printf("Board: Matrix Vision mvBlueCOUGAR-P\n");
147   -
148   - return 0;
149   -}
150   -
151   -void flash_preinit(void)
152   -{
153   - /*
154   - * Now, when we are in RAM, enable flash write
155   - * access for detection process.
156   - * Note that CS_BOOT cannot be cleared when
157   - * executing in flash.
158   - */
159   - clrbits_be32((u32*)MPC5XXX_BOOTCS_CFG, 0x1);
160   -}
161   -
162   -void flash_afterinit(ulong size)
163   -{
164   - out_be32((u32*)MPC5XXX_BOOTCS_START, START_REG(CONFIG_SYS_BOOTCS_START |
165   - size));
166   - out_be32((u32*)MPC5XXX_CS0_START, START_REG(CONFIG_SYS_BOOTCS_START |
167   - size));
168   - out_be32((u32*)MPC5XXX_BOOTCS_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size,
169   - size));
170   - out_be32((u32*)MPC5XXX_CS0_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size,
171   - size));
172   -}
173   -
174   -void pci_mvbc_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
175   -{
176   - unsigned char line = 0xff;
177   - char *s = getenv("pci_latency");
178   - u32 base;
179   - u8 val = 0;
180   -
181   - if (s)
182   - val = simple_strtoul(s, NULL, 16);
183   -
184   - if (PCI_BUS(dev) == 0) {
185   - switch (PCI_DEV (dev)) {
186   - case 0xa: /* FPGA */
187   - line = 3;
188   - pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &base);
189   - printf("found FPGA - enable arbitration\n");
190   - writel(0x03, (u32*)(base + 0x80c0));
191   - writel(0xf0, (u32*)(base + 0x8080));
192   - if (val)
193   - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val);
194   - break;
195   - case 0xb: /* LAN */
196   - line = 2;
197   - if (val)
198   - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val);
199   - break;
200   - case 0x1a:
201   - break;
202   - default:
203   - printf ("***pci_scan: illegal dev = 0x%08x\n", PCI_DEV (dev));
204   - break;
205   - }
206   - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, line);
207   - }
208   -}
209   -
210   -struct pci_controller hose = {
211   - fixup_irq:pci_mvbc_fixup_irq
212   -};
213   -
214   -extern void pci_mpc5xxx_init(struct pci_controller *);
215   -
216   -void pci_init_board(void)
217   -{
218   - mvbc_p_init_fpga();
219   - mv_load_fpga();
220   - pci_mpc5xxx_init(&hose);
221   -}
222   -
223   -void show_boot_progress(int val)
224   -{
225   - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
226   -
227   - switch(val) {
228   - case BOOTSTAGE_ID_START: /* FPGA ok */
229   - setbits_be32(&gpio->simple_dvo, LED_G0);
230   - break;
231   - case BOOTSTAGE_ID_NET_ETH_INIT:
232   - setbits_be32(&gpio->simple_dvo, LED_G1);
233   - break;
234   - case BOOTSTAGE_ID_COPY_RAMDISK:
235   - setbits_be32(&gpio->simple_dvo, LED_Y);
236   - break;
237   - case BOOTSTAGE_ID_RUN_OS:
238   - setbits_be32(&gpio->simple_dvo, LED_R);
239   - break;
240   - default:
241   - break;
242   - }
243   -
244   -}
245   -
246   -void ft_board_setup(void *blob, bd_t *bd)
247   -{
248   - ft_cpu_setup(blob, bd);
249   -}
250   -
251   -int board_eth_init(bd_t *bis)
252   -{
253   - cpu_eth_init(bis); /* Built in FEC comes first */
254   - return pci_eth_init(bis);
255   -}
board/matrix_vision/mvbc_p/mvbc_p.h
View file @ af55e35
1   -#ifndef __MVBC_H__
2   -#define __MVBC_H__
3   -
4   -#define LED_G0 MPC5XXX_GPIO_SIMPLE_PSC2_0
5   -#define LED_G1 MPC5XXX_GPIO_SIMPLE_PSC2_1
6   -#define LED_Y MPC5XXX_GPIO_SIMPLE_PSC2_2
7   -#define LED_R MPC5XXX_GPIO_SIMPLE_PSC2_3
8   -#define ARB_X_EN MPC5XXX_GPIO_WKUP_PSC2_4
9   -
10   -#define FPGA_DIN MPC5XXX_GPIO_SIMPLE_PSC3_0
11   -#define FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_1
12   -#define FPGA_CONF_DONE MPC5XXX_GPIO_SIMPLE_PSC3_2
13   -#define FPGA_CONFIG MPC5XXX_GPIO_SIMPLE_PSC3_3
14   -#define FPGA_STATUS MPC5XXX_GPIO_SINT_PSC3_4
15   -
16   -#define MAN_RST MPC5XXX_GPIO_WKUP_PSC6_0
17   -#define WD_TS MPC5XXX_GPIO_WKUP_PSC6_1
18   -#define WD_WDI MPC5XXX_GPIO_SIMPLE_PSC6_2
19   -#define COP_PRESENT MPC5XXX_GPIO_SIMPLE_PSC6_3
20   -#define FACT_RST MPC5XXX_GPIO_WKUP_6
21   -#define FLASH_RBY MPC5XXX_GPIO_WKUP_7
22   -
23   -#define SIMPLE_DDR (LED_G0 | LED_G1 | LED_Y | LED_R | \
24   - FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI)
25   -#define SIMPLE_DVO (FPGA_CONFIG)
26   -#define SIMPLE_ODE (FPGA_CONFIG | LED_G0 | LED_G1 | LED_Y | LED_R)
27   -#define SIMPLE_GPIOEN (LED_G0 | LED_G1 | LED_Y | LED_R | \
28   - FPGA_DIN | FPGA_CCLK | FPGA_CONF_DONE | FPGA_CONFIG |\
29   - WD_WDI | COP_PRESENT)
30   -
31   -#define SINT_ODE 0
32   -#define SINT_DDR 0
33   -#define SINT_DVO 0
34   -#define SINT_INTEN 0
35   -#define SINT_ITYPE 0
36   -#define SINT_GPIOEN (FPGA_STATUS)
37   -
38   -#define WKUP_ODE (MAN_RST)
39   -#define WKUP_DIR (ARB_X_EN|MAN_RST|WD_TS)
40   -#define WKUP_DO (ARB_X_EN|MAN_RST|WD_TS)
41   -#define WKUP_EN (ARB_X_EN|MAN_RST|WD_TS|FACT_RST|FLASH_RBY)
42   -
43   -#endif
board/matrix_vision/mvbc_p/mvbc_p_autoscript
View file @ af55e35
1   -echo
2   -echo "==== running autoscript ===="
3   -echo
4   -setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram}
5   -setenv ramkernel setenv kernel_boot \${loadaddr}
6   -setenv flashkernel setenv kernel_boot \${mv_kernel_addr}
7   -setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length}
8   -setenv bootfromflash run flashkernel cpird ramparam addcons e1000para addprofile bootdtb
9   -setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name}
10   -setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000
11   -setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup
12   -setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel
13   -if test ${console} = yes;
14   -then
15   -setenv addcons setenv bootargs \${bootargs} console=ttyPSC\${console_nr},\${baudrate}N8
16   -else
17   -setenv addcons setenv bootargs \${bootargs} console=tty0
18   -fi
19   -setenv e1000para setenv bootargs \${bootargs} e1000.TxDescriptors=256 e1000.SmartPowerDownEnable=1
20   -setenv set_static_ip setenv ipaddr \${static_ipaddr}
21   -setenv set_static_nm setenv netmask \${static_netmask}
22   -setenv set_static_gw setenv gatewayip \${static_gateway}
23   -setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask}
24   -setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs
25   -if test ${oprofile} = yes;
26   -then
27   -setenv addprofile setenv bootargs \${bootargs} profile=\${profile}
28   -fi
29   -if test ${autoscript_boot} != no;
30   -then
31   - if test ${netboot} = yes;
32   - then
33   - bootp
34   - if test $? = 0;
35   - then
36   - echo "=== bootp succeeded -> netboot ==="
37   - run set_ip
38   - run getdtb rundtb bootfromnet ramparam addcons e1000para addprofile bootdtb
39   - else
40   - echo "=== netboot failed ==="
41   - fi
42   - fi
43   - run set_static_ip set_static_nm set_static_gw set_ip
44   - echo "=== bootfromflash ==="
45   - run cpdtb rundtb bootfromflash
46   -else
47   - echo "=== boot stopped with autoscript_boot no ==="
48   -fi
board/matrix_vision/mvsmr/.gitignore
View file @ af55e35
1   -bootscript.img
board/matrix_vision/mvsmr/Kconfig
View file @ af55e35
1   -if TARGET_MVSMR
2   -
3   -config SYS_BOARD
4   - default "mvsmr"
5   -
6   -config SYS_VENDOR
7   - default "matrix_vision"
8   -
9   -config SYS_CONFIG_NAME
10   - default "MVSMR"
11   -
12   -endif
board/matrix_vision/mvsmr/MAINTAINERS
View file @ af55e35
1   -MVSMR BOARD
2   -#M: Andre Schwarz <andre.schwarz@matrix-vision.de>
3   -S: Orphan (since 2014-03)
4   -F: board/matrix_vision/mvsmr/
5   -F: include/configs/MVSMR.h
6   -F: configs/MVSMR_defconfig
board/matrix_vision/mvsmr/Makefile
View file @ af55e35
1   -#
2   -# (C) Copyright 2003
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# (C) Copyright 2004-2008
6   -# Matrix-Vision GmbH, info@matrix-vision.de
7   -#
8   -# SPDX-License-Identifier: GPL-2.0+
9   -#
10   -
11   -obj-y := mvsmr.o fpga.o
12   -
13   -extra-y := bootscript.img
14   -
15   -MKIMAGEFLAGS_bootscript.image := -T script -C none -n mvSMR_Script
16   -
17   -$(obj)/bootscript.img: $(src)/bootscript
18   - $(call cmd,mkimage)
board/matrix_vision/mvsmr/README.mvsmr
View file @ af55e35
1   -Matrix Vision mvSMR
2   --------------------
3   -
4   -1. Board Description
5   -
6   - The mvSMR is a 75x130mm single image processing board used
7   - in automation. Power Supply is 24VDC.
8   -
9   -2 System Components
10   -
11   -2.1 CPU
12   - Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB.
13   - 64MB DDR-I @ 133MHz.
14   - 8 MByte Nor Flash on local bus.
15   - 2 serial ports. Console running on ttyS0 @ 115200 8N1.
16   -
17   -2.2 PCI
18   - PCI clock fixed at 33MHz due to old'n'slow Xilinx PCI core.
19   -
20   -2.3 FPGA
21   - Xilinx Spartan-3 XC3S200 with PCI DMA engine.
22   - Connects to Matrix Vision specific CCD/CMOS sensor interface.
23   -
24   -2.4 I2C
25   - EEPROM @ 0xA0 for vendor specifics.
26   - image sensor interface (slave addresses depend on sensor)
27   -
28   -3 Flash layout.
29   -
30   - reset vector is 0x00000100, i.e. "LOWBOOT".
31   -
32   - FF800000 u-boot
33   - FF806000 u-boot script image
34   - FF808000 u-boot environment
35   - FF840000 FPGA raw bit file
36   - FF880000 root FS
37   - FFF00000 kernel
38   -
39   -4 Booting
40   -
41   - On startup the bootscript @ FF806000 is executed. This script can be
42   - exchanged easily. Default boot mode is "boot from flash", i.e. system
43   - works stand-alone.
44   -
45   - This behaviour depends on some environment variables :
46   -
47   - "netboot" : yes ->try dhcp/bootp and boot from network.
48   - A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
49   - DHCP server configuration, e.g. to provide different images to
50   - different devices.
51   -
52   - During netboot the system tries to get 3 image files:
53   - 1. Kernel - name + data is given during BOOTP.
54   - 2. Initrd - name is stored in "initrd_name"
55   - Fallback files are the flash versions.
board/matrix_vision/mvsmr/bootscript
View file @ af55e35
1   -echo
2   -echo "==== running autoscript ===="
3   -echo
4   -setenv boot24 'bootm ${kernel_boot} ${mv_initrd_addr_ram}'
5   -setenv ramkernel 'setenv kernel_boot ${loadaddr}'
6   -setenv flashkernel 'setenv kernel_boot ${mv_kernel_addr}'
7   -setenv cpird 'cp ${mv_initrd_addr} ${mv_initrd_addr_ram} ${mv_initrd_length}'
8   -setenv bootfromflash run flashkernel cpird addcons boot24
9   -setenv bootfromnet 'tftp ${mv_initrd_addr_ram} ${initrd_name};run ramkernel'
10   -if test ${console} = yes;
11   -then
12   -setenv addcons 'setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8'
13   -else
14   -setenv addcons 'setenv bootargs ${bootargs} console=tty0'
15   -fi
16   -setenv set_static_ip 'setenv ipaddr ${static_ipaddr}'
17   -setenv set_static_nm 'setenv netmask ${static_netmask}'
18   -setenv set_static_gw 'setenv gatewayip ${static_gateway}'
19   -setenv set_ip 'setenv ip ${ipaddr}::${gatewayip}:${netmask}'
20   -if test ${servicemode} != yes;
21   -then
22   - echo "=== forced flash mode ==="
23   - run set_static_ip set_static_nm set_static_gw set_ip bootfromflash
24   -fi
25   -if test ${autoscript_boot} != no;
26   -then
27   - if test ${netboot} = yes;
28   - then
29   - bootp
30   - if test $? = 0;
31   - then
32   - echo "=== bootp succeeded -> netboot ==="
33   - run set_ip bootfromnet addcons boot24
34   - else
35   - echo "=== netboot failed ==="
36   - fi
37   - fi
38   - echo "=== bootfromflash ==="
39   - run set_static_ip set_static_nm set_static_gw set_ip bootfromflash
40   -else
41   - echo "=== boot stopped with autoscript_boot no ==="
42   -fi
board/matrix_vision/mvsmr/fpga.c
View file @ af55e35
1   -/*
2   - * (C) Copyright 2002
3   - * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4   - * Keith Outwater, keith_outwater@mvis.com.
5   - *
6   - * (C) Copyright 2010
7   - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
8   - *
9   - * SPDX-License-Identifier: GPL-2.0+
10   - */
11   -
12   -#include <common.h>
13   -#include <spartan3.h>
14   -#include <command.h>
15   -#include <asm/io.h>
16   -#include "fpga.h"
17   -#include "mvsmr.h"
18   -
19   -xilinx_spartan3_slave_serial_fns fpga_fns = {
20   - fpga_pre_config_fn,
21   - fpga_pgm_fn,
22   - fpga_clk_fn,
23   - fpga_init_fn,
24   - fpga_done_fn,
25   - fpga_wr_fn,
26   - 0
27   -};
28   -
29   -xilinx_desc spartan3 = {
30   - xilinx_spartan2,
31   - slave_serial,
32   - XILINX_XC3S200_SIZE,
33   - (void *) &fpga_fns,
34   - 0,
35   -};
36   -
37   -DECLARE_GLOBAL_DATA_PTR;
38   -
39   -int mvsmr_init_fpga(void)
40   -{
41   - fpga_init();
42   - fpga_add(fpga_xilinx, &spartan3);
43   -
44   - return 1;
45   -}
46   -
47   -int fpga_init_fn(int cookie)
48   -{
49   - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
50   -
51   - if (in_be32(&gpio->simple_ival) & FPGA_CONFIG)
52   - return 0;
53   -
54   - return 1;
55   -}
56   -
57   -int fpga_done_fn(int cookie)
58   -{
59   - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
60   - int result = 0;
61   -
62   - udelay(10);
63   - if (in_be32(&gpio->simple_ival) & FPGA_DONE)
64   - result = 1;
65   -
66   - return result;
67   -}
68   -
69   -int fpga_pgm_fn(int assert, int flush, int cookie)
70   -{
71   - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
72   -
73   - if (!assert)
74   - setbits_8(&gpio->sint_dvo, FPGA_STATUS);
75   - else
76   - clrbits_8(&gpio->sint_dvo, FPGA_STATUS);
77   -
78   - return assert;
79   -}
80   -
81   -int fpga_clk_fn(int assert_clk, int flush, int cookie)
82   -{
83   - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
84   -
85   - if (assert_clk)
86   - setbits_be32(&gpio->simple_dvo, FPGA_CCLK);
87   - else
88   - clrbits_be32(&gpio->simple_dvo, FPGA_CCLK);
89   -
90   - return assert_clk;
91   -}
92   -
93   -int fpga_wr_fn(int assert_write, int flush, int cookie)
94   -{
95   - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
96   -
97   - if (assert_write)
98   - setbits_be32(&gpio->simple_dvo, FPGA_DIN);
99   - else
100   - clrbits_be32(&gpio->simple_dvo, FPGA_DIN);
101   -
102   - return assert_write;
103   -}
104   -
105   -int fpga_pre_config_fn(int cookie)
106   -{
107   - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
108   -
109   - setbits_8(&gpio->sint_dvo, FPGA_STATUS);
110   -
111   - return 0;
112   -}
board/matrix_vision/mvsmr/fpga.h
View file @ af55e35
1   -/*
2   - * (C) Copyright 2008
3   - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -extern int mvsmr_init_fpga(void);
9   -
10   -extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
11   -extern int fpga_init_fn(int cookie);
12   -extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
13   -extern int fpga_wr_fn(int assert_write, int flush, int cookie);
14   -extern int fpga_done_fn(int cookie);
15   -extern int fpga_pre_config_fn(int cookie);
board/matrix_vision/mvsmr/mvsmr.c
View file @ af55e35
1   -/*
2   - * (C) Copyright 2003
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * (C) Copyright 2004
6   - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7   - *
8   - * (C) Copyright 2005-2010
9   - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
10   - *
11   - * SPDX-License-Identifier: GPL-2.0+
12   - */
13   -
14   -#include <common.h>
15   -#include <mpc5xxx.h>
16   -#include <malloc.h>
17   -#include <pci.h>
18   -#include <i2c.h>
19   -#include <fpga.h>
20   -#include <environment.h>
21   -#include <netdev.h>
22   -#include <asm/io.h>
23   -#include "fpga.h"
24   -#include "mvsmr.h"
25   -#include "../common/mv_common.h"
26   -
27   -#define SDRAM_DDR 1
28   -#define SDRAM_MODE 0x018D0000
29   -#define SDRAM_EMODE 0x40090000
30   -#define SDRAM_CONTROL 0x715f0f00
31   -#define SDRAM_CONFIG1 0xd3722930
32   -#define SDRAM_CONFIG2 0x46770000
33   -
34   -DECLARE_GLOBAL_DATA_PTR;
35   -
36   -static void sdram_start(int hi_addr)
37   -{
38   - long hi_bit = hi_addr ? 0x01000000 : 0;
39   -
40   - /* unlock mode register */
41   - out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 |
42   - hi_bit);
43   -
44   - /* precharge all banks */
45   - out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 |
46   - hi_bit);
47   -
48   - /* set mode register: extended mode */
49   - out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
50   -
51   - /* set mode register: reset DLL */
52   - out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
53   -
54   - /* precharge all banks */
55   - out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 |
56   - hi_bit);
57   -
58   - /* auto refresh */
59   - out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 |
60   - hi_bit);
61   -
62   - /* set mode register */
63   - out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
64   -
65   - /* normal operation */
66   - out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit);
67   -}
68   -
69   -phys_addr_t initdram(int board_type)
70   -{
71   - ulong dramsize = 0;
72   - ulong test1,
73   - test2;
74   -
75   - /* setup SDRAM chip selects */
76   - out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);
77   -
78   - /* setup config registers */
79   - out_be32((u32 *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
80   - out_be32((u32 *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
81   -
82   - /* find RAM size using SDRAM CS0 only */
83   - sdram_start(0);
84   - test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
85   - sdram_start(1);
86   - test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
87   - if (test1 > test2) {
88   - sdram_start(0);
89   - dramsize = test1;
90   - } else
91   - dramsize = test2;
92   -
93   - if (dramsize < (1 << 20))
94   - dramsize = 0;
95   -
96   - if (dramsize > 0)
97   - out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x13 +
98   - __builtin_ffs(dramsize >> 20) - 1);
99   - else
100   - out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0);
101   -
102   - return dramsize;
103   -}
104   -
105   -void mvsmr_init_gpio(void)
106   -{
107   - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
108   - struct mpc5xxx_wu_gpio *wu_gpio =
109   - (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
110   - struct mpc5xxx_gpt_0_7 *timers = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
111   -
112   - printf("Ports : 0x%08x\n", gpio->port_config);
113   - printf("PORCFG: 0x%08x\n", in_be32((unsigned *)MPC5XXX_CDM_PORCFG));
114   -
115   - out_be32(&gpio->simple_ddr, SIMPLE_DDR);
116   - out_be32(&gpio->simple_dvo, SIMPLE_DVO);
117   - out_be32(&gpio->simple_ode, SIMPLE_ODE);
118   - out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
119   -
120   - out_8(&gpio->sint_ode, SINT_ODE);
121   - out_8(&gpio->sint_ddr, SINT_DDR);
122   - out_8(&gpio->sint_dvo, SINT_DVO);
123   - out_8(&gpio->sint_inten, SINT_INTEN);
124   - out_be16(&gpio->sint_itype, SINT_ITYPE);
125   - out_8(&gpio->sint_gpioe, SINT_GPIOEN);
126   -
127   - out_8(&wu_gpio->ode, WKUP_ODE);
128   - out_8(&wu_gpio->ddr, WKUP_DIR);
129   - out_8(&wu_gpio->dvo, WKUP_DO);
130   - out_8(&wu_gpio->enable, WKUP_EN);
131   -
132   - out_be32(&timers->gpt0.emsr, 0x00000234); /* OD output high */
133   - out_be32(&timers->gpt1.emsr, 0x00000234);
134   - out_be32(&timers->gpt2.emsr, 0x00000234);
135   - out_be32(&timers->gpt3.emsr, 0x00000234);
136   - out_be32(&timers->gpt4.emsr, 0x00000234);
137   - out_be32(&timers->gpt5.emsr, 0x00000234);
138   - out_be32(&timers->gpt6.emsr, 0x00000024); /* push-pull output low */
139   - out_be32(&timers->gpt7.emsr, 0x00000024);
140   -}
141   -
142   -int misc_init_r(void)
143   -{
144   - char *s = getenv("reset_env");
145   -
146   - if (s) {
147   - printf(" === FACTORY RESET ===\n");
148   - mv_reset_environment();
149   - saveenv();
150   - }
151   -
152   - return -1;
153   -}
154   -
155   -void mvsmr_get_dbg_present(void)
156   -{
157   - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
158   - struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)MPC5XXX_PSC1;
159   -
160   - if (in_be32(&gpio->simple_ival) & COP_PRESENT) {
161   - setenv("dbg_present", "no\0");
162   - setenv("bootstopkey", "abcdefghijklmnopqrstuvwxyz\0");
163   - } else {
164   - setenv("dbg_present", "yes\0");
165   - setenv("bootstopkey", "s\0");
166   - setbits_8(&psc->command, PSC_RX_ENABLE);
167   - }
168   -}
169   -
170   -void mvsmr_get_service_mode(void)
171   -{
172   - struct mpc5xxx_wu_gpio *wu_gpio =
173   - (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
174   -
175   - if (in_8(&wu_gpio->ival) & SERVICE_MODE)
176   - setenv("servicemode", "no\0");
177   - else
178   - setenv("servicemode", "yes\0");
179   -}
180   -
181   -int mvsmr_get_mac(void)
182   -{
183   - unsigned char mac[6];
184   - struct mpc5xxx_wu_gpio *wu_gpio =
185   - (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
186   -
187   - if (in_8(&wu_gpio->ival) & LAN_PRSNT) {
188   - setenv("lan_present", "no\0");
189   - return -1;
190   - } else
191   - setenv("lan_present", "yes\0");
192   -
193   - i2c_read(0x50, 0, 1, mac, 6);
194   -
195   - eth_setenv_enetaddr("ethaddr", mac);
196   -
197   - return 0;
198   -}
199   -
200   -int checkboard(void)
201   -{
202   - mvsmr_init_gpio();
203   - printf("Board: Matrix Vision mvSMR\n");
204   -
205   - return 0;
206   -}
207   -
208   -void flash_preinit(void)
209   -{
210   - /*
211   - * Now, when we are in RAM, enable flash write
212   - * access for detection process.
213   - * Note that CS_BOOT cannot be cleared when
214   - * executing in flash.
215   - */
216   - clrbits_be32((u32 *)MPC5XXX_BOOTCS_CFG, 0x1);
217   -}
218   -
219   -void flash_afterinit(ulong size)
220   -{
221   - out_be32((u32 *)MPC5XXX_BOOTCS_START,
222   - START_REG(CONFIG_SYS_BOOTCS_START | size));
223   - out_be32((u32 *)MPC5XXX_CS0_START,
224   - START_REG(CONFIG_SYS_BOOTCS_START | size));
225   - out_be32((u32 *)MPC5XXX_BOOTCS_STOP,
226   - STOP_REG(CONFIG_SYS_BOOTCS_START | size, size));
227   - out_be32((u32 *)MPC5XXX_CS0_STOP,
228   - STOP_REG(CONFIG_SYS_BOOTCS_START | size, size));
229   -}
230   -
231   -struct pci_controller hose;
232   -
233   -void pci_init_board(void)
234   -{
235   - mvsmr_get_dbg_present();
236   - mvsmr_get_service_mode();
237   - mvsmr_init_fpga();
238   - mv_load_fpga();
239   - pci_mpc5xxx_init(&hose);
240   -}
241   -
242   -int board_eth_init(bd_t *bis)
243   -{
244   - if (!mvsmr_get_mac())
245   - return cpu_eth_init(bis);
246   -
247   - return pci_eth_init(bis);
248   -}
board/matrix_vision/mvsmr/mvsmr.h
View file @ af55e35
1   -#include <pci.h>
2   -
3   -extern void pci_mpc5xxx_init(struct pci_controller *);
4   -
5   -#define FPGA_DIN MPC5XXX_GPIO_SIMPLE_PSC3_0
6   -#define FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_1
7   -#define FPGA_DONE MPC5XXX_GPIO_SIMPLE_PSC3_2
8   -#define FPGA_CONFIG MPC5XXX_GPIO_SIMPLE_PSC3_3
9   -#define FPGA_STATUS MPC5XXX_GPIO_SINT_PSC3_4
10   -#define S_FPGA_DIN MPC5XXX_GPIO_SINT_PSC3_5
11   -#define S_FPGA_CCLK MPC5XXX_GPIO_SIMPLE_PSC3_6
12   -#define S_FPGA_DONE MPC5XXX_GPIO_SIMPLE_PSC3_7
13   -#define S_FPGA_CONFIG MPC5XXX_GPIO_SINT_PSC3_8
14   -#define S_FPGA_STATUS MPC5XXX_GPIO_WKUP_PSC3_9
15   -
16   -#define MAN_RST MPC5XXX_GPIO_WKUP_PSC6_0
17   -#define WD_TS MPC5XXX_GPIO_WKUP_PSC6_1
18   -#define WD_WDI MPC5XXX_GPIO_SIMPLE_PSC6_2
19   -#define COP_PRESENT MPC5XXX_GPIO_SIMPLE_PSC6_3
20   -#define SERVICE_MODE MPC5XXX_GPIO_WKUP_6
21   -#define FLASH_RBY MPC5XXX_GPIO_WKUP_7
22   -#define UART_EN1 MPC5XXX_GPIO_WKUP_PSC1_4
23   -#define LAN_PRSNT MPC5XXX_GPIO_WKUP_PSC2_4
24   -
25   -#define SIMPLE_DDR (FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI |\
26   - S_FPGA_CCLK)
27   -#define SIMPLE_DVO (FPGA_CONFIG)
28   -#define SIMPLE_ODE (FPGA_CONFIG)
29   -#define SIMPLE_GPIOEN (FPGA_DIN | FPGA_CCLK | FPGA_DONE | FPGA_CONFIG |\
30   - S_FPGA_CCLK | S_FPGA_DONE | WD_WDI | COP_PRESENT)
31   -
32   -#define SINT_ODE 0x1
33   -#define SINT_DDR 0x3
34   -#define SINT_DVO 0x1
35   -#define SINT_INTEN 0
36   -#define SINT_ITYPE 0
37   -#define SINT_GPIOEN (FPGA_STATUS | S_FPGA_DIN | S_FPGA_CONFIG)
38   -
39   -#define WKUP_ODE (MAN_RST | S_FPGA_STATUS)
40   -#define WKUP_DIR (MAN_RST | WD_TS | S_FPGA_STATUS)
41   -#define WKUP_DO (MAN_RST | WD_TS | S_FPGA_STATUS)
42   -#define WKUP_EN (MAN_RST | WD_TS | S_FPGA_STATUS | SERVICE_MODE |\
43   - FLASH_RBY | UART_EN1 | LAN_PRSNT)
board/matrix_vision/mvsmr/u-boot.lds
View file @ af55e35
1   -/*
2   - * (C) Copyright 2003-2004
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - * (C) Copyright 2010
5   - * Andrรฉ Schwarz, Matrix Vision GmbH, as@matrix-vision.de
6   - *
7   - * SPDX-License-Identifier: GPL-2.0+
8   - */
9   -
10   -OUTPUT_ARCH(powerpc)
11   -
12   -SECTIONS
13   -{
14   - /* Read-only sections, merged into text segment: */
15   - .text :
16   - {
17   - /* WARNING - the following is hand-optimized to fit within */
18   - /* the first two sectors (=8KB) of our S29GL flash chip */
19   - arch/powerpc/cpu/mpc5xxx/start.o (.text*)
20   - arch/powerpc/cpu/mpc5xxx/traps.o (.text*)
21   - board/matrix_vision/common/built-in.o (.text*)
22   -
23   - /* This is only needed to force failure if size of above code will ever */
24   - /* increase and grow into reserved space. */
25   - . = ALIGN(0x2000); /* location counter has to be 0x4000 now */
26   - . += 0x4000; /* ->0x8000, i.e. move to env_offset */
27   -
28   - . = env_offset; /* ld error as soon as above ALIGN misplaces lc */
29   - common/env_embedded.o (.ppcenv)
30   -
31   - *(.text*)
32   - . = ALIGN(16);
33   - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
34   - }
35   -
36   - /* Read-write section, merged into data segment: */
37   - . = (. + 0x0FFF) & 0xFFFFF000;
38   - _erotext = .;
39   - PROVIDE (erotext = .);
40   - .reloc :
41   - {
42   - _GOT2_TABLE_ = .;
43   - KEEP(*(.got2))
44   - KEEP(*(.got))
45   - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
46   - _FIXUP_TABLE_ = .;
47   - KEEP(*(.fixup))
48   - }
49   - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
50   - __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
51   -
52   - .data :
53   - {
54   - *(.data*)
55   - *(.sdata*)
56   - }
57   - _edata = .;
58   - PROVIDE (edata = .);
59   -
60   - . = .;
61   -
62   - . = ALIGN(4);
63   - .u_boot_list : {
64   - KEEP(*(SORT(.u_boot_list*)));
65   - }
66   -
67   -
68   - . = .;
69   - __start___ex_table = .;
70   - __ex_table : { *(__ex_table) }
71   - __stop___ex_table = .;
72   -
73   - . = ALIGN(4096);
74   - __init_begin = .;
75   - .text.init : { *(.text.init) }
76   - .data.init : { *(.data.init) }
77   - . = ALIGN(4096);
78   - __init_end = .;
79   -
80   - __bss_start = .;
81   - .bss (NOLOAD) :
82   - {
83   - *(.bss*)
84   - *(.sbss*)
85   - . = ALIGN(4);
86   - }
87   - __bss_end = . ;
88   - PROVIDE (end = .);
89   -}
configs/MVBC_P_defconfig
View file @ af55e35
1   -CONFIG_SYS_EXTRA_OPTIONS="MVBC_P"
2   -CONFIG_PPC=y
3   -CONFIG_MPC5xxx=y
4   -CONFIG_TARGET_MVBC_P=y
configs/MVSMR_defconfig
View file @ af55e35
1   -CONFIG_PPC=y
2   -CONFIG_MPC5xxx=y
3   -CONFIG_TARGET_MVSMR=y
doc/README.scrapyard
Diff comments   View file @ af55e35
... ... @@ -12,6 +12,8 @@
12 12  
13 13 Board Arch CPU Commit Removed Last known maintainer/contact
14 14 =================================================================================================
  15 +MVBC_P powerpc mpc5xxx - - Andre Schwarz <andre.schwarz@matrix-vision.de>
  16 +MVSMR powerpc mpc5xxx - - Andre Schwarz <andre.schwarz@matrix-vision.de>
15 17 MERGERBOX powerpc mpc83xx - - Andre Schwarz <andre.schwarz@matrix-vision.de>
16 18 MVBLM7 powerpc mpc83xx - - Andre Schwarz <andre.schwarz@matrix-vision.de>
17 19 bluestone powerpc ppc4xx - - Tirumala Marri <tmarri@apm.com>
include/configs/MVBC_P.h
View file @ af55e35
1   -/*
2   - * (C) Copyright 2003-2004
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * (C) Copyright 2004-2008
6   - * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
7   - *
8   - * SPDX-License-Identifier: GPL-2.0+
9   - */
10   -
11   -#ifndef __CONFIG_H
12   -#define __CONFIG_H
13   -
14   -#include <version.h>
15   -
16   -#define CONFIG_MPC5200 1
17   -
18   -#ifndef CONFIG_SYS_TEXT_BASE
19   -#define CONFIG_SYS_TEXT_BASE 0xFF800000
20   -#endif
21   -
22   -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
23   -
24   -#define CONFIG_MISC_INIT_R 1
25   -
26   -#define CONFIG_SYS_CACHELINE_SIZE 32
27   -#ifdef CONFIG_CMD_KGDB
28   -#define CONFIG_SYS_CACHELINE_SHIFT 5
29   -#endif
30   -
31   -#define CONFIG_PSC_CONSOLE 1
32   -#define CONFIG_BAUDRATE 115200
33   -#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200, 230400}
34   -
35   -#define CONFIG_PCI 1
36   -#define CONFIG_PCI_PNP 1
37   -#undef CONFIG_PCI_SCAN_SHOW
38   -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
39   -
40   -#define CONFIG_PCI_MEM_BUS 0x40000000
41   -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
42   -#define CONFIG_PCI_MEM_SIZE 0x10000000
43   -
44   -#define CONFIG_PCI_IO_BUS 0x50000000
45   -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
46   -#define CONFIG_PCI_IO_SIZE 0x01000000
47   -
48   -#define CONFIG_SYS_XLB_PIPELINING 1
49   -#define CONFIG_HIGH_BATS 1
50   -
51   -#define MV_CI mvBlueCOUGAR-P
52   -#define MV_VCI mvBlueCOUGAR-P
53   -#define MV_FPGA_DATA 0xff860000
54   -#define MV_FPGA_SIZE 0
55   -#define MV_KERNEL_ADDR 0xffd00000
56   -#define MV_INITRD_ADDR 0xff900000
57   -#define MV_INITRD_LENGTH 0x00400000
58   -#define MV_SCRATCH_ADDR 0x00000000
59   -#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH
60   -#define MV_SCRIPT_ADDR 0xff840000
61   -#define MV_SCRIPT_ADDR2 0xff850000
62   -#define MV_DTB_ADDR 0xfffc0000
63   -
64   -#define CONFIG_SHOW_BOOT_PROGRESS 1
65   -
66   -#define MV_KERNEL_ADDR_RAM 0x00100000
67   -#define MV_DTB_ADDR_RAM 0x00600000
68   -#define MV_INITRD_ADDR_RAM 0x01000000
69   -
70   -/* pass open firmware flat tree */
71   -#define CONFIG_OF_LIBFDT 1
72   -#define CONFIG_OF_BOARD_SETUP 1
73   -
74   -#define OF_CPU "PowerPC,5200@0"
75   -#define OF_SOC "soc5200@f0000000"
76   -#define OF_TBCLK (bd->bi_busfreq / 4)
77   -#define MV_DTB_NAME mvbc-p.dtb
78   -#define CONFIG_OF_STDOUT_VIA_ALIAS 1
79   -
80   -/*
81   - * Supported commands
82   - */
83   -#include <config_cmd_default.h>
84   -
85   -#define CONFIG_CMD_CACHE
86   -#define CONFIG_CMD_NET
87   -#define CONFIG_CMD_PING
88   -#define CONFIG_CMD_DHCP
89   -#define CONFIG_CMD_SDRAM
90   -#define CONFIG_CMD_PCI
91   -#define CONFIG_CMD_FPGA
92   -#define CONFIG_CMD_FPGA_LOADMK
93   -#define CONFIG_CMD_I2C
94   -
95   -#undef CONFIG_WATCHDOG
96   -
97   -#define CONFIG_BOOTP_VENDOREX
98   -#define CONFIG_BOOTP_SUBNETMASK
99   -#define CONFIG_BOOTP_GATEWAY
100   -#define CONFIG_BOOTP_DNS
101   -#define CONFIG_BOOTP_DNS2
102   -#define CONFIG_BOOTP_HOSTNAME
103   -#define CONFIG_BOOTP_BOOTFILESIZE
104   -#define CONFIG_BOOTP_BOOTPATH
105   -#define CONFIG_BOOTP_NTPSERVER
106   -#define CONFIG_BOOTP_RANDOM_DELAY
107   -#define CONFIG_BOOTP_SEND_HOSTNAME
108   -#define CONFIG_LIB_RAND
109   -
110   -/*
111   - * Autoboot
112   - */
113   -#define CONFIG_BOOTDELAY 2
114   -#define CONFIG_AUTOBOOT_KEYED
115   -#define CONFIG_AUTOBOOT_STOP_STR "s"
116   -#define CONFIG_ZERO_BOOTDELAY_CHECK
117   -#define CONFIG_RESET_TO_RETRY 1000
118   -
119   -#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; \
120   - then source ${script_addr}; \
121   - else source ${script_addr2}; \
122   - fi;"
123   -
124   -#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
125   -#define CONFIG_ENV_OVERWRITE
126   -
127   -#define CONFIG_EXTRA_ENV_SETTINGS \
128   - "console_nr=0\0" \
129   - "console=yes\0" \
130   - "stdin=serial\0" \
131   - "stdout=serial\0" \
132   - "stderr=serial\0" \
133   - "fpga=0\0" \
134   - "fpgadata=" __stringify(MV_FPGA_DATA) "\0" \
135   - "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \
136   - "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \
137   - "script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0" \
138   - "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \
139   - "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \
140   - "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \
141   - "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \
142   - "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \
143   - "mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0" \
144   - "mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0" \
145   - "dtb_name=" __stringify(MV_DTB_NAME) "\0" \
146   - "mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0" \
147   - "mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0" \
148   - "mv_version=" U_BOOT_VERSION "\0" \
149   - "dhcp_client_id=" __stringify(MV_CI) "\0" \
150   - "dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0" \
151   - "netretry=no\0" \
152   - "use_static_ipaddr=no\0" \
153   - "static_ipaddr=192.168.90.10\0" \
154   - "static_netmask=255.255.255.0\0" \
155   - "static_gateway=0.0.0.0\0" \
156   - "initrd_name=uInitrd.mvbc-p-rfs\0" \
157   - "zcip=no\0" \
158   - "netboot=yes\0" \
159   - "mvtest=Ff\0" \
160   - "tried_bootfromflash=no\0" \
161   - "tried_bootfromnet=no\0" \
162   - "use_dhcp=yes\0" \
163   - "gev_start=yes\0" \
164   - "mvbcdma_debug=0\0" \
165   - "mvbcia_debug=0\0" \
166   - "propdev_debug=0\0" \
167   - "gevss_debug=0\0" \
168   - "watchdog=1\0" \
169   - "sensor_cnt=1\0" \
170   - ""
171   -
172   -/*
173   - * IPB Bus clocking configuration.
174   - */
175   -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
176   -#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
177   -
178   -/*
179   - * Flash configuration
180   - */
181   -#undef CONFIG_FLASH_16BIT
182   -#define CONFIG_SYS_FLASH_CFI
183   -#define CONFIG_FLASH_CFI_DRIVER
184   -#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
185   -#define CONFIG_SYS_FLASH_EMPTY_INFO
186   -
187   -#define CONFIG_SYS_FLASH_ERASE_TOUT 50000
188   -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
189   -
190   -#define CONFIG_SYS_MAX_FLASH_BANKS 1
191   -#define CONFIG_SYS_MAX_FLASH_SECT 256
192   -
193   -#define CONFIG_SYS_LOWBOOT
194   -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
195   -#define CONFIG_SYS_FLASH_SIZE 0x00800000
196   -
197   -/*
198   - * Environment settings
199   - */
200   -#define CONFIG_ENV_IS_IN_FLASH
201   -#undef CONFIG_SYS_FLASH_PROTECTION
202   -
203   -#define CONFIG_ENV_ADDR 0xFFFE0000
204   -#define CONFIG_ENV_SIZE 0x10000
205   -#define CONFIG_ENV_SECT_SIZE 0x10000
206   -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
207   -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
208   -
209   -/*
210   - * Memory map
211   - */
212   -#define CONFIG_SYS_MBAR 0xF0000000
213   -#define CONFIG_SYS_SDRAM_BASE 0x00000000
214   -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
215   -
216   -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
217   -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
218   -
219   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
220   -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
221   -
222   -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
223   -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
224   -#define CONFIG_SYS_RAMBOOT 1
225   -#endif
226   -
227   -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
228   -#define CONFIG_SYS_MONITOR_LEN (512 << 10)
229   -#define CONFIG_SYS_MALLOC_LEN (512 << 10)
230   -#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
231   -
232   -/*
233   - * I2C configuration
234   - */
235   -#define CONFIG_HARD_I2C 1
236   -#define CONFIG_SYS_I2C_MODULE 1
237   -#define CONFIG_SYS_I2C_SPEED 86000
238   -#define CONFIG_SYS_I2C_SLAVE 0x7F
239   -
240   -/*
241   - * Ethernet configuration
242   - */
243   -#define CONFIG_NET_RETRY_COUNT 5
244   -
245   -#define CONFIG_E1000
246   -#define CONFIG_E1000_FALLBACK_MAC { 0xb6, 0xb4, 0x45, 0xeb, 0xfb, 0xc0 }
247   -#undef CONFIG_MPC5xxx_FEC
248   -#undef CONFIG_PHY_ADDR
249   -#define CONFIG_NETDEV eth0
250   -
251   -/*
252   - * Miscellaneous configurable options
253   - */
254   -#define CONFIG_SYS_HUSH_PARSER
255   -#define CONFIG_CMDLINE_EDITING
256   -#undef CONFIG_SYS_LONGHELP
257   -#ifdef CONFIG_CMD_KGDB
258   -#define CONFIG_SYS_CBSIZE 1024
259   -#else
260   -#define CONFIG_SYS_CBSIZE 256
261   -#endif
262   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
263   -#define CONFIG_SYS_MAXARGS 16
264   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
265   -
266   -#define CONFIG_SYS_MEMTEST_START 0x00800000
267   -#define CONFIG_SYS_MEMTEST_END 0x02f00000
268   -
269   -/* default load address */
270   -#define CONFIG_SYS_LOAD_ADDR 0x02000000
271   -/* default location for tftp and bootm */
272   -#define CONFIG_LOADADDR 0x00200000
273   -
274   -/*
275   - * Various low-level settings
276   - */
277   -#define CONFIG_SYS_GPS_PORT_CONFIG 0x20000004
278   -
279   -#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
280   -#define CONFIG_SYS_HID0_FINAL HID0_ICE
281   -
282   -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
283   -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
284   -#define CONFIG_SYS_BOOTCS_CFG 0x00047800
285   -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
286   -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
287   -
288   -#define CONFIG_SYS_CS_BURST 0x000000f0
289   -#define CONFIG_SYS_CS_DEADCYCLE 0x33333303
290   -
291   -#define CONFIG_SYS_RESET_ADDRESS 0x00000100
292   -
293   -#undef FPGA_DEBUG
294   -#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
295   -#define CONFIG_FPGA
296   -#define CONFIG_FPGA_ALTERA 1
297   -#define CONFIG_FPGA_CYCLON2 1
298   -#define CONFIG_FPGA_COUNT 1
299   -
300   -#endif
include/configs/MVSMR.h
View file @ af55e35
1   -/*
2   - * (C) Copyright 2003-2004
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * (C) Copyright 2004-2010
6   - * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
7   - *
8   - * SPDX-License-Identifier: GPL-2.0+
9   - */
10   -
11   -#ifndef __CONFIG_H
12   -#define __CONFIG_H
13   -
14   -#include <version.h>
15   -
16   -#define CONFIG_MPC5200 1
17   -
18   -#ifndef CONFIG_SYS_TEXT_BASE
19   -#define CONFIG_SYS_TEXT_BASE 0xFF800000
20   -#endif
21   -#define CONFIG_SYS_LDSCRIPT "board/matrix_vision/mvsmr/u-boot.lds"
22   -
23   -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
24   -
25   -#define CONFIG_MISC_INIT_R 1
26   -
27   -#define CONFIG_SYS_CACHELINE_SIZE 32
28   -#ifdef CONFIG_CMD_KGDB
29   -#define CONFIG_SYS_CACHELINE_SHIFT 5
30   -#endif
31   -
32   -#define CONFIG_PSC_CONSOLE 1
33   -#define CONFIG_BAUDRATE 115200
34   -#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200,\
35   - 230400}
36   -
37   -#define CONFIG_PCI 1
38   -#define CONFIG_PCI_PNP 1
39   -#undef CONFIG_PCI_SCAN_SHOW
40   -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
41   -
42   -#define CONFIG_PCI_MEM_BUS 0x40000000
43   -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
44   -#define CONFIG_PCI_MEM_SIZE 0x10000000
45   -
46   -#define CONFIG_PCI_IO_BUS 0x50000000
47   -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
48   -#define CONFIG_PCI_IO_SIZE 0x01000000
49   -
50   -#define CONFIG_SYS_XLB_PIPELINING 1
51   -#define CONFIG_HIGH_BATS 1
52   -
53   -#define MV_CI mvSMR
54   -#define MV_VCI mvSMR
55   -#define MV_FPGA_DATA 0xff840000
56   -#define MV_FPGA_SIZE 0x1ff88
57   -#define MV_KERNEL_ADDR 0xfff00000
58   -#define MV_SCRIPT_ADDR 0xff806000
59   -#define MV_INITRD_ADDR 0xff880000
60   -#define MV_INITRD_LENGTH 0x00240000
61   -#define MV_SCRATCH_ADDR 0xffcc0000
62   -#define MV_SCRATCH_LENGTH MV_INITRD_LENGTH
63   -
64   -#define CONFIG_SHOW_BOOT_PROGRESS 1
65   -
66   -#define MV_KERNEL_ADDR_RAM 0x00100000
67   -#define MV_INITRD_ADDR_RAM 0x00400000
68   -
69   -/*
70   - * Supported commands
71   - */
72   -#include <config_cmd_default.h>
73   -
74   -#define CONFIG_CMD_CACHE
75   -#define CONFIG_CMD_DHCP
76   -#define CONFIG_CMD_FPGA
77   -#define CONFIG_CMD_FPGA_LOADMK
78   -#define CONFIG_CMD_I2C
79   -#define CONFIG_CMD_MII
80   -#define CONFIG_CMD_NET
81   -#define CONFIG_CMD_PCI
82   -#define CONFIG_CMD_PING
83   -#define CONFIG_CMD_SDRAM
84   -
85   -#define CONFIG_BOOTP_BOOTFILESIZE
86   -#define CONFIG_BOOTP_BOOTPATH
87   -#define CONFIG_BOOTP_DNS
88   -#define CONFIG_BOOTP_DNS2
89   -#define CONFIG_BOOTP_GATEWAY
90   -#define CONFIG_BOOTP_HOSTNAME
91   -#define CONFIG_BOOTP_NTPSERVER
92   -#define CONFIG_BOOTP_RANDOM_DELAY
93   -#define CONFIG_BOOTP_SEND_HOSTNAME
94   -#define CONFIG_BOOTP_SUBNETMASK
95   -#define CONFIG_BOOTP_VENDOREX
96   -#define CONFIG_LIB_RAND
97   -
98   -/*
99   - * Autoboot
100   - */
101   -#define CONFIG_BOOTDELAY 1
102   -#define CONFIG_AUTOBOOT_KEYED
103   -#define CONFIG_AUTOBOOT_STOP_STR "abcdefg"
104   -#define CONFIG_ZERO_BOOTDELAY_CHECK
105   -
106   -#define CONFIG_BOOTCOMMAND "source ${script_addr}"
107   -#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" \
108   - " allocate=6M"
109   -
110   -#define CONFIG_EXTRA_ENV_SETTINGS \
111   - "console_nr=0\0" \
112   - "console=no\0" \
113   - "stdin=serial\0" \
114   - "stdout=serial\0" \
115   - "stderr=serial\0" \
116   - "fpga=0\0" \
117   - "fpgadata=" __stringify(MV_FPGA_DATA) "\0" \
118   - "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \
119   - "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \
120   - "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \
121   - "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \
122   - "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \
123   - "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \
124   - "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \
125   - "mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0" \
126   - "mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0" \
127   - "mv_version=" U_BOOT_VERSION "\0" \
128   - "dhcp_client_id=" __stringify(MV_CI) "\0" \
129   - "dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0" \
130   - "netretry=no\0" \
131   - "use_static_ipaddr=no\0" \
132   - "static_ipaddr=192.168.0.101\0" \
133   - "static_netmask=255.255.255.0\0" \
134   - "static_gateway=0.0.0.0\0" \
135   - "initrd_name=uInitrd.mvsmr-rfs\0" \
136   - "zcip=yes\0" \
137   - "netboot=no\0" \
138   - ""
139   -
140   -/*
141   - * IPB Bus clocking configuration.
142   - */
143   -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
144   -
145   -/*
146   - * Flash configuration
147   - */
148   -#undef CONFIG_FLASH_16BIT
149   -#define CONFIG_SYS_FLASH_CFI
150   -#define CONFIG_FLASH_CFI_DRIVER
151   -#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
152   -#define CONFIG_SYS_FLASH_EMPTY_INFO
153   -
154   -#define CONFIG_SYS_FLASH_ERASE_TOUT 50000
155   -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
156   -
157   -#define CONFIG_SYS_MAX_FLASH_BANKS 1
158   -#define CONFIG_SYS_MAX_FLASH_SECT 256
159   -
160   -#define CONFIG_SYS_LOWBOOT
161   -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
162   -#define CONFIG_SYS_FLASH_SIZE 0x00800000
163   -
164   -/*
165   - * Environment settings
166   - */
167   -#define CONFIG_ENV_IS_IN_FLASH
168   -#undef CONFIG_SYS_FLASH_PROTECTION
169   -#define CONFIG_OVERWRITE_ETHADDR_ONCE
170   -
171   -#define CONFIG_ENV_OFFSET 0x8000
172   -#define CONFIG_ENV_SIZE 0x2000
173   -#define CONFIG_ENV_SECT_SIZE 0x2000
174   -
175   -/* used by linker script to wrap code around */
176   -#define CONFIG_SCRIPT_OFFSET 0x6000
177   -#define CONFIG_SCRIPT_SECT_SIZE 0x2000
178   -
179   -/*
180   - * Memory map
181   - */
182   -#define CONFIG_SYS_MBAR 0xF0000000
183   -#define CONFIG_SYS_SDRAM_BASE 0x00000000
184   -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
185   -
186   -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
187   -#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
188   -
189   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
190   - GENERATED_GBL_DATA_SIZE)
191   -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
192   -
193   -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
194   -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
195   -#define CONFIG_SYS_RAMBOOT 1
196   -#endif
197   -
198   -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
199   -#define CONFIG_SYS_MONITOR_LEN (512 << 10)
200   -#define CONFIG_SYS_MALLOC_LEN (512 << 10)
201   -#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
202   -
203   -/*
204   - * I2C configuration
205   - */
206   -#define CONFIG_HARD_I2C 1
207   -#define CONFIG_SYS_I2C_MODULE 1
208   -#define CONFIG_SYS_I2C_SPEED 86000
209   -#define CONFIG_SYS_I2C_SLAVE 0x7F
210   -
211   -/*
212   - * Ethernet configuration
213   - */
214   -#define CONFIG_NET_RETRY_COUNT 5
215   -
216   -#define CONFIG_MPC5xxx_FEC
217   -#define CONFIG_MPC5xxx_FEC_MII100
218   -#define CONFIG_PHY_ADDR 0x00
219   -#define CONFIG_NETDEV eth0
220   -
221   -/*
222   - * Miscellaneous configurable options
223   - */
224   -#define CONFIG_SYS_HUSH_PARSER
225   -#define CONFIG_CMDLINE_EDITING
226   -#undef CONFIG_SYS_LONGHELP
227   -#ifdef CONFIG_CMD_KGDB
228   -#define CONFIG_SYS_CBSIZE 1024
229   -#else
230   -#define CONFIG_SYS_CBSIZE 256
231   -#endif
232   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
233   -#define CONFIG_SYS_MAXARGS 16
234   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
235   -
236   -#define CONFIG_SYS_MEMTEST_START 0x00800000
237   -#define CONFIG_SYS_MEMTEST_END 0x02f00000
238   -
239   -/* default load address */
240   -#define CONFIG_SYS_LOAD_ADDR 0x02000000
241   -/* default location for tftp and bootm */
242   -#define CONFIG_LOADADDR 0x00200000
243   -
244   -/*
245   - * Various low-level settings
246   - */
247   -#define CONFIG_SYS_GPS_PORT_CONFIG 0x00050044
248   -
249   -#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
250   -#define CONFIG_SYS_HID0_FINAL HID0_ICE
251   -
252   -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
253   -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
254   -#define CONFIG_SYS_BOOTCS_CFG 0x00047800
255   -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
256   -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
257   -
258   -#define CONFIG_SYS_CS_BURST 0x000000f0
259   -#define CONFIG_SYS_CS_DEADCYCLE 0x33333303
260   -
261   -#define CONFIG_SYS_RESET_ADDRESS 0x00000100
262   -
263   -#undef FPGA_DEBUG
264   -#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
265   -#define CONFIG_FPGA
266   -#define CONFIG_FPGA_XILINX 1
267   -#define CONFIG_FPGA_SPARTAN2 1
268   -#define CONFIG_FPGA_COUNT 1
269   -
270   -#endif