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Commit af5b9b1f789d600cf0d996f1a5e80eb8b38f4264

Authored by Albert ARIBAUD
1 parent 4efd69250f
Exists in master and in 50 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

mini2440: remove board support 

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>

Showing 6 changed files with 3 additions and 301 deletions Side-by-side Diff

board/friendlyarm/mini2440/Makefile
View file @ af5b9b1
1   -#
2   -# (C) Copyright 2012
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -obj-y := mini2440.o
board/friendlyarm/mini2440/mini2440.c
View file @ af5b9b1
1   -/*
2   - * (C) Copyright 2002
3   - * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4   - * Marius Groeger <mgroeger@sysgo.de>
5   - *
6   - * (C) Copyright 2002
7   - * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
8   - *
9   - * (C) Copyright 2009
10   - * Michel Pollet <buserror@gmail.com>
11   - *
12   - * (C) Copyright 2012
13   - * Gabriel Huau <contact@huau-gabriel.fr>
14   - *
15   - * SPDX-License-Identifier: GPL-2.0+
16   - */
17   -
18   -#include <common.h>
19   -#include <asm/arch/s3c2440.h>
20   -#include <asm/arch/iomux.h>
21   -#include <asm/arch/gpio.h>
22   -#include <asm/io.h>
23   -#include <asm/gpio.h>
24   -#include <netdev.h>
25   -#include "mini2440.h"
26   -
27   -DECLARE_GLOBAL_DATA_PTR;
28   -
29   -static inline void pll_delay(unsigned long loops)
30   -{
31   - __asm__ volatile ("1:\n"
32   - "subs %0, %1, #1\n"
33   - "bne 1b" : "=r" (loops) : "0" (loops));
34   -}
35   -
36   -int board_early_init_f(void)
37   -{
38   - struct s3c24x0_clock_power * const clk_power =
39   - s3c24x0_get_base_clock_power();
40   -
41   - /* to reduce PLL lock time, adjust the LOCKTIME register */
42   - clk_power->locktime = 0xFFFFFF; /* Max PLL Lock time count */
43   - clk_power->clkdivn = CLKDIVN_VAL;
44   -
45   - /* configure UPLL */
46   - clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
47   - /* some delay between MPLL and UPLL */
48   - pll_delay(100);
49   -
50   - /* configure MPLL */
51   - clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
52   -
53   - /* some delay between MPLL and UPLL */
54   - pll_delay(10000);
55   -
56   - return 0;
57   -}
58   -
59   -/*
60   - * Miscellaneous platform dependent initialisations
61   - */
62   -int board_init(void)
63   -{
64   - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
65   -
66   - /* IOMUX Port H : UART Configuration */
67   - gpio->gphcon = IOMUXH_nCTS0 | IOMUXH_nRTS0 | IOMUXH_TXD0 | IOMUXH_RXD0 |
68   - IOMUXH_TXD1 | IOMUXH_RXD1 | IOMUXH_TXD2 | IOMUXH_RXD2;
69   -
70   - gpio_direction_output(GPH8, 0);
71   - gpio_direction_output(GPH9, 0);
72   - gpio_direction_output(GPH10, 0);
73   -
74   - /* adress of boot parameters */
75   - gd->bd->bi_boot_params = CONFIG_BOOT_PARAM_ADDR;
76   -
77   - return 0;
78   -}
79   -
80   -int dram_init(void)
81   -{
82   - struct s3c24x0_memctl *memctl = s3c24x0_get_base_memctl();
83   -
84   - /*
85   - * Configuring bus width and timing
86   - * Initialize clocks for each bank 0..5
87   - * Bank 3 and 4 are used for DM9000
88   - */
89   - writel(BANK_CONF, &memctl->bwscon);
90   - writel(B0_CONF, &memctl->bankcon[0]);
91   - writel(B1_CONF, &memctl->bankcon[1]);
92   - writel(B2_CONF, &memctl->bankcon[2]);
93   - writel(B3_CONF, &memctl->bankcon[3]);
94   - writel(B4_CONF, &memctl->bankcon[4]);
95   - writel(B5_CONF, &memctl->bankcon[5]);
96   -
97   - /* Bank 6 and 7 are used for DRAM */
98   - writel(SDRAM_64MB, &memctl->bankcon[6]);
99   - writel(SDRAM_64MB, &memctl->bankcon[7]);
100   -
101   - writel(MEM_TIMING, &memctl->refresh);
102   - writel(BANKSIZE_CONF, &memctl->banksize);
103   - writel(B6_MRSR, &memctl->mrsrb6);
104   - writel(B7_MRSR, &memctl->mrsrb7);
105   -
106   - gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
107   - PHYS_SDRAM_SIZE);
108   - return 0;
109   -}
110   -
111   -int board_eth_init(bd_t *bis)
112   -{
113   -#ifdef CONFIG_DRIVER_DM9000
114   - return dm9000_initialize(bis);
115   -#else
116   - return 0;
117   -#endif
118   -}
board/friendlyarm/mini2440/mini2440.h
View file @ af5b9b1
1   -#ifndef __MINI2440_BOARD_CONF_H__
2   -#define __MINI2440_BOARD_CONF_H__
3   -
4   -/* PLL Parameters */
5   -#define CLKDIVN_VAL 7
6   -#define M_MDIV 0x7f
7   -#define M_PDIV 0x2
8   -#define M_SDIV 0x1
9   -
10   -#define U_M_MDIV 0x38
11   -#define U_M_PDIV 0x2
12   -#define U_M_SDIV 0x2
13   -
14   -/* BWSCON */
15   -#define DW8 0x0
16   -#define DW16 0x1
17   -#define DW32 0x2
18   -#define WAIT (0x1<<2)
19   -#define UBLB (0x1<<3)
20   -
21   -#define B1_BWSCON (DW32)
22   -#define B2_BWSCON (DW16)
23   -#define B3_BWSCON (DW16 + WAIT + UBLB)
24   -#define B4_BWSCON (DW16 + WAIT + UBLB)
25   -#define B5_BWSCON (DW16)
26   -#define B6_BWSCON (DW32)
27   -#define B7_BWSCON (DW32)
28   -
29   -/*
30   - * Bank Configuration
31   - */
32   -#define B0_Tacs 0x0 /* 0clk */
33   -#define B0_Tcos 0x0 /* 0clk */
34   -#define B0_Tacc 0x7 /* 14clk */
35   -#define B0_Tcoh 0x0 /* 0clk */
36   -#define B0_Tah 0x0 /* 0clk */
37   -#define B0_Tacp 0x0 /* 0clk */
38   -#define B0_PMC 0x0 /* normal */
39   -
40   -#define B1_Tacs 0x0
41   -#define B1_Tcos 0x0
42   -#define B1_Tacc 0x7
43   -#define B1_Tcoh 0x0
44   -#define B1_Tah 0x0
45   -#define B1_Tacp 0x0
46   -#define B1_PMC 0x0
47   -
48   -#define B2_Tacs 0x0
49   -#define B2_Tcos 0x0
50   -#define B2_Tacc 0x7
51   -#define B2_Tcoh 0x0
52   -#define B2_Tah 0x0
53   -#define B2_Tacp 0x0
54   -#define B2_PMC 0x0
55   -
56   -#define B3_Tacs 0x0
57   -#define B3_Tcos 0x3 /* 4clk */
58   -#define B3_Tacc 0x7
59   -#define B3_Tcoh 0x1 /* 1clk */
60   -#define B3_Tah 0x3 /* 4clk */
61   -#define B3_Tacp 0x0
62   -#define B3_PMC 0x0
63   -
64   -#define B4_Tacs 0x0
65   -#define B4_Tcos 0x3
66   -#define B4_Tacc 0x7
67   -#define B4_Tcoh 0x1
68   -#define B4_Tah 0x3
69   -#define B4_Tacp 0x0
70   -#define B4_PMC 0x0
71   -
72   -#define B5_Tacs 0x0
73   -#define B5_Tcos 0x0
74   -#define B5_Tacc 0x7
75   -#define B5_Tcoh 0x0
76   -#define B5_Tah 0x0
77   -#define B5_Tacp 0x0
78   -#define B5_PMC 0x0
79   -
80   -/*
81   - * SDRAM Configuration
82   - */
83   -#define SDRAM_MT 0x3 /* SDRAM */
84   -#define SDRAM_Trcd 0x0 /* 2clk */
85   -#define SDRAM_SCAN_9 0x1 /* 9bit */
86   -#define SDRAM_SCAN_10 0x2 /* 10bit */
87   -
88   -#define SDRAM_64MB ((SDRAM_MT<<15) + (SDRAM_Trcd<<2) + (SDRAM_SCAN_9))
89   -
90   -/*
91   - * Refresh Parameter
92   - */
93   -#define REFEN 0x1 /* Refresh enable */
94   -#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
95   -#define Trp 0x1 /* 3clk */
96   -#define Trc 0x3 /* 7clk */
97   -#define Tchr 0x0 /* unused */
98   -#define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048 + 1-10.37*100) */
99   -
100   -/*
101   - * MRSR Parameter
102   - */
103   -#define BL 0x0
104   -#define BT 0x0
105   -#define CL 0x3 /* 3 clocks */
106   -#define TM 0x0
107   -#define WBL 0x0
108   -
109   -/*
110   - * BankSize Parameter
111   - */
112   -#define BK76MAP 0x2 /* 128MB/128MB */
113   -#define SCLK_EN 0x1 /* SCLK active */
114   -#define SCKE_EN 0x1 /* SDRAM power down mode enable */
115   -#define BURST_EN 0x1 /* Burst enable */
116   -
117   -/*
118   - * Register values
119   - */
120   -#define BANK_CONF ((0 + (B1_BWSCON<<4) + (B2_BWSCON<<8) + (B3_BWSCON<<12) + \
121   - (B4_BWSCON<<16) + (B5_BWSCON<<20) + (B6_BWSCON<<24) + \
122   - (B7_BWSCON<<28)))
123   -
124   -#define B0_CONF ((B0_Tacs<<13) + (B0_Tcos<<11) + (B0_Tacc<<8) + \
125   - (B0_Tcoh<<6) + (B0_Tah<<4) + (B0_Tacp<<2) + (B0_PMC))
126   -#define B1_CONF ((B1_Tacs<<13) + (B1_Tcos<<11) + (B1_Tacc<<8) + \
127   - (B1_Tcoh<<6) + (B1_Tah<<4) + (B1_Tacp<<2) + (B1_PMC))
128   -#define B2_CONF ((B2_Tacs<<13) + (B2_Tcos<<11) + (B2_Tacc<<8) + \
129   - (B2_Tcoh<<6) + (B2_Tah<<4) + (B2_Tacp<<2) + (B2_PMC))
130   -#define B3_CONF ((B3_Tacs<<13) + (B3_Tcos<<11) + (B3_Tacc<<8) + \
131   - (B3_Tcoh<<6) + (B3_Tah<<4) + (B3_Tacp<<2) + (B3_PMC))
132   -#define B4_CONF ((B4_Tacs<<13) + (B4_Tcos<<11) + (B4_Tacc<<8) + \
133   - (B4_Tcoh<<6) + (B4_Tah<<4) + (B4_Tacp<<2) + (B4_PMC))
134   -#define B5_CONF ((B5_Tacs<<13) + (B5_Tcos<<11) + (B5_Tacc<<8) + \
135   - (B5_Tcoh<<6) + (B5_Tah<<4) + (B5_Tacp<<2) + (B5_PMC))
136   -
137   -#define MEM_TIMING (REFEN<<23) + (TREFMD<<22) + (Trp<<20) + \
138   - (Trc<<18) + (Tchr<<16) + REFCNT
139   -
140   -#define BANKSIZE_CONF (BK76MAP) + (SCLK_EN<<4) + (SCKE_EN<<5) + (BURST_EN<<7)
141   -#define B6_MRSR (CL<<4)
142   -#define B7_MRSR (CL<<4)
143   -
144   -#endif
... ... @@ -69,7 +69,6 @@
69 69 Active arm arm920t imx - - scb9328 - Torsten Koschorrek <koschorrek@synertronixx.de>
70 70 Active arm arm920t ks8695 - - cm4008 - Greg Ungerer <greg.ungerer@opengear.com>
71 71 Active arm arm920t ks8695 - - cm41xx - -
72   -Active arm arm920t s3c24x0 friendlyarm mini2440 mini2440 - Gabriel Huau <contact@huau-gabriel.fr>
73 72 Active arm arm920t s3c24x0 mpl vcma9 VCMA9 - David Müller <d.mueller@elsoft.ch>
74 73 Active arm arm920t s3c24x0 samsung - smdk2410 - David Müller <d.mueller@elsoft.ch>
75 74 Active arm arm926ejs - armltd integrator integratorap_cm926ejs integratorap:CM926EJ_S Linus Walleij <linus.walleij@linaro.org>
doc/README.mini2440
View file @ af5b9b1
1   -U-Boot for FriendlyARM Mini2440 (s3c2440)
2   -
3   -This file contains information for the port of U-Boot to FriendlyARM
4   -mini2440
5   -
6   -All information about the board can be found on :
7   -http://www.friendlyarm.net/products/mini2440
8   -
9   -To build u-boot : ./MAKEALL mini2440
10   -
11   -Overview :
12   ---------
13   -FriendlyARM Mini 2440 SBC (Single-Board Computer) with 400 MHz Samsung S3C2440
14   -ARM9 processor. The board measures 100 x 100 mm, ideal for learning about ARM9
15   -systems. It's a low cost board.
16   -
17   -Boot Methods :
18   -------------
19   -Mini2440 can boot from NOR or NAND.
20   -
21   -Build :
22   ------
23   -./MAKEALL mini2440
24   -
25   -or
26   -
27   -make mini2440_config
28   -make
doc/README.scrapyard
Diff comments   View file @ af5b9b1
... ... @@ -11,8 +11,9 @@
11 11  
12 12 Board Arch CPU Commit Removed Last known maintainer/contact
13 13 =================================================================================================
14   -omap730p2 arm arm926ejs - 2013-11-11
15   -pn62 powerpc mpc824x - 2013-11-11 Wolfgang Grandegger <wg@grandegger.com>
  14 +mini2440 arm arm920t - 2014-01-13 Gabriel Huau <contact@huau-gabriel.fr>
  15 +omap730p2 arm arm926ejs 79c5c08d 2013-11-11
  16 +pn62 powerpc mpc824x 649acfe1 2013-11-11 Wolfgang Grandegger <wg@grandegger.com>
16 17 pdnb3 arm ixp 304db0b 2013-09-24 Stefan Roese <sr@denx.de>
17 18 scpu arm ixp 304db0b 2013-09-24 Stefan Roese <sr@denx.de>
18 19 omap1510inn arm arm925t 0610a16 2013-09-23 Kshitij Gupta <kshitij@ti.com>