Commit b03b25caea1ff3a501161f5bc1ad5e5b5b124e0c
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6631db4773
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fpga: Remove all CONFIG_SYS_* fpga related options
All these macros are completely unused by any code. CONFIG_FPGA is not a bitfield anymore. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
Showing 10 changed files with 6 additions and 60 deletions Side-by-side Diff
include/altera.h
| ... | ... | @@ -27,23 +27,6 @@ |
| 27 | 27 | #ifndef _ALTERA_H_ |
| 28 | 28 | #define _ALTERA_H_ |
| 29 | 29 | |
| 30 | -/* Altera Model definitions | |
| 31 | - *********************************************************************/ | |
| 32 | -#define CONFIG_SYS_ACEX1K CONFIG_SYS_FPGA_DEV( 0x1 ) | |
| 33 | -#define CONFIG_SYS_CYCLON2 CONFIG_SYS_FPGA_DEV( 0x2 ) | |
| 34 | -#define CONFIG_SYS_STRATIX_II CONFIG_SYS_FPGA_DEV( 0x4 ) | |
| 35 | - | |
| 36 | -#define CONFIG_SYS_ALTERA_ACEX1K (CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_ACEX1K) | |
| 37 | -#define CONFIG_SYS_ALTERA_CYCLON2 (CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_CYCLON2) | |
| 38 | -#define CONFIG_SYS_ALTERA_STRATIX_II (CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_STRATIX_II) | |
| 39 | -/* Add new models here */ | |
| 40 | - | |
| 41 | -/* Altera Interface definitions | |
| 42 | - *********************************************************************/ | |
| 43 | -#define CONFIG_SYS_ALTERA_IF_PS CONFIG_SYS_FPGA_IF( 0x1 ) /* passive serial */ | |
| 44 | -#define CONFIG_SYS_ALTERA_IF_FPP CONFIG_SYS_FPGA_IF( 0x2 ) /* fast passive parallel */ | |
| 45 | -/* Add new interfaces here */ | |
| 46 | - | |
| 47 | 30 | typedef enum { /* typedef Altera_iface */ |
| 48 | 31 | min_altera_iface_type, /* insert all new types after this */ |
| 49 | 32 | passive_serial, /* serial data and external clock */ |
include/configs/M54455EVB.h
include/configs/MERGERBOX.h
include/configs/MVBC_P.h
include/configs/MVBLM7.h
include/configs/MVSMR.h
include/configs/omap3_mvblx.h
| ... | ... | @@ -273,7 +273,7 @@ |
| 273 | 273 | #endif /* (CONFIG_CMD_NET) */ |
| 274 | 274 | |
| 275 | 275 | #define CONFIG_FPGA_COUNT 1 |
| 276 | -#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2 | |
| 276 | +#define CONFIG_FPGA | |
| 277 | 277 | #define CONFIG_FPGA_ALTERA |
| 278 | 278 | #define CONFIG_FPGA_CYCLON2 |
| 279 | 279 | #define CONFIG_SYS_FPGA_PROG_FEEDBACK |
include/fpga.h
| ... | ... | @@ -31,16 +31,6 @@ |
| 31 | 31 | #define CONFIG_MAX_FPGA_DEVICES 5 |
| 32 | 32 | #endif |
| 33 | 33 | |
| 34 | -/* CONFIG_FPGA bit assignments */ | |
| 35 | -#define CONFIG_SYS_FPGA_MAN(x) (x) | |
| 36 | -#define CONFIG_SYS_FPGA_DEV(x) ((x) << 8 ) | |
| 37 | -#define CONFIG_SYS_FPGA_IF(x) ((x) << 16 ) | |
| 38 | - | |
| 39 | -/* FPGA Manufacturer bits in CONFIG_FPGA */ | |
| 40 | -#define CONFIG_SYS_FPGA_XILINX CONFIG_SYS_FPGA_MAN( 0x1 ) | |
| 41 | -#define CONFIG_SYS_FPGA_ALTERA CONFIG_SYS_FPGA_MAN( 0x2 ) | |
| 42 | - | |
| 43 | - | |
| 44 | 34 | /* fpga_xxxx function return value definitions */ |
| 45 | 35 | #define FPGA_SUCCESS 0 |
| 46 | 36 | #define FPGA_FAIL -1 |
include/lattice.h
| ... | ... | @@ -278,9 +278,6 @@ |
| 278 | 278 | char *desc; /* description string */ |
| 279 | 279 | } Lattice_desc; /* end, typedef Altera_desc */ |
| 280 | 280 | |
| 281 | -/* Lattice Model Type */ | |
| 282 | -#define CONFIG_SYS_XP2 CONFIG_SYS_FPGA_DEV(0x1) | |
| 283 | - | |
| 284 | 281 | /* Board specific implementation specific function types */ |
| 285 | 282 | typedef void (*Lattice_jtag_init)(void); |
| 286 | 283 | typedef void (*Lattice_jtag_set_tdi)(int v); |
include/xilinx.h
| ... | ... | @@ -27,30 +27,6 @@ |
| 27 | 27 | #ifndef _XILINX_H_ |
| 28 | 28 | #define _XILINX_H_ |
| 29 | 29 | |
| 30 | -/* Xilinx Model definitions | |
| 31 | - *********************************************************************/ | |
| 32 | -#define CONFIG_SYS_SPARTAN2 CONFIG_SYS_FPGA_DEV( 0x1 ) | |
| 33 | -#define CONFIG_SYS_VIRTEX_E CONFIG_SYS_FPGA_DEV( 0x2 ) | |
| 34 | -#define CONFIG_SYS_VIRTEX2 CONFIG_SYS_FPGA_DEV( 0x4 ) | |
| 35 | -#define CONFIG_SYS_SPARTAN3 CONFIG_SYS_FPGA_DEV( 0x8 ) | |
| 36 | -#define CONFIG_SYS_ZYNQ CONFIG_SYS_FPGA_DEV(0x10) | |
| 37 | -#define CONFIG_SYS_XILINX_SPARTAN2 (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_SPARTAN2) | |
| 38 | -#define CONFIG_SYS_XILINX_VIRTEX_E (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_VIRTEX_E) | |
| 39 | -#define CONFIG_SYS_XILINX_VIRTEX2 (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_VIRTEX2) | |
| 40 | -#define CONFIG_SYS_XILINX_SPARTAN3 (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_SPARTAN3) | |
| 41 | -#define CONFIG_SYS_XILINX_ZYNQ (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_ZYNQ) | |
| 42 | -/* XXX - Add new models here */ | |
| 43 | - | |
| 44 | - | |
| 45 | -/* Xilinx Interface definitions | |
| 46 | - *********************************************************************/ | |
| 47 | -#define CONFIG_SYS_XILINX_IF_SS CONFIG_SYS_FPGA_IF( 0x1 ) /* slave serial */ | |
| 48 | -#define CONFIG_SYS_XILINX_IF_MS CONFIG_SYS_FPGA_IF( 0x2 ) /* master serial */ | |
| 49 | -#define CONFIG_SYS_XILINX_IF_SP CONFIG_SYS_FPGA_IF( 0x4 ) /* slave parallel */ | |
| 50 | -#define CONFIG_SYS_XILINX_IF_JTAG CONFIG_SYS_FPGA_IF( 0x8 ) /* jtag */ | |
| 51 | -#define CONFIG_SYS_XILINX_IF_MSM CONFIG_SYS_FPGA_IF( 0x10 ) /* master selectmap */ | |
| 52 | -#define CONFIG_SYS_XILINX_IF_SSM CONFIG_SYS_FPGA_IF( 0x20 ) /* slave selectmap */ | |
| 53 | - | |
| 54 | 30 | /* Xilinx types |
| 55 | 31 | *********************************************************************/ |
| 56 | 32 | typedef enum { /* typedef Xilinx_iface */ |